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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.07 98.62 89.36 97.29 95.43 99.25


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1011 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2731898796 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:08 PM PDT 24 14500981 ps
T1012 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2047987374 Jun 26 06:58:03 PM PDT 24 Jun 26 06:58:06 PM PDT 24 19346613 ps
T143 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1502425928 Jun 26 06:57:38 PM PDT 24 Jun 26 06:58:02 PM PDT 24 2096401749 ps
T144 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1009454631 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:05 PM PDT 24 102603663 ps
T1013 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3470316488 Jun 26 06:57:19 PM PDT 24 Jun 26 06:57:21 PM PDT 24 27792396 ps
T164 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.459710507 Jun 26 06:57:53 PM PDT 24 Jun 26 06:58:15 PM PDT 24 602708619 ps
T1014 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2440850524 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:43 PM PDT 24 338853719 ps
T1015 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2007061898 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:08 PM PDT 24 83745261 ps
T1016 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.723853420 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:08 PM PDT 24 15231419 ps
T1017 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3163521912 Jun 26 06:57:20 PM PDT 24 Jun 26 06:57:25 PM PDT 24 28042307 ps
T1018 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1189762881 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:27 PM PDT 24 50570328 ps
T145 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.120748058 Jun 26 06:57:46 PM PDT 24 Jun 26 06:57:49 PM PDT 24 99490055 ps
T1019 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2090983592 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:08 PM PDT 24 28527620 ps
T1020 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2341468235 Jun 26 06:57:24 PM PDT 24 Jun 26 06:57:28 PM PDT 24 15051057 ps
T146 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4280641078 Jun 26 06:57:25 PM PDT 24 Jun 26 06:57:44 PM PDT 24 1244953861 ps
T148 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.66293766 Jun 26 06:57:39 PM PDT 24 Jun 26 06:57:45 PM PDT 24 310465368 ps
T1021 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.267613585 Jun 26 06:57:36 PM PDT 24 Jun 26 06:57:41 PM PDT 24 359347209 ps
T1022 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.601104632 Jun 26 06:57:25 PM PDT 24 Jun 26 06:57:31 PM PDT 24 232884551 ps
T1023 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3696600540 Jun 26 06:58:17 PM PDT 24 Jun 26 06:58:20 PM PDT 24 14771670 ps
T166 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3433697230 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:30 PM PDT 24 1040528266 ps
T1024 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1305880187 Jun 26 06:57:25 PM PDT 24 Jun 26 06:57:29 PM PDT 24 20546296 ps
T1025 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.61394625 Jun 26 06:57:54 PM PDT 24 Jun 26 06:57:58 PM PDT 24 194962000 ps
T1026 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2964622238 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:05 PM PDT 24 15357447 ps
T74 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3917849502 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:26 PM PDT 24 65526905 ps
T1027 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3602308056 Jun 26 06:57:38 PM PDT 24 Jun 26 06:57:45 PM PDT 24 508275681 ps
T1028 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.468649370 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:09 PM PDT 24 91729592 ps
T1029 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3485663627 Jun 26 06:57:50 PM PDT 24 Jun 26 06:57:55 PM PDT 24 268876641 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1997184909 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:33 PM PDT 24 395435892 ps
T1031 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2965118054 Jun 26 06:57:43 PM PDT 24 Jun 26 06:58:05 PM PDT 24 866676202 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1762754956 Jun 26 06:57:28 PM PDT 24 Jun 26 06:57:31 PM PDT 24 32618821 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.269431599 Jun 26 06:57:24 PM PDT 24 Jun 26 06:57:44 PM PDT 24 1143708310 ps
T1034 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2161094158 Jun 26 06:57:50 PM PDT 24 Jun 26 06:58:10 PM PDT 24 7138178479 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2860133453 Jun 26 06:57:50 PM PDT 24 Jun 26 06:57:55 PM PDT 24 140121521 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2393074796 Jun 26 06:57:22 PM PDT 24 Jun 26 06:57:31 PM PDT 24 755448994 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3825097633 Jun 26 06:57:24 PM PDT 24 Jun 26 06:57:28 PM PDT 24 239021400 ps
T161 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.89428731 Jun 26 06:57:52 PM PDT 24 Jun 26 06:57:56 PM PDT 24 261730945 ps
T1038 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2813703688 Jun 26 06:57:46 PM PDT 24 Jun 26 06:57:49 PM PDT 24 27139530 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2243277030 Jun 26 06:57:45 PM PDT 24 Jun 26 06:57:50 PM PDT 24 155504264 ps
T1040 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2365474192 Jun 26 06:57:42 PM PDT 24 Jun 26 06:57:46 PM PDT 24 126828707 ps
T1041 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.210709335 Jun 26 06:57:52 PM PDT 24 Jun 26 06:57:55 PM PDT 24 178869354 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4023576730 Jun 26 06:57:26 PM PDT 24 Jun 26 06:57:38 PM PDT 24 1755984250 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3114337654 Jun 26 06:57:22 PM PDT 24 Jun 26 06:57:27 PM PDT 24 217130526 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2791606376 Jun 26 06:57:40 PM PDT 24 Jun 26 06:57:45 PM PDT 24 1263649695 ps
T1045 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.211628418 Jun 26 06:58:03 PM PDT 24 Jun 26 06:58:06 PM PDT 24 49052733 ps
T1046 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.201872148 Jun 26 06:57:40 PM PDT 24 Jun 26 06:57:57 PM PDT 24 564206949 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1673618674 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:42 PM PDT 24 178759731 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2373658950 Jun 26 06:57:22 PM PDT 24 Jun 26 06:57:48 PM PDT 24 4145169005 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3908763621 Jun 26 06:57:20 PM PDT 24 Jun 26 06:57:23 PM PDT 24 17183262 ps
T1050 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.984529235 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:09 PM PDT 24 57962506 ps
T1051 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3966856274 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:04 PM PDT 24 196116962 ps
T1052 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3683736996 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:39 PM PDT 24 15923814 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1131398795 Jun 26 06:57:20 PM PDT 24 Jun 26 06:57:36 PM PDT 24 205070765 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.311733955 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:07 PM PDT 24 472579229 ps
T1055 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4035352922 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:42 PM PDT 24 718342623 ps
T1056 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4250291173 Jun 26 06:58:17 PM PDT 24 Jun 26 06:58:21 PM PDT 24 37982086 ps
T1057 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1440025786 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:39 PM PDT 24 14015168 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4288247425 Jun 26 06:57:50 PM PDT 24 Jun 26 06:57:54 PM PDT 24 26329076 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2789179487 Jun 26 06:57:25 PM PDT 24 Jun 26 06:57:29 PM PDT 24 47896618 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.58169972 Jun 26 06:57:40 PM PDT 24 Jun 26 06:57:43 PM PDT 24 26950344 ps
T1061 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3165638635 Jun 26 06:58:18 PM PDT 24 Jun 26 06:58:23 PM PDT 24 16358154 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3269366352 Jun 26 06:57:24 PM PDT 24 Jun 26 06:57:27 PM PDT 24 26013196 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.148175567 Jun 26 06:57:28 PM PDT 24 Jun 26 06:57:33 PM PDT 24 543366492 ps
T1064 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3612111703 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:42 PM PDT 24 199452494 ps
T1065 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1768351587 Jun 26 06:58:16 PM PDT 24 Jun 26 06:58:20 PM PDT 24 13564740 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2919256864 Jun 26 06:57:25 PM PDT 24 Jun 26 06:57:31 PM PDT 24 40899252 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.34706525 Jun 26 06:57:52 PM PDT 24 Jun 26 06:58:14 PM PDT 24 299092751 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1960335389 Jun 26 06:58:04 PM PDT 24 Jun 26 06:58:09 PM PDT 24 223793165 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1585443376 Jun 26 06:57:24 PM PDT 24 Jun 26 06:58:04 PM PDT 24 3762958264 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1331028880 Jun 26 06:57:20 PM PDT 24 Jun 26 06:57:24 PM PDT 24 38465459 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2021158516 Jun 26 06:57:37 PM PDT 24 Jun 26 06:57:40 PM PDT 24 90046962 ps
T1072 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2475109185 Jun 26 06:58:03 PM PDT 24 Jun 26 06:58:09 PM PDT 24 167507671 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2749934984 Jun 26 06:57:26 PM PDT 24 Jun 26 06:57:29 PM PDT 24 57719281 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3299033778 Jun 26 06:57:20 PM PDT 24 Jun 26 06:57:26 PM PDT 24 622892929 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3991422493 Jun 26 06:57:26 PM PDT 24 Jun 26 06:57:32 PM PDT 24 299741192 ps
T1076 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1680533365 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:03 PM PDT 24 13622617 ps
T1077 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3264759445 Jun 26 06:57:39 PM PDT 24 Jun 26 06:57:44 PM PDT 24 121528049 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3140170903 Jun 26 06:57:22 PM PDT 24 Jun 26 06:57:28 PM PDT 24 222376436 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.454954609 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:26 PM PDT 24 13707626 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2303773301 Jun 26 06:57:29 PM PDT 24 Jun 26 06:57:43 PM PDT 24 190664963 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1703996012 Jun 26 06:58:02 PM PDT 24 Jun 26 06:58:04 PM PDT 24 21425518 ps
T1082 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2857225117 Jun 26 06:58:03 PM PDT 24 Jun 26 06:58:21 PM PDT 24 2744109356 ps
T1083 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.574494504 Jun 26 06:57:38 PM PDT 24 Jun 26 06:57:43 PM PDT 24 224635055 ps
T1084 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1670982315 Jun 26 06:57:56 PM PDT 24 Jun 26 06:58:00 PM PDT 24 45863591 ps
T1085 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3476041213 Jun 26 06:57:51 PM PDT 24 Jun 26 06:57:57 PM PDT 24 837738357 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1599486392 Jun 26 06:57:22 PM PDT 24 Jun 26 06:57:26 PM PDT 24 75635239 ps
T1087 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2265984450 Jun 26 06:57:26 PM PDT 24 Jun 26 06:57:31 PM PDT 24 72020122 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.270850150 Jun 26 06:57:53 PM PDT 24 Jun 26 06:58:00 PM PDT 24 672154576 ps
T1089 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1005218086 Jun 26 06:57:53 PM PDT 24 Jun 26 06:57:57 PM PDT 24 82482324 ps
T1090 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3732354026 Jun 26 06:58:03 PM PDT 24 Jun 26 06:58:07 PM PDT 24 15259412 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1831246052 Jun 26 06:57:36 PM PDT 24 Jun 26 06:58:02 PM PDT 24 4319111305 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3738603627 Jun 26 06:57:53 PM PDT 24 Jun 26 06:57:57 PM PDT 24 80118017 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1930235643 Jun 26 06:57:40 PM PDT 24 Jun 26 06:57:43 PM PDT 24 58551880 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2339053147 Jun 26 06:57:26 PM PDT 24 Jun 26 06:57:33 PM PDT 24 188201309 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4061954391 Jun 26 06:57:21 PM PDT 24 Jun 26 06:57:24 PM PDT 24 24495389 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4080096174 Jun 26 06:57:23 PM PDT 24 Jun 26 06:57:26 PM PDT 24 16935164 ps
T1097 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1543182341 Jun 26 06:57:47 PM PDT 24 Jun 26 06:57:50 PM PDT 24 34840676 ps
T162 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3371063480 Jun 26 06:57:46 PM PDT 24 Jun 26 06:57:52 PM PDT 24 535512482 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3107481605 Jun 26 06:57:54 PM PDT 24 Jun 26 06:58:01 PM PDT 24 601664022 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.402150395 Jun 26 06:57:25 PM PDT 24 Jun 26 06:58:05 PM PDT 24 2084243459 ps
T1100 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3584457783 Jun 26 06:57:55 PM PDT 24 Jun 26 06:57:58 PM PDT 24 40354959 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3266802018 Jun 26 06:57:24 PM PDT 24 Jun 26 06:57:29 PM PDT 24 78810261 ps

Test location /workspace/coverage/default/9.spi_device_stress_all.116897426
Short name T6
Test name
Test status
Simulation time 171664739493 ps
CPU time 776.15 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:13:48 PM PDT 24
Peak memory 282316 kb
Host smart-434109e3-3197-4753-821b-2fec99a553ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116897426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.116897426
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1739157595
Short name T13
Test name
Test status
Simulation time 88963665165 ps
CPU time 507.71 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:11:24 PM PDT 24
Peak memory 272760 kb
Host smart-fe66e153-9aac-497a-9507-734cee28c48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739157595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1739157595
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2620038449
Short name T101
Test name
Test status
Simulation time 57663078 ps
CPU time 1.71 seconds
Started Jun 26 06:57:38 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 215856 kb
Host smart-6a63140d-fb12-45fd-ad33-cc4f3d40cfa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620038449 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2620038449
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3898475643
Short name T15
Test name
Test status
Simulation time 33273107162 ps
CPU time 180.53 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:05:23 PM PDT 24
Peak memory 269696 kb
Host smart-a559fdd8-d6d8-4991-88ea-07b189f9eae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898475643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3898475643
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3105598602
Short name T56
Test name
Test status
Simulation time 43500378 ps
CPU time 0.79 seconds
Started Jun 26 06:59:59 PM PDT 24
Finished Jun 26 07:00:04 PM PDT 24
Peak memory 216656 kb
Host smart-2bc4de27-1140-4944-99d1-ee3b56ad4611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105598602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3105598602
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.865670833
Short name T187
Test name
Test status
Simulation time 766182494043 ps
CPU time 594.41 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:11:13 PM PDT 24
Peak memory 274308 kb
Host smart-e7217eda-1d72-4bfb-9c52-5c7c5f0123ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865670833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.865670833
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1341583357
Short name T90
Test name
Test status
Simulation time 558429971 ps
CPU time 17.77 seconds
Started Jun 26 06:57:36 PM PDT 24
Finished Jun 26 06:57:55 PM PDT 24
Peak memory 224012 kb
Host smart-664b7c79-f972-4d3b-a5d3-f5f2413ab409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341583357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1341583357
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.897617279
Short name T3
Test name
Test status
Simulation time 238686443483 ps
CPU time 608.29 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:12:52 PM PDT 24
Peak memory 266100 kb
Host smart-403b7ab2-3031-4df7-91fd-f459a13af99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897617279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.897617279
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3702154929
Short name T36
Test name
Test status
Simulation time 5254283107 ps
CPU time 141 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:04:19 PM PDT 24
Peak memory 262860 kb
Host smart-e8561be1-e97c-40a3-b3c5-9c76584fe3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702154929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3702154929
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1489604510
Short name T11
Test name
Test status
Simulation time 462023128 ps
CPU time 7.03 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 233176 kb
Host smart-17052371-806f-42a1-a4f5-d096f8eb1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489604510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1489604510
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3792739042
Short name T123
Test name
Test status
Simulation time 16371432 ps
CPU time 0.77 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:02 PM PDT 24
Peak memory 206224 kb
Host smart-e538942d-5c81-467a-b965-aecdc5fd48c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792739042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3792739042
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.965018293
Short name T192
Test name
Test status
Simulation time 37707187136 ps
CPU time 283 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:06:18 PM PDT 24
Peak memory 274048 kb
Host smart-837ee4a6-ad54-49a8-a7b7-f38bd8bc1173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965018293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.965018293
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1654144972
Short name T14
Test name
Test status
Simulation time 164899246749 ps
CPU time 438.34 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:08:02 PM PDT 24
Peak memory 266812 kb
Host smart-c8455c27-d632-465b-a0f7-eb7c342f1bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654144972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1654144972
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1660552311
Short name T94
Test name
Test status
Simulation time 145405567 ps
CPU time 5.13 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:11 PM PDT 24
Peak memory 215860 kb
Host smart-b772f2ad-e70c-49f7-9ff7-53e6084b8c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660552311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1660552311
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2457449319
Short name T113
Test name
Test status
Simulation time 115313550 ps
CPU time 2.44 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 215836 kb
Host smart-51e3facb-f79f-4c9b-8b6c-de4d78161ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457449319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
457449319
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1690941325
Short name T153
Test name
Test status
Simulation time 571375571648 ps
CPU time 987.82 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:18:29 PM PDT 24
Peak memory 282484 kb
Host smart-7f089360-74f9-4c43-bfc4-29f5b106a9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690941325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1690941325
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.498047207
Short name T63
Test name
Test status
Simulation time 20708022446 ps
CPU time 136.01 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:06:01 PM PDT 24
Peak memory 262404 kb
Host smart-efc30cfa-519f-4005-b120-cfb824667f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498047207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.498047207
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3652991988
Short name T31
Test name
Test status
Simulation time 15819660 ps
CPU time 1.08 seconds
Started Jun 26 07:00:15 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 218588 kb
Host smart-68e403e8-fd79-4baa-a612-e59e1c2f87cd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652991988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3652991988
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2249653112
Short name T271
Test name
Test status
Simulation time 37553566550 ps
CPU time 369.22 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:06:22 PM PDT 24
Peak memory 307064 kb
Host smart-c499cf02-08c3-42fe-ae6c-9122366ab8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249653112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2249653112
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3005214349
Short name T58
Test name
Test status
Simulation time 154270790 ps
CPU time 1.05 seconds
Started Jun 26 07:00:08 PM PDT 24
Finished Jun 26 07:00:10 PM PDT 24
Peak memory 235848 kb
Host smart-a121bb38-7499-4a38-92aa-d1ba4f561722
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005214349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3005214349
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4082797665
Short name T152
Test name
Test status
Simulation time 16490762529 ps
CPU time 182.23 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:05:00 PM PDT 24
Peak memory 272392 kb
Host smart-5c4162f5-36cb-40c3-834b-e6355ac4d679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082797665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4082797665
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3299464016
Short name T179
Test name
Test status
Simulation time 46654959671 ps
CPU time 76.25 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:01:49 PM PDT 24
Peak memory 266712 kb
Host smart-d5922ada-7e67-4d78-9f3c-e505e62602ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299464016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3299464016
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2190251272
Short name T18
Test name
Test status
Simulation time 36713597721 ps
CPU time 170.69 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:05:32 PM PDT 24
Peak memory 257552 kb
Host smart-5a91464e-7ec2-4b9b-9c37-59c8a13c64ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190251272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2190251272
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.801839981
Short name T40
Test name
Test status
Simulation time 5639911993 ps
CPU time 65.76 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:01:49 PM PDT 24
Peak memory 255188 kb
Host smart-ba1cfd24-ebad-4bad-b0b3-d6ae1310bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801839981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.801839981
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4280641078
Short name T146
Test name
Test status
Simulation time 1244953861 ps
CPU time 16.35 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:44 PM PDT 24
Peak memory 216028 kb
Host smart-05a1ce22-cb80-4c06-9bb7-80235150a85a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280641078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4280641078
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3925737014
Short name T281
Test name
Test status
Simulation time 6878224944 ps
CPU time 61.05 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:01:52 PM PDT 24
Peak memory 234992 kb
Host smart-5d9c76f0-d3d2-430c-bb03-bcd4ce59d45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925737014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3925737014
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.673520505
Short name T32
Test name
Test status
Simulation time 450223350266 ps
CPU time 531.47 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:10:07 PM PDT 24
Peak memory 266120 kb
Host smart-ae11c3f2-c039-4397-b2c8-b774cfddccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673520505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.673520505
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2224447722
Short name T127
Test name
Test status
Simulation time 283019846702 ps
CPU time 548.65 seconds
Started Jun 26 07:03:41 PM PDT 24
Finished Jun 26 07:12:51 PM PDT 24
Peak memory 265972 kb
Host smart-00fd73fe-ce12-46c8-991a-3a950937a1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224447722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2224447722
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3485364332
Short name T245
Test name
Test status
Simulation time 2153720192 ps
CPU time 51.57 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:03:14 PM PDT 24
Peak memory 249676 kb
Host smart-cffbe5c4-3d6d-4e7a-81f6-f151e1becac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485364332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3485364332
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2808383874
Short name T260
Test name
Test status
Simulation time 10879581570 ps
CPU time 151.99 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:05:00 PM PDT 24
Peak memory 268024 kb
Host smart-8138a043-a7a4-4725-b254-84b2e87ef235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808383874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2808383874
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3371063480
Short name T162
Test name
Test status
Simulation time 535512482 ps
CPU time 4.14 seconds
Started Jun 26 06:57:46 PM PDT 24
Finished Jun 26 06:57:52 PM PDT 24
Peak memory 215884 kb
Host smart-90e0fb43-1eb6-462b-a255-a86c5284a42e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371063480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
371063480
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1313181811
Short name T163
Test name
Test status
Simulation time 5415962793 ps
CPU time 23.86 seconds
Started Jun 26 06:57:51 PM PDT 24
Finished Jun 26 06:58:17 PM PDT 24
Peak memory 215820 kb
Host smart-52a6b49d-953a-48da-8aed-a919035317cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313181811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1313181811
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.469201465
Short name T33
Test name
Test status
Simulation time 118707973769 ps
CPU time 578.35 seconds
Started Jun 26 07:00:08 PM PDT 24
Finished Jun 26 07:09:47 PM PDT 24
Peak memory 267156 kb
Host smart-4c7a4cb1-391d-432d-86c1-4f1e2c27f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469201465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
469201465
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.556787390
Short name T20
Test name
Test status
Simulation time 3884697788 ps
CPU time 46.28 seconds
Started Jun 26 07:03:15 PM PDT 24
Finished Jun 26 07:04:02 PM PDT 24
Peak memory 254952 kb
Host smart-ffcfa483-dea9-4b78-9b32-ebc28dc79bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556787390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.556787390
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.342035845
Short name T184
Test name
Test status
Simulation time 182594145538 ps
CPU time 484.87 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:08:47 PM PDT 24
Peak memory 260972 kb
Host smart-d1e6e69a-b4c3-4bcc-bc83-40b3dc4dfd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342035845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
342035845
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2101709897
Short name T78
Test name
Test status
Simulation time 279904610 ps
CPU time 7.14 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:43 PM PDT 24
Peak memory 233224 kb
Host smart-a4ceaa0f-cdb3-4a74-861e-4e92ae7277a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101709897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2101709897
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2301874609
Short name T968
Test name
Test status
Simulation time 116221747 ps
CPU time 2.58 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:20 PM PDT 24
Peak memory 224900 kb
Host smart-af40667a-7f92-4430-b5b2-446747160e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301874609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2301874609
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.565935219
Short name T2
Test name
Test status
Simulation time 14392932394 ps
CPU time 19.02 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:31 PM PDT 24
Peak memory 233204 kb
Host smart-61925517-096e-4b67-aa18-35bd5fa941e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565935219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.565935219
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3485663627
Short name T1029
Test name
Test status
Simulation time 268876641 ps
CPU time 3.59 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:55 PM PDT 24
Peak memory 215912 kb
Host smart-a109fdd2-0dfa-445e-8723-a3babf50d46a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485663627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3485663627
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3582836932
Short name T212
Test name
Test status
Simulation time 9977844580 ps
CPU time 146.08 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:04:02 PM PDT 24
Peak memory 249740 kb
Host smart-bed17c1f-44b9-422f-8500-dd5268792156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582836932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3582836932
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1337988367
Short name T196
Test name
Test status
Simulation time 136796379 ps
CPU time 3.75 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:38 PM PDT 24
Peak memory 224932 kb
Host smart-c4e80680-45df-4d35-b024-c0f231610777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337988367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1337988367
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2008638272
Short name T266
Test name
Test status
Simulation time 13704706382 ps
CPU time 100.72 seconds
Started Jun 26 07:03:48 PM PDT 24
Finished Jun 26 07:05:31 PM PDT 24
Peak memory 269044 kb
Host smart-fcf30606-30bc-4cca-8a8a-e15729f7efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008638272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2008638272
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2250544059
Short name T73
Test name
Test status
Simulation time 181785562 ps
CPU time 1.51 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 207468 kb
Host smart-6effc013-38bb-48c1-9f5b-248453762aea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250544059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2250544059
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1239408172
Short name T83
Test name
Test status
Simulation time 3555218677 ps
CPU time 31.98 seconds
Started Jun 26 07:01:01 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 225092 kb
Host smart-58d911e8-09d7-4551-9b37-c7da85274c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239408172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1239408172
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.433968642
Short name T106
Test name
Test status
Simulation time 913723167 ps
CPU time 24.66 seconds
Started Jun 26 06:57:19 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 215772 kb
Host smart-3c5ef7a7-ebce-45c5-b60c-66e1407eb26a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433968642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.433968642
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.402150395
Short name T1099
Test name
Test status
Simulation time 2084243459 ps
CPU time 36.57 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 215732 kb
Host smart-7683c9c4-ad6b-489a-beb4-9dc2e75ea306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402150395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.402150395
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3917849502
Short name T74
Test name
Test status
Simulation time 65526905 ps
CPU time 0.98 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 207272 kb
Host smart-16fb440b-3e3e-4547-bea1-5591ce137a9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917849502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3917849502
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2552369602
Short name T142
Test name
Test status
Simulation time 156972204 ps
CPU time 3.8 seconds
Started Jun 26 06:57:21 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 217544 kb
Host smart-adb8a638-e8a9-4289-92e2-ada057bff97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552369602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2552369602
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3163521912
Short name T1017
Test name
Test status
Simulation time 28042307 ps
CPU time 2.11 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 207560 kb
Host smart-0f6047e9-589c-4785-9ef3-8dceb88af3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163521912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
163521912
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4061954391
Short name T1095
Test name
Test status
Simulation time 24495389 ps
CPU time 0.7 seconds
Started Jun 26 06:57:21 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 204080 kb
Host smart-6dcf9aa1-1e93-472d-b471-f6225998af41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061954391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
061954391
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1331028880
Short name T1070
Test name
Test status
Simulation time 38465459 ps
CPU time 1.44 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 215744 kb
Host smart-5e7bda66-b9f5-4806-a5b2-dd3d5ff55dde
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331028880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1331028880
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1449101648
Short name T984
Test name
Test status
Simulation time 158369334 ps
CPU time 0.66 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:23 PM PDT 24
Peak memory 204320 kb
Host smart-5e765a00-54a3-420e-ba16-edafcad4cd98
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449101648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1449101648
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3140170903
Short name T1078
Test name
Test status
Simulation time 222376436 ps
CPU time 4.06 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:28 PM PDT 24
Peak memory 215616 kb
Host smart-01b89d13-44e0-47e2-bada-6e15f0c08895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140170903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3140170903
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2051382064
Short name T93
Test name
Test status
Simulation time 99424248 ps
CPU time 3.32 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 215864 kb
Host smart-d0490bd3-87f1-4909-94a9-bae56bb52f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051382064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
051382064
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4125366126
Short name T165
Test name
Test status
Simulation time 124154255 ps
CPU time 7.63 seconds
Started Jun 26 06:57:19 PM PDT 24
Finished Jun 26 06:57:28 PM PDT 24
Peak memory 215728 kb
Host smart-0199088d-5a13-4872-906e-8084ba9d2010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125366126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4125366126
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2393074796
Short name T1036
Test name
Test status
Simulation time 755448994 ps
CPU time 6.75 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 207504 kb
Host smart-b06a7cb8-d7a7-447a-9c28-f8e207826467
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393074796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2393074796
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2094464843
Short name T110
Test name
Test status
Simulation time 707810583 ps
CPU time 24.51 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:53 PM PDT 24
Peak memory 215740 kb
Host smart-0f71e512-66d2-4ac8-8182-dc487b802b8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094464843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2094464843
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3908763621
Short name T1049
Test name
Test status
Simulation time 17183262 ps
CPU time 0.96 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:23 PM PDT 24
Peak memory 207272 kb
Host smart-4539a555-9e0c-48ec-80b3-7bf7a83e078e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908763621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3908763621
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3825097633
Short name T1037
Test name
Test status
Simulation time 239021400 ps
CPU time 1.91 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:28 PM PDT 24
Peak memory 215820 kb
Host smart-9b1db82f-e2f5-46d0-b296-8e1faae0da46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825097633 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3825097633
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.454954609
Short name T1079
Test name
Test status
Simulation time 13707626 ps
CPU time 0.72 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 203992 kb
Host smart-283d3df5-f186-41a2-8a61-73d7092d9e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454954609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.454954609
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2136150108
Short name T108
Test name
Test status
Simulation time 184945699 ps
CPU time 2.16 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:30 PM PDT 24
Peak memory 215768 kb
Host smart-696f3d89-eb1f-46c2-8e59-2c1b87e9c658
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136150108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2136150108
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3470316488
Short name T1013
Test name
Test status
Simulation time 27792396 ps
CPU time 0.65 seconds
Started Jun 26 06:57:19 PM PDT 24
Finished Jun 26 06:57:21 PM PDT 24
Peak memory 203980 kb
Host smart-37562254-2408-4212-9d87-e04eed48c315
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470316488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3470316488
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3299033778
Short name T1074
Test name
Test status
Simulation time 622892929 ps
CPU time 4.49 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 215752 kb
Host smart-fa84c062-7b8b-4bcf-ad3f-1bebaa6a5c88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299033778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3299033778
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.58385146
Short name T98
Test name
Test status
Simulation time 692574862 ps
CPU time 2.04 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 215988 kb
Host smart-e849f987-6a74-4984-93df-dbbc08aeee50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58385146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.58385146
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2440850524
Short name T1014
Test name
Test status
Simulation time 338853719 ps
CPU time 17.12 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 215768 kb
Host smart-877c552c-cae7-4c09-adcc-e6a15fa7a127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440850524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2440850524
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.70753176
Short name T87
Test name
Test status
Simulation time 80284836 ps
CPU time 1.8 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 215880 kb
Host smart-02332ad5-6a54-4dd4-81ed-0c486c026033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70753176 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.70753176
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2381332851
Short name T117
Test name
Test status
Simulation time 28937646 ps
CPU time 1.86 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 215708 kb
Host smart-970527e9-e263-42d5-aac9-8b736618c369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381332851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2381332851
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3683736996
Short name T1052
Test name
Test status
Simulation time 15923814 ps
CPU time 0.76 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:39 PM PDT 24
Peak memory 204100 kb
Host smart-680887f2-5e96-44df-9c76-25cb51b90c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683736996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3683736996
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1673618674
Short name T1047
Test name
Test status
Simulation time 178759731 ps
CPU time 3.21 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:42 PM PDT 24
Peak memory 215788 kb
Host smart-92ee1df9-eb81-4752-b4f5-a1b36e66f9a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673618674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1673618674
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.625982552
Short name T85
Test name
Test status
Simulation time 152738044 ps
CPU time 3.69 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 215988 kb
Host smart-a5c42cbf-9be1-4add-afee-cc56a10208db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625982552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.625982552
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.28016727
Short name T96
Test name
Test status
Simulation time 2266860592 ps
CPU time 13.91 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:56 PM PDT 24
Peak memory 216228 kb
Host smart-050a2143-e015-456f-b846-06421f240555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28016727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.28016727
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2813703688
Short name T1038
Test name
Test status
Simulation time 27139530 ps
CPU time 1.83 seconds
Started Jun 26 06:57:46 PM PDT 24
Finished Jun 26 06:57:49 PM PDT 24
Peak memory 215784 kb
Host smart-10c29aca-1903-4e37-a792-8ba011019fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813703688 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2813703688
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3264759445
Short name T1077
Test name
Test status
Simulation time 121528049 ps
CPU time 2.06 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:44 PM PDT 24
Peak memory 215772 kb
Host smart-28607411-c5ac-46c8-afeb-312e68a0f3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264759445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3264759445
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1440025786
Short name T1057
Test name
Test status
Simulation time 14015168 ps
CPU time 0.75 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:39 PM PDT 24
Peak memory 203968 kb
Host smart-dac97083-92e0-4acc-b745-b3c32de21737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440025786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1440025786
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.267613585
Short name T1021
Test name
Test status
Simulation time 359347209 ps
CPU time 4.12 seconds
Started Jun 26 06:57:36 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 215772 kb
Host smart-a223050c-6029-4c90-9ed3-f0f40aa5f3f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267613585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.267613585
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1628180867
Short name T97
Test name
Test status
Simulation time 375426471 ps
CPU time 2.99 seconds
Started Jun 26 06:57:42 PM PDT 24
Finished Jun 26 06:57:47 PM PDT 24
Peak memory 215820 kb
Host smart-25b1c7f2-6dfb-4758-b2ac-d2f0a1503374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628180867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1628180867
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3307512176
Short name T89
Test name
Test status
Simulation time 7554100839 ps
CPU time 22.88 seconds
Started Jun 26 06:57:41 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 216232 kb
Host smart-830e2803-1c6c-4297-aff2-0bb3f7880ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307512176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3307512176
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3648083803
Short name T102
Test name
Test status
Simulation time 88635848 ps
CPU time 1.63 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:54 PM PDT 24
Peak memory 215940 kb
Host smart-9b8271e9-2337-4ad7-ac92-6c326a2af423
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648083803 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3648083803
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1342572848
Short name T115
Test name
Test status
Simulation time 137249897 ps
CPU time 2.04 seconds
Started Jun 26 06:57:49 PM PDT 24
Finished Jun 26 06:57:54 PM PDT 24
Peak memory 215768 kb
Host smart-817ae85f-6898-4077-ada3-1c6d77336ae3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342572848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1342572848
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3745256017
Short name T992
Test name
Test status
Simulation time 40124522 ps
CPU time 0.68 seconds
Started Jun 26 06:57:51 PM PDT 24
Finished Jun 26 06:57:54 PM PDT 24
Peak memory 204392 kb
Host smart-5ac2dfa1-7adb-46d2-b8eb-400175866d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745256017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3745256017
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2536877003
Short name T132
Test name
Test status
Simulation time 47462049 ps
CPU time 2.71 seconds
Started Jun 26 06:57:52 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215816 kb
Host smart-28f9b4a7-42a1-48d7-8e80-c0e721c8de28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536877003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2536877003
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1543182341
Short name T1097
Test name
Test status
Simulation time 34840676 ps
CPU time 1.43 seconds
Started Jun 26 06:57:47 PM PDT 24
Finished Jun 26 06:57:50 PM PDT 24
Peak memory 216904 kb
Host smart-18e937ab-5876-468b-88e6-2f619b2945f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543182341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1543182341
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.201872148
Short name T1046
Test name
Test status
Simulation time 564206949 ps
CPU time 15.24 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215860 kb
Host smart-8fa831e0-416b-41f0-9ea0-980e1a3f7d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201872148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.201872148
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.270850150
Short name T1088
Test name
Test status
Simulation time 672154576 ps
CPU time 4.26 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:58:00 PM PDT 24
Peak memory 217584 kb
Host smart-fc085aba-778e-48ce-abb0-630187405af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270850150 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.270850150
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3539165576
Short name T147
Test name
Test status
Simulation time 47004968 ps
CPU time 1.38 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:53 PM PDT 24
Peak memory 207492 kb
Host smart-5e1c51e9-f017-4fbb-ae74-845110630f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539165576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3539165576
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1458882780
Short name T989
Test name
Test status
Simulation time 48552695 ps
CPU time 0.71 seconds
Started Jun 26 06:57:49 PM PDT 24
Finished Jun 26 06:57:52 PM PDT 24
Peak memory 203988 kb
Host smart-223cc280-6223-4081-b64d-333cdc069d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458882780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1458882780
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3662687502
Short name T1000
Test name
Test status
Simulation time 381780032 ps
CPU time 2.82 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:55 PM PDT 24
Peak memory 215728 kb
Host smart-5fee362b-bdbc-4d75-b3cc-7c9b0ec7abf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662687502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3662687502
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.89428731
Short name T161
Test name
Test status
Simulation time 261730945 ps
CPU time 2.12 seconds
Started Jun 26 06:57:52 PM PDT 24
Finished Jun 26 06:57:56 PM PDT 24
Peak memory 215872 kb
Host smart-a6106801-9d32-4376-af9c-f072380bde84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89428731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.89428731
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.34706525
Short name T1067
Test name
Test status
Simulation time 299092751 ps
CPU time 19.46 seconds
Started Jun 26 06:57:52 PM PDT 24
Finished Jun 26 06:58:14 PM PDT 24
Peak memory 215732 kb
Host smart-66d557a8-805a-48da-bf19-d11bfc8c4d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.34706525
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1300156107
Short name T88
Test name
Test status
Simulation time 215285457 ps
CPU time 2.13 seconds
Started Jun 26 06:57:51 PM PDT 24
Finished Jun 26 06:57:56 PM PDT 24
Peak memory 215772 kb
Host smart-7c047008-a8c4-4256-8b37-e4dab4b6ca80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300156107 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1300156107
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4288247425
Short name T1058
Test name
Test status
Simulation time 26329076 ps
CPU time 1.64 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:54 PM PDT 24
Peak memory 215624 kb
Host smart-dbffb813-9967-4105-bbe9-fa24da5cb70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288247425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4288247425
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1540781432
Short name T1008
Test name
Test status
Simulation time 13601288 ps
CPU time 0.74 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:56 PM PDT 24
Peak memory 204068 kb
Host smart-b9d3ef0a-4b82-4c8c-8903-0a765c06e87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540781432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1540781432
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3738603627
Short name T1092
Test name
Test status
Simulation time 80118017 ps
CPU time 1.97 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215820 kb
Host smart-0d723062-a309-4ba1-b849-5296c615d466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738603627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3738603627
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2494231731
Short name T84
Test name
Test status
Simulation time 199963343 ps
CPU time 13.55 seconds
Started Jun 26 06:57:49 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 215756 kb
Host smart-af6211a9-6f55-4de0-b970-e67b8d7ba12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494231731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2494231731
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.61394625
Short name T1025
Test name
Test status
Simulation time 194962000 ps
CPU time 1.97 seconds
Started Jun 26 06:57:54 PM PDT 24
Finished Jun 26 06:57:58 PM PDT 24
Peak memory 216748 kb
Host smart-149b396e-a7a1-4f4c-b377-af61dee99e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61394625 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.61394625
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4015845682
Short name T107
Test name
Test status
Simulation time 124072244 ps
CPU time 2.36 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215732 kb
Host smart-5cbacbc3-526c-4286-b20f-e452ffa97a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015845682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4015845682
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3584457783
Short name T1100
Test name
Test status
Simulation time 40354959 ps
CPU time 0.78 seconds
Started Jun 26 06:57:55 PM PDT 24
Finished Jun 26 06:57:58 PM PDT 24
Peak memory 204296 kb
Host smart-da312f36-01ae-4cdf-a624-0e76777567ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584457783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3584457783
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3107481605
Short name T1098
Test name
Test status
Simulation time 601664022 ps
CPU time 4.53 seconds
Started Jun 26 06:57:54 PM PDT 24
Finished Jun 26 06:58:01 PM PDT 24
Peak memory 215692 kb
Host smart-022969f7-57fd-413d-8d72-fa3a12a671c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107481605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3107481605
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1005218086
Short name T1089
Test name
Test status
Simulation time 82482324 ps
CPU time 2.23 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215816 kb
Host smart-3e6e4890-1bea-4408-91e1-0ea905f14f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005218086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1005218086
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.459710507
Short name T164
Test name
Test status
Simulation time 602708619 ps
CPU time 20.35 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:58:15 PM PDT 24
Peak memory 215764 kb
Host smart-51ecc7a3-b098-4619-848c-8f9d5f34817d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459710507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.459710507
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.525378052
Short name T1007
Test name
Test status
Simulation time 23400565 ps
CPU time 1.6 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215940 kb
Host smart-2ec58786-780c-4ece-8051-f6f674d9b647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525378052 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.525378052
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3714629827
Short name T114
Test name
Test status
Simulation time 148932747 ps
CPU time 2.88 seconds
Started Jun 26 06:57:52 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215756 kb
Host smart-81f872bb-61b1-4911-85f7-09341ac38bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714629827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3714629827
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.210709335
Short name T1041
Test name
Test status
Simulation time 178869354 ps
CPU time 0.78 seconds
Started Jun 26 06:57:52 PM PDT 24
Finished Jun 26 06:57:55 PM PDT 24
Peak memory 204072 kb
Host smart-c863031e-5a8d-4428-95ac-11566ad17203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210709335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.210709335
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3476041213
Short name T1085
Test name
Test status
Simulation time 837738357 ps
CPU time 4.49 seconds
Started Jun 26 06:57:51 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215752 kb
Host smart-312af084-2135-4065-ba6b-b99c1ab4780d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476041213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3476041213
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2860133453
Short name T1035
Test name
Test status
Simulation time 140121521 ps
CPU time 3.29 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:57:55 PM PDT 24
Peak memory 215876 kb
Host smart-afc73c1f-36b0-41fb-a1cb-5680a1f947d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860133453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2860133453
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2161094158
Short name T1034
Test name
Test status
Simulation time 7138178479 ps
CPU time 16.99 seconds
Started Jun 26 06:57:50 PM PDT 24
Finished Jun 26 06:58:10 PM PDT 24
Peak memory 215944 kb
Host smart-2d889d53-3aed-459e-82e1-d68ca282f284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161094158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2161094158
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3507153054
Short name T100
Test name
Test status
Simulation time 47262687 ps
CPU time 1.74 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 216872 kb
Host smart-5133e2d7-61ff-42d7-81ba-98ec5a4bc1b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507153054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3507153054
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1960335389
Short name T1068
Test name
Test status
Simulation time 223793165 ps
CPU time 2.01 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 215772 kb
Host smart-23a77bff-8b18-4357-bf72-ee9adb7dd8de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960335389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1960335389
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2731898796
Short name T1011
Test name
Test status
Simulation time 14500981 ps
CPU time 0.72 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204032 kb
Host smart-37046775-8529-4b6f-a053-e4dc5dd703bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731898796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2731898796
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3554945988
Short name T133
Test name
Test status
Simulation time 351460214 ps
CPU time 2 seconds
Started Jun 26 06:58:01 PM PDT 24
Finished Jun 26 06:58:04 PM PDT 24
Peak memory 215776 kb
Host smart-d6d29839-455a-4d90-a16c-8c6a346d1f16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554945988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3554945988
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4152734232
Short name T95
Test name
Test status
Simulation time 108857331 ps
CPU time 2.04 seconds
Started Jun 26 06:57:53 PM PDT 24
Finished Jun 26 06:57:57 PM PDT 24
Peak memory 215928 kb
Host smart-dcd95769-a552-4a43-9408-011de7d641e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152734232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4152734232
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.311733955
Short name T1054
Test name
Test status
Simulation time 472579229 ps
CPU time 1.93 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:07 PM PDT 24
Peak memory 216800 kb
Host smart-8b3a8f43-8e3e-4c78-a27e-4efa3f274421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311733955 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.311733955
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.984529235
Short name T1050
Test name
Test status
Simulation time 57962506 ps
CPU time 1.99 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 215724 kb
Host smart-f55e9679-0b3c-440f-9c78-bff1b647aebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984529235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.984529235
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1703996012
Short name T1081
Test name
Test status
Simulation time 21425518 ps
CPU time 0.79 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:04 PM PDT 24
Peak memory 204060 kb
Host smart-e63df62c-561c-4848-8ab5-e4af25ba5c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703996012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1703996012
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1911210963
Short name T999
Test name
Test status
Simulation time 255922651 ps
CPU time 2.68 seconds
Started Jun 26 06:58:05 PM PDT 24
Finished Jun 26 06:58:10 PM PDT 24
Peak memory 215732 kb
Host smart-db9570c0-6d30-49dd-8895-b59762b3e50b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911210963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1911210963
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3433697230
Short name T166
Test name
Test status
Simulation time 1040528266 ps
CPU time 23.38 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:30 PM PDT 24
Peak memory 216184 kb
Host smart-b884b6b9-2b22-44dc-b46f-155252118f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433697230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3433697230
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.468649370
Short name T1028
Test name
Test status
Simulation time 91729592 ps
CPU time 1.72 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 216800 kb
Host smart-fdb1c1c4-1ff0-4030-a5dd-62e6d8c4da45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468649370 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.468649370
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1009454631
Short name T144
Test name
Test status
Simulation time 102603663 ps
CPU time 2.37 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 215780 kb
Host smart-782fc8d9-c295-4838-9e85-30ed6e4dfa2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009454631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1009454631
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4263713572
Short name T990
Test name
Test status
Simulation time 21707865 ps
CPU time 0.73 seconds
Started Jun 26 06:58:05 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 204004 kb
Host smart-1c0d4837-0995-47e6-9237-4726e786b246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263713572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4263713572
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2475109185
Short name T1072
Test name
Test status
Simulation time 167507671 ps
CPU time 3.08 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 215776 kb
Host smart-6dbcbe9b-daeb-4df7-ab53-db86fbe71ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475109185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2475109185
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.580597749
Short name T149
Test name
Test status
Simulation time 2655456984 ps
CPU time 5.51 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:12 PM PDT 24
Peak memory 215916 kb
Host smart-bcd6c5b7-e798-426f-a7a2-5285e19f91be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580597749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.580597749
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2857225117
Short name T1082
Test name
Test status
Simulation time 2744109356 ps
CPU time 15.65 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 216068 kb
Host smart-dce28e45-837f-406b-b20c-eb5e59e23c42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857225117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2857225117
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4023576730
Short name T1042
Test name
Test status
Simulation time 1755984250 ps
CPU time 9.33 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:38 PM PDT 24
Peak memory 207536 kb
Host smart-8ea81db7-628b-4b09-a965-1e61757a94ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023576730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4023576730
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2303773301
Short name T1080
Test name
Test status
Simulation time 190664963 ps
CPU time 11.9 seconds
Started Jun 26 06:57:29 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 207600 kb
Host smart-57e25744-1844-47f7-ab9d-b052ad06a2af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303773301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2303773301
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2919256864
Short name T1066
Test name
Test status
Simulation time 40899252 ps
CPU time 2.99 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 217344 kb
Host smart-1a2805e6-f127-4def-9a5f-85fdedab9c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919256864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2919256864
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3114337654
Short name T1043
Test name
Test status
Simulation time 217130526 ps
CPU time 2.7 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 215860 kb
Host smart-1d6c8c58-ab81-442c-afc4-58f1ea060b0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114337654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
114337654
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2762511312
Short name T1001
Test name
Test status
Simulation time 13678739 ps
CPU time 0.76 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 204128 kb
Host smart-29b4e925-644d-45b1-b9fb-409cfac944a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762511312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
762511312
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1689008711
Short name T112
Test name
Test status
Simulation time 203941665 ps
CPU time 1.85 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 215832 kb
Host smart-7a4f4ae9-6ad3-48ba-a13c-27aa0b4561e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689008711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1689008711
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4080096174
Short name T1096
Test name
Test status
Simulation time 16935164 ps
CPU time 0.67 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 203984 kb
Host smart-44a528a4-9116-472e-bfd4-85fe1e296913
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080096174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4080096174
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.148175567
Short name T1063
Test name
Test status
Simulation time 543366492 ps
CPU time 3.02 seconds
Started Jun 26 06:57:28 PM PDT 24
Finished Jun 26 06:57:33 PM PDT 24
Peak memory 216132 kb
Host smart-e2d5758f-ce20-48de-a488-c06fb498aaed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148175567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.148175567
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3266802018
Short name T1101
Test name
Test status
Simulation time 78810261 ps
CPU time 2.62 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 216884 kb
Host smart-41274982-97ae-46a3-9521-e58d3f0669a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266802018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
266802018
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1131398795
Short name T1053
Test name
Test status
Simulation time 205070765 ps
CPU time 13.56 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:36 PM PDT 24
Peak memory 215736 kb
Host smart-93352a22-ad42-44ca-84fa-48e933de899a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131398795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1131398795
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1164692782
Short name T986
Test name
Test status
Simulation time 44395852 ps
CPU time 0.77 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204344 kb
Host smart-5ed7bad8-c358-4a06-85e6-d64d90939bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164692782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1164692782
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.13551178
Short name T983
Test name
Test status
Simulation time 15108813 ps
CPU time 0.76 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204348 kb
Host smart-42b4ccb3-2fed-4a36-9756-7c393b8ed442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.13551178
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.419800160
Short name T1004
Test name
Test status
Simulation time 77055170 ps
CPU time 0.73 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204340 kb
Host smart-bb64474f-7652-4b88-b254-198af8b587b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419800160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.419800160
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.723853420
Short name T1016
Test name
Test status
Simulation time 15231419 ps
CPU time 0.75 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204076 kb
Host smart-a6b2e317-5e77-466b-8dd8-8971a51b3a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723853420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.723853420
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1725231215
Short name T980
Test name
Test status
Simulation time 23417030 ps
CPU time 0.72 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204004 kb
Host smart-023cc916-aaa2-4d8d-99ea-b1c528efb4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725231215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1725231215
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2047987374
Short name T1012
Test name
Test status
Simulation time 19346613 ps
CPU time 0.76 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204116 kb
Host smart-2d1c8584-326b-41ba-b4c3-a7c497fe2381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047987374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2047987374
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2007061898
Short name T1015
Test name
Test status
Simulation time 83745261 ps
CPU time 0.77 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 203964 kb
Host smart-3ad54d14-a091-443c-99b6-3df492459275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007061898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2007061898
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2546693704
Short name T987
Test name
Test status
Simulation time 29933132 ps
CPU time 0.7 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:04 PM PDT 24
Peak memory 204020 kb
Host smart-e0f66472-946f-4319-9731-65b84ae92acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546693704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2546693704
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1461298354
Short name T1010
Test name
Test status
Simulation time 14752325 ps
CPU time 0.76 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 204336 kb
Host smart-e1037cf3-b60d-44e0-a286-6085623e9c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461298354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1461298354
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.154514069
Short name T993
Test name
Test status
Simulation time 28785229 ps
CPU time 0.75 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204100 kb
Host smart-3e232709-39f1-48e6-9929-8da91679c463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154514069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.154514069
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.588477851
Short name T141
Test name
Test status
Simulation time 894340649 ps
CPU time 9.3 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:36 PM PDT 24
Peak memory 207512 kb
Host smart-47794e64-9609-4a13-b62d-3e9b91f2133e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588477851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.588477851
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.146465061
Short name T111
Test name
Test status
Simulation time 1870151918 ps
CPU time 34.71 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:58:00 PM PDT 24
Peak memory 207756 kb
Host smart-4a432619-a460-404a-92ef-b75f158bf2d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146465061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.146465061
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1599486392
Short name T1086
Test name
Test status
Simulation time 75635239 ps
CPU time 1.35 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 207548 kb
Host smart-4440ba66-9dc2-4815-ae3e-03a8b8558615
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599486392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1599486392
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3991422493
Short name T1075
Test name
Test status
Simulation time 299741192 ps
CPU time 3.66 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:32 PM PDT 24
Peak memory 217176 kb
Host smart-5d9cb35e-4375-46bb-b64f-ca1723149c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991422493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3991422493
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1189762881
Short name T1018
Test name
Test status
Simulation time 50570328 ps
CPU time 1.67 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 215944 kb
Host smart-87a1f597-bfed-42e3-8ebc-717106437793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189762881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
189762881
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2341468235
Short name T1020
Test name
Test status
Simulation time 15051057 ps
CPU time 0.73 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:28 PM PDT 24
Peak memory 204120 kb
Host smart-dc91be4a-cf4a-4ee2-bf99-9a171ef43bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341468235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
341468235
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.415977956
Short name T118
Test name
Test status
Simulation time 33555899 ps
CPU time 1.23 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 215716 kb
Host smart-45823da1-4190-4c64-a6c4-1567d142ab84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415977956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.415977956
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1762754956
Short name T1032
Test name
Test status
Simulation time 32618821 ps
CPU time 0.66 seconds
Started Jun 26 06:57:28 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 203972 kb
Host smart-101b1d90-e89a-4eb7-8d7e-cdf4d3405c1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762754956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1762754956
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2339053147
Short name T1094
Test name
Test status
Simulation time 188201309 ps
CPU time 4.08 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:33 PM PDT 24
Peak memory 215804 kb
Host smart-96d5f582-bfe5-4f08-85e8-aadb5b0fc30d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339053147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2339053147
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2789179487
Short name T1059
Test name
Test status
Simulation time 47896618 ps
CPU time 1.65 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 215860 kb
Host smart-d4b6bf4b-1ed2-48b7-9668-f3e2f88cc687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789179487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
789179487
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1997184909
Short name T1030
Test name
Test status
Simulation time 395435892 ps
CPU time 6.84 seconds
Started Jun 26 06:57:23 PM PDT 24
Finished Jun 26 06:57:33 PM PDT 24
Peak memory 216248 kb
Host smart-67434df2-70a2-4afe-8eca-11371151293a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997184909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1997184909
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3732354026
Short name T1090
Test name
Test status
Simulation time 15259412 ps
CPU time 0.75 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:07 PM PDT 24
Peak memory 204100 kb
Host smart-26a7b285-56d7-4ded-aea1-633c44c8ed73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732354026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3732354026
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1680533365
Short name T1076
Test name
Test status
Simulation time 13622617 ps
CPU time 0.75 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:03 PM PDT 24
Peak memory 203980 kb
Host smart-7fcef4c4-e5c6-4451-9da8-4c8b58dea0d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680533365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1680533365
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2964622238
Short name T1026
Test name
Test status
Simulation time 15357447 ps
CPU time 0.77 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 204072 kb
Host smart-dcf62d04-9b66-4599-8b97-78b79b7c5424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964622238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2964622238
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2090983592
Short name T1019
Test name
Test status
Simulation time 28527620 ps
CPU time 0.77 seconds
Started Jun 26 06:58:04 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204060 kb
Host smart-1fb96fdb-1e24-418e-b13a-321683d786f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090983592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2090983592
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1445008192
Short name T1005
Test name
Test status
Simulation time 42976726 ps
CPU time 0.79 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204076 kb
Host smart-f86e5962-13ce-490f-bae9-12a1800d8d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445008192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1445008192
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.565122603
Short name T982
Test name
Test status
Simulation time 16120627 ps
CPU time 0.74 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 204072 kb
Host smart-5c3e6b3b-edd3-454b-a544-6363dc52eb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565122603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.565122603
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.211628418
Short name T1045
Test name
Test status
Simulation time 49052733 ps
CPU time 0.79 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204340 kb
Host smart-ec0ef36b-e124-4047-91d5-2e7b413b9315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211628418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.211628418
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1071575265
Short name T998
Test name
Test status
Simulation time 18611543 ps
CPU time 0.74 seconds
Started Jun 26 06:58:05 PM PDT 24
Finished Jun 26 06:58:08 PM PDT 24
Peak memory 204048 kb
Host smart-f8951394-dfb7-470a-9c2b-c2dac8fa0b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071575265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1071575265
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4107682991
Short name T1009
Test name
Test status
Simulation time 122429061 ps
CPU time 0.82 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204100 kb
Host smart-90441dc6-aa1f-4af9-bac9-d90ff9310e13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107682991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4107682991
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3966856274
Short name T1051
Test name
Test status
Simulation time 196116962 ps
CPU time 0.86 seconds
Started Jun 26 06:58:02 PM PDT 24
Finished Jun 26 06:58:04 PM PDT 24
Peak memory 204364 kb
Host smart-de59d045-287b-439e-9590-41b5fc285007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966856274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3966856274
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2373658950
Short name T1048
Test name
Test status
Simulation time 4145169005 ps
CPU time 23.54 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:57:48 PM PDT 24
Peak memory 215816 kb
Host smart-5003d7e9-f5a0-4110-b882-4eaf6c708c06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373658950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2373658950
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1585443376
Short name T1069
Test name
Test status
Simulation time 3762958264 ps
CPU time 37.64 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:58:04 PM PDT 24
Peak memory 207628 kb
Host smart-020f82da-b8fe-4154-ac4e-ddd6c5a034bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585443376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1585443376
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2067112436
Short name T72
Test name
Test status
Simulation time 46599323 ps
CPU time 0.96 seconds
Started Jun 26 06:57:32 PM PDT 24
Finished Jun 26 06:57:34 PM PDT 24
Peak memory 207116 kb
Host smart-728993cc-9900-4ab9-9af0-0cf4f1401d12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067112436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2067112436
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.601104632
Short name T1022
Test name
Test status
Simulation time 232884551 ps
CPU time 3.78 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 218616 kb
Host smart-d05ae2f3-efef-4db2-a19b-1a869ee06d32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601104632 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.601104632
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1305880187
Short name T1024
Test name
Test status
Simulation time 20546296 ps
CPU time 1.29 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 215760 kb
Host smart-28d53ac8-d2c1-4d9d-ae3a-127b61f58262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305880187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
305880187
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3269366352
Short name T1062
Test name
Test status
Simulation time 26013196 ps
CPU time 0.74 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 204360 kb
Host smart-78d85cc0-9793-48cd-abd9-d2a265dcfc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269366352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
269366352
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.906221445
Short name T109
Test name
Test status
Simulation time 59542219 ps
CPU time 1.37 seconds
Started Jun 26 06:57:21 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 215772 kb
Host smart-92b83e61-0876-4c98-9f20-5ea7182d96dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906221445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.906221445
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2718159626
Short name T997
Test name
Test status
Simulation time 13052173 ps
CPU time 0.68 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:30 PM PDT 24
Peak memory 203932 kb
Host smart-fd94325f-c61c-46b6-8269-8c6f53cddc8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718159626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2718159626
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3061812195
Short name T129
Test name
Test status
Simulation time 111968767 ps
CPU time 1.71 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:30 PM PDT 24
Peak memory 207480 kb
Host smart-d9881e43-b5d4-4666-808a-f36e520747d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061812195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3061812195
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2265984450
Short name T1087
Test name
Test status
Simulation time 72020122 ps
CPU time 2.12 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 216852 kb
Host smart-835a029c-8be0-49be-8928-c531d29e8b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265984450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
265984450
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.269431599
Short name T1033
Test name
Test status
Simulation time 1143708310 ps
CPU time 17.56 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:44 PM PDT 24
Peak memory 215808 kb
Host smart-f3e80620-6565-4106-a01d-70a0c42bdfa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269431599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.269431599
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1959876887
Short name T994
Test name
Test status
Simulation time 138981339 ps
CPU time 0.79 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:06 PM PDT 24
Peak memory 204100 kb
Host smart-6936edf7-4999-41e7-94cb-ace069fb66c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959876887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1959876887
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3180963197
Short name T985
Test name
Test status
Simulation time 25467015 ps
CPU time 0.77 seconds
Started Jun 26 06:58:03 PM PDT 24
Finished Jun 26 06:58:07 PM PDT 24
Peak memory 204084 kb
Host smart-2d4d6b2b-48e8-485e-a457-13925c289e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180963197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3180963197
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1985214713
Short name T1003
Test name
Test status
Simulation time 64206614 ps
CPU time 0.77 seconds
Started Jun 26 06:58:06 PM PDT 24
Finished Jun 26 06:58:09 PM PDT 24
Peak memory 204344 kb
Host smart-f577b16b-ce02-47a4-b101-629c1e73fd17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985214713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1985214713
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3696600540
Short name T1023
Test name
Test status
Simulation time 14771670 ps
CPU time 0.76 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204320 kb
Host smart-9f054944-a2ac-4095-9a29-f81a87344319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696600540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3696600540
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.855030087
Short name T995
Test name
Test status
Simulation time 19509288 ps
CPU time 0.81 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204256 kb
Host smart-084aac37-c79a-41ae-9c41-6ad76fb3587c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855030087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.855030087
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1858000840
Short name T981
Test name
Test status
Simulation time 12807614 ps
CPU time 0.73 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204000 kb
Host smart-72ac07b3-1777-4876-b514-14d2b18771d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858000840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1858000840
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4250291173
Short name T1056
Test name
Test status
Simulation time 37982086 ps
CPU time 0.74 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 204112 kb
Host smart-67e6e867-bcb5-48bc-b7b5-f8e2a78d2719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250291173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4250291173
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1768351587
Short name T1065
Test name
Test status
Simulation time 13564740 ps
CPU time 0.74 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204080 kb
Host smart-e4f79f54-928d-478e-8ec6-e454a710bf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768351587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1768351587
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2534517848
Short name T988
Test name
Test status
Simulation time 25008753 ps
CPU time 0.74 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 204044 kb
Host smart-5c232e7d-a1e8-431f-b9e0-bfd6c5959d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534517848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2534517848
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3165638635
Short name T1061
Test name
Test status
Simulation time 16358154 ps
CPU time 0.72 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204088 kb
Host smart-62a4ed27-75bc-44bb-b2e9-1ed1e3c6d499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165638635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3165638635
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.66293766
Short name T148
Test name
Test status
Simulation time 310465368 ps
CPU time 3.78 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 217204 kb
Host smart-7404e746-0127-476c-b93c-befd5464bee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66293766 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.66293766
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.204609002
Short name T116
Test name
Test status
Simulation time 140536334 ps
CPU time 1.21 seconds
Started Jun 26 06:57:21 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 207448 kb
Host smart-c599c510-a2ab-4689-9b1c-337d53262672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204609002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.204609002
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2749934984
Short name T1073
Test name
Test status
Simulation time 57719281 ps
CPU time 0.68 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 204308 kb
Host smart-532b686e-1930-454c-865a-5acb2c6ab142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749934984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
749934984
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4035352922
Short name T1055
Test name
Test status
Simulation time 718342623 ps
CPU time 4.12 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:42 PM PDT 24
Peak memory 215732 kb
Host smart-52f74e60-ac6c-4183-96bb-8ba51b4fdfe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035352922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4035352922
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1886049331
Short name T86
Test name
Test status
Simulation time 768971855 ps
CPU time 5.89 seconds
Started Jun 26 06:57:25 PM PDT 24
Finished Jun 26 06:57:34 PM PDT 24
Peak memory 215884 kb
Host smart-297d4fb9-329b-4661-9be5-2d1b150785f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886049331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
886049331
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.574494504
Short name T1083
Test name
Test status
Simulation time 224635055 ps
CPU time 2.98 seconds
Started Jun 26 06:57:38 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 216884 kb
Host smart-553c8a41-acde-4f41-b4f9-3b33d1d3d027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574494504 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.574494504
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3428898949
Short name T1006
Test name
Test status
Simulation time 59718610 ps
CPU time 1.89 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 215764 kb
Host smart-d16259e7-b62b-4412-a17d-a797598448cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428898949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
428898949
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.938185852
Short name T991
Test name
Test status
Simulation time 44741266 ps
CPU time 0.76 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:42 PM PDT 24
Peak memory 204080 kb
Host smart-0ea0979d-f799-4ca6-8763-84adf5a666e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938185852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.938185852
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2791606376
Short name T1044
Test name
Test status
Simulation time 1263649695 ps
CPU time 3.08 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 215740 kb
Host smart-926444f0-b694-4d64-a972-a2a715fc5388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791606376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2791606376
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2243277030
Short name T1039
Test name
Test status
Simulation time 155504264 ps
CPU time 3.75 seconds
Started Jun 26 06:57:45 PM PDT 24
Finished Jun 26 06:57:50 PM PDT 24
Peak memory 215980 kb
Host smart-b9aeb2c9-7cbf-4c31-952c-c24a65d2f075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243277030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
243277030
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2965118054
Short name T1031
Test name
Test status
Simulation time 866676202 ps
CPU time 20.34 seconds
Started Jun 26 06:57:43 PM PDT 24
Finished Jun 26 06:58:05 PM PDT 24
Peak memory 215728 kb
Host smart-476fbc47-de40-42dc-af3b-63fc0f603564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965118054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2965118054
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.120748058
Short name T145
Test name
Test status
Simulation time 99490055 ps
CPU time 1.82 seconds
Started Jun 26 06:57:46 PM PDT 24
Finished Jun 26 06:57:49 PM PDT 24
Peak memory 215780 kb
Host smart-49efd473-6d6b-4c14-98a5-653c688c069b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120748058 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.120748058
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1581660414
Short name T130
Test name
Test status
Simulation time 919038976 ps
CPU time 1.91 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 215796 kb
Host smart-69ec6da0-b712-44bc-b999-6315285ce596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581660414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
581660414
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2171725378
Short name T996
Test name
Test status
Simulation time 30428487 ps
CPU time 0.76 seconds
Started Jun 26 06:57:38 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 204036 kb
Host smart-d01257ab-ba3f-40eb-9275-cfb2dc595b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171725378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
171725378
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1899295391
Short name T1002
Test name
Test status
Simulation time 527176187 ps
CPU time 2.92 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 215784 kb
Host smart-30ee7b76-fcc2-4552-8dfe-0b3f7d29ced3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899295391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1899295391
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2363783515
Short name T99
Test name
Test status
Simulation time 150307878 ps
CPU time 4.49 seconds
Started Jun 26 06:57:39 PM PDT 24
Finished Jun 26 06:57:46 PM PDT 24
Peak memory 215928 kb
Host smart-0928e720-945b-457c-ae07-88c4d0f991b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363783515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
363783515
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1502425928
Short name T143
Test name
Test status
Simulation time 2096401749 ps
CPU time 21.77 seconds
Started Jun 26 06:57:38 PM PDT 24
Finished Jun 26 06:58:02 PM PDT 24
Peak memory 215832 kb
Host smart-09dc0c5d-f3fb-4b7b-a160-656423c0fae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502425928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1502425928
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.210513714
Short name T131
Test name
Test status
Simulation time 42750348 ps
CPU time 1.41 seconds
Started Jun 26 06:57:47 PM PDT 24
Finished Jun 26 06:57:50 PM PDT 24
Peak memory 215752 kb
Host smart-2b3c88c0-2b05-45c8-81eb-a661a629b6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210513714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.210513714
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1930235643
Short name T1093
Test name
Test status
Simulation time 58551880 ps
CPU time 0.72 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 204068 kb
Host smart-28b20bd6-fee1-4132-978c-84df4efa81a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930235643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
930235643
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1670982315
Short name T1084
Test name
Test status
Simulation time 45863591 ps
CPU time 2.8 seconds
Started Jun 26 06:57:56 PM PDT 24
Finished Jun 26 06:58:00 PM PDT 24
Peak memory 215824 kb
Host smart-71da9050-1e2c-466e-b127-0e85eab55225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670982315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1670982315
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1831246052
Short name T1091
Test name
Test status
Simulation time 4319111305 ps
CPU time 24.2 seconds
Started Jun 26 06:57:36 PM PDT 24
Finished Jun 26 06:58:02 PM PDT 24
Peak memory 216024 kb
Host smart-a3ba4285-aa3e-4d73-b20c-63413d3fa30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831246052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1831246052
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3602308056
Short name T1027
Test name
Test status
Simulation time 508275681 ps
CPU time 4 seconds
Started Jun 26 06:57:38 PM PDT 24
Finished Jun 26 06:57:45 PM PDT 24
Peak memory 217740 kb
Host smart-37ae5581-0eef-42dd-8e2e-afcf7a0399a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602308056 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3602308056
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3612111703
Short name T1064
Test name
Test status
Simulation time 199452494 ps
CPU time 3.14 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:42 PM PDT 24
Peak memory 215688 kb
Host smart-3e3de16f-c11e-4c21-a128-24e6bddebd47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612111703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
612111703
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.58169972
Short name T1060
Test name
Test status
Simulation time 26950344 ps
CPU time 0.72 seconds
Started Jun 26 06:57:40 PM PDT 24
Finished Jun 26 06:57:43 PM PDT 24
Peak memory 204088 kb
Host smart-557894c5-c476-4262-8887-8ccbc3b84e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58169972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.58169972
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2021158516
Short name T1071
Test name
Test status
Simulation time 90046962 ps
CPU time 1.86 seconds
Started Jun 26 06:57:37 PM PDT 24
Finished Jun 26 06:57:40 PM PDT 24
Peak memory 215828 kb
Host smart-62d6c921-bb11-4cfd-91e4-600955775220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021158516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2021158516
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2365474192
Short name T1040
Test name
Test status
Simulation time 126828707 ps
CPU time 1.81 seconds
Started Jun 26 06:57:42 PM PDT 24
Finished Jun 26 06:57:46 PM PDT 24
Peak memory 215848 kb
Host smart-7a7357a0-ba30-42bf-b04f-940dbd736af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365474192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
365474192
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.69371998
Short name T49
Test name
Test status
Simulation time 20599475 ps
CPU time 0.73 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:12 PM PDT 24
Peak memory 205908 kb
Host smart-e174d3ab-c69e-4dd7-b74a-960f7010dc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69371998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.69371998
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3361994901
Short name T445
Test name
Test status
Simulation time 131484642 ps
CPU time 2.45 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 224996 kb
Host smart-6785e8f0-2eb6-4311-9453-64078dd91b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361994901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3361994901
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1584007921
Short name T753
Test name
Test status
Simulation time 12828945 ps
CPU time 0.85 seconds
Started Jun 26 06:59:59 PM PDT 24
Finished Jun 26 07:00:04 PM PDT 24
Peak memory 206992 kb
Host smart-5d1c58af-55ef-4fba-8df4-ade43f609000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584007921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1584007921
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2408060612
Short name T450
Test name
Test status
Simulation time 37443203136 ps
CPU time 131.63 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:02:27 PM PDT 24
Peak memory 257804 kb
Host smart-453f8bb9-a022-451a-b81c-2d81ae5e0311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408060612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2408060612
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2783257874
Short name T449
Test name
Test status
Simulation time 83643557975 ps
CPU time 416.02 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:07:08 PM PDT 24
Peak memory 251760 kb
Host smart-cc24de37-e08d-447e-9e2d-e7c71a108e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783257874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2783257874
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3202215106
Short name T24
Test name
Test status
Simulation time 134021087760 ps
CPU time 282.61 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:04:58 PM PDT 24
Peak memory 249728 kb
Host smart-522a2195-ac15-41d4-9120-5383f72c4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202215106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3202215106
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.200457197
Short name T525
Test name
Test status
Simulation time 581182061 ps
CPU time 13.01 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 224980 kb
Host smart-0e4ab6dc-6159-4177-bcd8-bd026ee0a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200457197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.200457197
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.311865570
Short name T376
Test name
Test status
Simulation time 391135495 ps
CPU time 5.64 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:19 PM PDT 24
Peak memory 228540 kb
Host smart-00266d39-9c13-48ac-b4bc-735b21abaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311865570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.311865570
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2458328748
Short name T865
Test name
Test status
Simulation time 4287469677 ps
CPU time 18.33 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:32 PM PDT 24
Peak memory 236884 kb
Host smart-18caf84e-0dfe-4902-987f-a7958307a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458328748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2458328748
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2526163028
Short name T677
Test name
Test status
Simulation time 98681902 ps
CPU time 1.09 seconds
Started Jun 26 07:00:00 PM PDT 24
Finished Jun 26 07:00:05 PM PDT 24
Peak memory 217140 kb
Host smart-0eb8cb8c-fbba-47d7-8afe-5e2f5b3c4b14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526163028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2526163028
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1096840612
Short name T250
Test name
Test status
Simulation time 3510548520 ps
CPU time 11.98 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 233184 kb
Host smart-33e7cafc-a626-453b-a52d-af08ee466932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096840612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1096840612
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1815031349
Short name T411
Test name
Test status
Simulation time 258535673 ps
CPU time 6.25 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:23 PM PDT 24
Peak memory 222956 kb
Host smart-f99bec69-7111-45a3-92a2-2aeecf05d28a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1815031349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1815031349
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2829848728
Short name T876
Test name
Test status
Simulation time 2885621800 ps
CPU time 19.95 seconds
Started Jun 26 06:59:59 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 217032 kb
Host smart-07473445-0e85-49b5-ba5f-a6fdded85e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829848728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2829848728
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.990870747
Short name T880
Test name
Test status
Simulation time 45825708 ps
CPU time 0.69 seconds
Started Jun 26 06:59:58 PM PDT 24
Finished Jun 26 07:00:01 PM PDT 24
Peak memory 206044 kb
Host smart-f0ca60d1-ebc2-4c34-823b-27a8a4e7ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990870747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.990870747
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2927653933
Short name T295
Test name
Test status
Simulation time 78294806 ps
CPU time 1.34 seconds
Started Jun 26 07:00:00 PM PDT 24
Finished Jun 26 07:00:06 PM PDT 24
Peak memory 208540 kb
Host smart-36fd9027-944f-4048-8d8c-bfc6ac6ddcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927653933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2927653933
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1617610262
Short name T766
Test name
Test status
Simulation time 30781070 ps
CPU time 0.79 seconds
Started Jun 26 06:59:59 PM PDT 24
Finished Jun 26 07:00:03 PM PDT 24
Peak memory 206332 kb
Host smart-bb323032-3c52-4260-9ab7-cea1ecde25e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617610262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1617610262
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3806152524
Short name T970
Test name
Test status
Simulation time 8676675077 ps
CPU time 15.01 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:31 PM PDT 24
Peak memory 233284 kb
Host smart-3167e92e-657a-4e4a-b686-f625b7c01dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806152524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3806152524
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.188209273
Short name T589
Test name
Test status
Simulation time 94288639 ps
CPU time 0.73 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 206232 kb
Host smart-2032309e-983a-4c25-ad9a-89869742b5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188209273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.188209273
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3657632019
Short name T170
Test name
Test status
Simulation time 828052088 ps
CPU time 5.23 seconds
Started Jun 26 07:00:09 PM PDT 24
Finished Jun 26 07:00:16 PM PDT 24
Peak memory 233192 kb
Host smart-1739b5ad-4e27-4d8c-b3f2-f50d78ffcd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657632019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3657632019
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1496146000
Short name T304
Test name
Test status
Simulation time 59453509 ps
CPU time 0.75 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 206316 kb
Host smart-345303df-f96b-45dc-b26f-d5edf3c2d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496146000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1496146000
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.593318799
Short name T175
Test name
Test status
Simulation time 54875049102 ps
CPU time 119.32 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:02:16 PM PDT 24
Peak memory 256048 kb
Host smart-41bac1b8-0bf9-4319-8170-56d8df2d61ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593318799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.593318799
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.148345772
Short name T801
Test name
Test status
Simulation time 3324769914 ps
CPU time 74.82 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:01:28 PM PDT 24
Peak memory 254560 kb
Host smart-20a8d3c0-21c1-42f4-945a-c1532416100b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148345772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.148345772
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.906623872
Short name T479
Test name
Test status
Simulation time 4566397591 ps
CPU time 40.5 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 233320 kb
Host smart-80862fd8-0176-42bd-8bf0-c1909da06755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906623872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.906623872
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2620765369
Short name T440
Test name
Test status
Simulation time 259565420 ps
CPU time 4.58 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 224968 kb
Host smart-332f04e9-d4d1-4bd5-b5cc-461ef4c6cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620765369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2620765369
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1715585657
Short name T451
Test name
Test status
Simulation time 858863228 ps
CPU time 12.26 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:28 PM PDT 24
Peak memory 233100 kb
Host smart-45352dc4-1469-488c-9943-7b5bdabcef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715585657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1715585657
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.706537022
Short name T253
Test name
Test status
Simulation time 5246127509 ps
CPU time 6.94 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 233316 kb
Host smart-ed03ef4b-b405-47ae-8660-55905fb83d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706537022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
706537022
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.622387728
Short name T9
Test name
Test status
Simulation time 502966349 ps
CPU time 7.14 seconds
Started Jun 26 07:00:15 PM PDT 24
Finished Jun 26 07:00:26 PM PDT 24
Peak memory 241028 kb
Host smart-6be1e83b-8841-4190-a767-88749a187107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622387728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.622387728
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1270816831
Short name T864
Test name
Test status
Simulation time 201954634 ps
CPU time 5.76 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:21 PM PDT 24
Peak memory 222700 kb
Host smart-1ddad855-30e7-42fa-bf13-d625acad9768
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270816831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1270816831
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3289158082
Short name T60
Test name
Test status
Simulation time 85308499 ps
CPU time 1.15 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:13 PM PDT 24
Peak memory 236200 kb
Host smart-37a99d1d-455c-4eb2-bdff-a613239467d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289158082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3289158082
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1018722526
Short name T799
Test name
Test status
Simulation time 44028676 ps
CPU time 1.07 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 207484 kb
Host smart-7adae5f1-bfb3-4f7c-a910-11ca54beb74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018722526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1018722526
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3368921997
Short name T478
Test name
Test status
Simulation time 21048794359 ps
CPU time 27.55 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:40 PM PDT 24
Peak memory 216976 kb
Host smart-50d55b56-e7d5-4fc8-83dc-5290f704d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368921997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3368921997
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1517925904
Short name T320
Test name
Test status
Simulation time 800724311 ps
CPU time 4.56 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:21 PM PDT 24
Peak memory 216772 kb
Host smart-8fd18a0c-f93f-488c-ad3d-16ecdccd4fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517925904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1517925904
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2768670336
Short name T576
Test name
Test status
Simulation time 107188147 ps
CPU time 1.39 seconds
Started Jun 26 07:00:09 PM PDT 24
Finished Jun 26 07:00:11 PM PDT 24
Peak memory 216692 kb
Host smart-f931bc92-64b9-459a-aaf0-09725cf9e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768670336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2768670336
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3980947839
Short name T431
Test name
Test status
Simulation time 62653416 ps
CPU time 0.96 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:15 PM PDT 24
Peak memory 207412 kb
Host smart-ff4e3ff4-0bae-49aa-8db5-036059633064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980947839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3980947839
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1276456701
Short name T246
Test name
Test status
Simulation time 1185740241 ps
CPU time 3.58 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:19 PM PDT 24
Peak memory 236576 kb
Host smart-50e9244d-ed1f-46e7-9257-a7c9bf905c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276456701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1276456701
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2220919552
Short name T595
Test name
Test status
Simulation time 12386306 ps
CPU time 0.74 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:51 PM PDT 24
Peak memory 205336 kb
Host smart-18377ee0-6399-4498-8ef3-61fce6b38d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220919552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2220919552
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4226243841
Short name T763
Test name
Test status
Simulation time 20890352516 ps
CPU time 32.25 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:21 PM PDT 24
Peak memory 224992 kb
Host smart-15628b8c-b282-4aee-add4-e94454aeb6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226243841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4226243841
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2655454257
Short name T804
Test name
Test status
Simulation time 67423336 ps
CPU time 0.78 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 206972 kb
Host smart-507bed6e-4282-4a31-8a0d-359eb91d941a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655454257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2655454257
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3293419136
Short name T39
Test name
Test status
Simulation time 12507851761 ps
CPU time 27.59 seconds
Started Jun 26 07:00:45 PM PDT 24
Finished Jun 26 07:01:15 PM PDT 24
Peak memory 238024 kb
Host smart-2396ffac-d253-4441-954e-0cdf838217c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293419136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3293419136
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1182171867
Short name T538
Test name
Test status
Simulation time 2809563325 ps
CPU time 19 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 218152 kb
Host smart-9e7040d3-6952-41be-8642-704acc364faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182171867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1182171867
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.872648245
Short name T498
Test name
Test status
Simulation time 2873231829 ps
CPU time 75.18 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:02:06 PM PDT 24
Peak memory 255252 kb
Host smart-e8f5539b-2ef7-410f-9e71-cba248121ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872648245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.872648245
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1182154708
Short name T541
Test name
Test status
Simulation time 131986185 ps
CPU time 2.26 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 223384 kb
Host smart-45a127e3-d9fa-4ee0-8318-77e2978625ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182154708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1182154708
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.548864014
Short name T523
Test name
Test status
Simulation time 740699041 ps
CPU time 13.49 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:01:05 PM PDT 24
Peak memory 241340 kb
Host smart-ec7ff42d-f8db-45ba-ad69-4cb7ae0632ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548864014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.548864014
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3825659676
Short name T816
Test name
Test status
Simulation time 28510996 ps
CPU time 1.07 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:51 PM PDT 24
Peak memory 217148 kb
Host smart-8ed9564d-a314-427f-8e2e-24588efbea66
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825659676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3825659676
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.269408948
Short name T134
Test name
Test status
Simulation time 119070590 ps
CPU time 2.59 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 233184 kb
Host smart-1516c96f-2e39-48a7-ba33-19b76387adaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269408948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.269408948
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2835681404
Short name T485
Test name
Test status
Simulation time 269130041 ps
CPU time 2.22 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:52 PM PDT 24
Peak memory 224264 kb
Host smart-57d96827-4159-43bc-ad04-2196c76111ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835681404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2835681404
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1449987988
Short name T356
Test name
Test status
Simulation time 5948540213 ps
CPU time 15.22 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:01:07 PM PDT 24
Peak memory 223288 kb
Host smart-e59bd341-9c73-4084-a719-cda7b9a0c7df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449987988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1449987988
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2637321534
Short name T704
Test name
Test status
Simulation time 12239626308 ps
CPU time 91.52 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:02:22 PM PDT 24
Peak memory 257928 kb
Host smart-01d56635-3de2-4ef3-97d5-a18bf5669b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637321534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2637321534
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2493574464
Short name T777
Test name
Test status
Simulation time 27921419607 ps
CPU time 17.73 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 216832 kb
Host smart-5720a465-6644-4b0d-b59b-1da796b007ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493574464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2493574464
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2416340274
Short name T353
Test name
Test status
Simulation time 767867288 ps
CPU time 4.44 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 216804 kb
Host smart-1fb89c77-9643-46d8-8bab-5d9683a50b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416340274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2416340274
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2392183318
Short name T976
Test name
Test status
Simulation time 141573329 ps
CPU time 1.07 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:51 PM PDT 24
Peak memory 216584 kb
Host smart-47df0279-aea8-4c4e-8330-76cfc351e3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392183318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2392183318
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1190224575
Short name T349
Test name
Test status
Simulation time 52675288 ps
CPU time 0.83 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 206372 kb
Host smart-90f470c7-3569-4a32-a0f2-5ce41374b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190224575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1190224575
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.540049651
Short name T497
Test name
Test status
Simulation time 4074163293 ps
CPU time 8.18 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:56 PM PDT 24
Peak memory 225024 kb
Host smart-0fdc4295-fce3-4cb3-9a4b-9bb8485d2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540049651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.540049651
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.927246887
Short name T620
Test name
Test status
Simulation time 19358440 ps
CPU time 0.79 seconds
Started Jun 26 07:01:01 PM PDT 24
Finished Jun 26 07:01:04 PM PDT 24
Peak memory 206220 kb
Host smart-b159b101-41ed-4b3a-bc73-5cea25b8403e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927246887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.927246887
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3177607094
Short name T434
Test name
Test status
Simulation time 280795547 ps
CPU time 5.09 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 233200 kb
Host smart-d3ce1902-cf22-49ca-bbb0-f0c16a1bc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177607094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3177607094
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2665563388
Short name T657
Test name
Test status
Simulation time 17423480 ps
CPU time 0.76 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 205948 kb
Host smart-c4026265-eee4-4d06-8cab-88b7e2761e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665563388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2665563388
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3856411286
Short name T398
Test name
Test status
Simulation time 6313852537 ps
CPU time 18.66 seconds
Started Jun 26 07:00:49 PM PDT 24
Finished Jun 26 07:01:11 PM PDT 24
Peak memory 225056 kb
Host smart-6dacb5d5-69bb-409b-b1af-5c7f119dac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856411286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3856411286
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2269214217
Short name T696
Test name
Test status
Simulation time 21152353203 ps
CPU time 100.76 seconds
Started Jun 26 07:01:00 PM PDT 24
Finished Jun 26 07:02:42 PM PDT 24
Peak memory 255808 kb
Host smart-a74147dc-1cd0-48ae-9e6d-be01f49da6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269214217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2269214217
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2140862145
Short name T191
Test name
Test status
Simulation time 36016575546 ps
CPU time 209 seconds
Started Jun 26 07:00:58 PM PDT 24
Finished Jun 26 07:04:28 PM PDT 24
Peak memory 252004 kb
Host smart-ca44f49a-d8ee-4fd7-9edb-5a31a1566033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140862145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2140862145
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.235739224
Short name T778
Test name
Test status
Simulation time 250339668 ps
CPU time 11.49 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:01:03 PM PDT 24
Peak memory 235056 kb
Host smart-ccb26a89-3a6f-46a4-be27-10ea14d624c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235739224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.235739224
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4142459229
Short name T203
Test name
Test status
Simulation time 277287087 ps
CPU time 6.02 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:56 PM PDT 24
Peak memory 225016 kb
Host smart-f1cd7e0c-2000-4114-902b-16b2b6afe7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142459229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4142459229
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.593175175
Short name T729
Test name
Test status
Simulation time 2688137985 ps
CPU time 11.91 seconds
Started Jun 26 07:00:49 PM PDT 24
Finished Jun 26 07:01:04 PM PDT 24
Peak memory 225016 kb
Host smart-f996dfba-2a70-4ead-b70c-2934d3c8588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593175175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.593175175
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1317897491
Short name T51
Test name
Test status
Simulation time 44866910 ps
CPU time 1.1 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 217140 kb
Host smart-806a3232-1ead-4d9b-b137-0f866fcc7214
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317897491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1317897491
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.589071041
Short name T867
Test name
Test status
Simulation time 498998696 ps
CPU time 5.79 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:57 PM PDT 24
Peak memory 224904 kb
Host smart-4dcf96a0-55bb-4dec-ab2d-39b05d18525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589071041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.589071041
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4243380671
Short name T787
Test name
Test status
Simulation time 72189249 ps
CPU time 2.12 seconds
Started Jun 26 07:00:49 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 224968 kb
Host smart-ff9d812a-0ed0-44f9-8862-679af7e09b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243380671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4243380671
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2687177925
Short name T470
Test name
Test status
Simulation time 293302379 ps
CPU time 6.05 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:55 PM PDT 24
Peak memory 219924 kb
Host smart-be27ffc0-2253-4d0b-8fc3-ef28c1056696
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2687177925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2687177925
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4220696102
Short name T21
Test name
Test status
Simulation time 128364959 ps
CPU time 1.19 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 207652 kb
Host smart-cbf78d01-9006-4f1e-96f3-dd7b9b6e6e7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220696102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4220696102
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4171821676
Short name T747
Test name
Test status
Simulation time 6130734043 ps
CPU time 8.4 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:01:00 PM PDT 24
Peak memory 216468 kb
Host smart-f050d6cf-e246-49ac-9a67-14d1e3531049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171821676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4171821676
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.429812734
Short name T760
Test name
Test status
Simulation time 65853860 ps
CPU time 0.7 seconds
Started Jun 26 07:00:45 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 206072 kb
Host smart-30a16361-2418-4457-812f-56964c8a32c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429812734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.429812734
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2215503056
Short name T890
Test name
Test status
Simulation time 24247499 ps
CPU time 1.1 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:52 PM PDT 24
Peak memory 207972 kb
Host smart-a3d4b5e6-2c26-496e-a2ef-b3e55f40302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215503056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2215503056
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.620625412
Short name T977
Test name
Test status
Simulation time 49963443 ps
CPU time 0.77 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 206336 kb
Host smart-e536e083-1bd2-4ebd-9669-f51813b1feb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620625412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.620625412
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2407138054
Short name T745
Test name
Test status
Simulation time 1233775853 ps
CPU time 8.59 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:59 PM PDT 24
Peak memory 224896 kb
Host smart-4a448095-ec85-49a6-97dc-af322b95c586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407138054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2407138054
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3315971688
Short name T171
Test name
Test status
Simulation time 156028915 ps
CPU time 2.44 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:03 PM PDT 24
Peak memory 233260 kb
Host smart-7610606a-5c0a-426c-9dd5-1c25254ded51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315971688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3315971688
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1071360921
Short name T317
Test name
Test status
Simulation time 22087234 ps
CPU time 0.77 seconds
Started Jun 26 07:01:02 PM PDT 24
Finished Jun 26 07:01:04 PM PDT 24
Peak memory 206308 kb
Host smart-508a62b5-538c-438c-86ed-db38a115aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071360921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1071360921
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.767290499
Short name T265
Test name
Test status
Simulation time 33204416454 ps
CPU time 233.38 seconds
Started Jun 26 07:01:00 PM PDT 24
Finished Jun 26 07:04:55 PM PDT 24
Peak memory 262836 kb
Host smart-27f88f27-d9a7-4bb8-b914-9cc88c9ea937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767290499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.767290499
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1925797208
Short name T815
Test name
Test status
Simulation time 1665041050 ps
CPU time 18.06 seconds
Started Jun 26 07:01:00 PM PDT 24
Finished Jun 26 07:01:19 PM PDT 24
Peak memory 217940 kb
Host smart-e10e5450-1f2c-4403-abe6-c0eebd8dcf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925797208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1925797208
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3061470551
Short name T121
Test name
Test status
Simulation time 18073894622 ps
CPU time 81.36 seconds
Started Jun 26 07:01:01 PM PDT 24
Finished Jun 26 07:02:24 PM PDT 24
Peak memory 241636 kb
Host smart-1360dec5-db7d-4967-b3d1-944c4aa4b799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061470551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3061470551
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1882732954
Short name T510
Test name
Test status
Simulation time 742529021 ps
CPU time 4.02 seconds
Started Jun 26 07:01:02 PM PDT 24
Finished Jun 26 07:01:07 PM PDT 24
Peak memory 225016 kb
Host smart-8bb5d140-c6bd-4d7a-a928-8f722a82750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882732954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1882732954
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2206173507
Short name T683
Test name
Test status
Simulation time 1519458357 ps
CPU time 16.9 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:18 PM PDT 24
Peak memory 233252 kb
Host smart-1e1412f5-2ea5-456c-88ae-5be2b77f4e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206173507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2206173507
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2671658396
Short name T757
Test name
Test status
Simulation time 118030475 ps
CPU time 2.55 seconds
Started Jun 26 07:00:57 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 224960 kb
Host smart-b2362429-3b3e-4923-88c1-a6b9530f5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671658396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2671658396
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2638528971
Short name T633
Test name
Test status
Simulation time 15037162 ps
CPU time 1.03 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 217180 kb
Host smart-e2b65f84-81c6-4753-8a51-eacbf247c513
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638528971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2638528971
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.740449234
Short name T858
Test name
Test status
Simulation time 4439681886 ps
CPU time 14.84 seconds
Started Jun 26 07:01:01 PM PDT 24
Finished Jun 26 07:01:17 PM PDT 24
Peak memory 225252 kb
Host smart-fef4e3b4-280d-4b91-bc5f-f28ba5a43279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740449234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.740449234
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1425464911
Short name T426
Test name
Test status
Simulation time 862726005 ps
CPU time 8.26 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:09 PM PDT 24
Peak memory 233236 kb
Host smart-9f5c2532-9fad-4fda-a96d-367df4b07aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425464911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1425464911
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2475869749
Short name T392
Test name
Test status
Simulation time 751967423 ps
CPU time 7.12 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 222952 kb
Host smart-354ead49-7ed1-4703-98e7-8b05c81977eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2475869749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2475869749
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2016778013
Short name T583
Test name
Test status
Simulation time 7113606739 ps
CPU time 26.09 seconds
Started Jun 26 07:01:02 PM PDT 24
Finished Jun 26 07:01:29 PM PDT 24
Peak memory 216696 kb
Host smart-be423b7c-b80d-480b-9389-8c2b309165f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016778013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2016778013
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2381855647
Short name T519
Test name
Test status
Simulation time 26785744429 ps
CPU time 19.11 seconds
Started Jun 26 07:00:58 PM PDT 24
Finished Jun 26 07:01:18 PM PDT 24
Peak memory 216892 kb
Host smart-1daf2880-a67b-438d-ad53-b766e1f0ac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381855647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2381855647
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.689871206
Short name T635
Test name
Test status
Simulation time 102231546 ps
CPU time 1.53 seconds
Started Jun 26 07:00:58 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 216716 kb
Host smart-7bc66364-ac06-4675-b1b3-8955e1795008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689871206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.689871206
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3733597546
Short name T410
Test name
Test status
Simulation time 189883349 ps
CPU time 0.72 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 206360 kb
Host smart-6d364343-a7d4-46d5-bb78-9c2428f6cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733597546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3733597546
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1047831618
Short name T783
Test name
Test status
Simulation time 12860774075 ps
CPU time 11.54 seconds
Started Jun 26 07:01:02 PM PDT 24
Finished Jun 26 07:01:15 PM PDT 24
Peak memory 233280 kb
Host smart-975a2d06-5ce2-467a-aadb-76ddd325f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047831618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1047831618
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2582510604
Short name T831
Test name
Test status
Simulation time 12213788 ps
CPU time 0.73 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 206240 kb
Host smart-880f0e40-f1a8-4477-98c9-4d959753345b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582510604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2582510604
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2013689154
Short name T545
Test name
Test status
Simulation time 78378286 ps
CPU time 2.72 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:24 PM PDT 24
Peak memory 233192 kb
Host smart-0774202d-9309-4b00-a0e7-606f07fcd224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013689154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2013689154
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3357445201
Short name T851
Test name
Test status
Simulation time 63593711 ps
CPU time 0.85 seconds
Started Jun 26 07:01:01 PM PDT 24
Finished Jun 26 07:01:04 PM PDT 24
Peak memory 206992 kb
Host smart-b71106f2-63dc-44ae-aa93-28bce9380681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357445201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3357445201
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3379498181
Short name T526
Test name
Test status
Simulation time 13035908585 ps
CPU time 92.73 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 249676 kb
Host smart-daa66c83-b578-4523-b6f2-d68b4921f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379498181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3379498181
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2506477889
Short name T158
Test name
Test status
Simulation time 31086147098 ps
CPU time 59.8 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:02:21 PM PDT 24
Peak memory 239460 kb
Host smart-d3395f71-70eb-4878-82d1-fc73c9d10391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506477889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2506477889
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2500514523
Short name T614
Test name
Test status
Simulation time 15232586498 ps
CPU time 62.33 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:02:18 PM PDT 24
Peak memory 238604 kb
Host smart-a01f4459-16d7-4e8d-9e9b-dec69d7690aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500514523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2500514523
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3756673401
Short name T733
Test name
Test status
Simulation time 2056611838 ps
CPU time 18.45 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:39 PM PDT 24
Peak memory 241380 kb
Host smart-2264e641-4899-4e85-b26a-0ce0495665cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756673401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3756673401
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2153611701
Short name T401
Test name
Test status
Simulation time 589357337 ps
CPU time 9.39 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:26 PM PDT 24
Peak memory 224972 kb
Host smart-2cf500a1-47cd-4b0a-8ca4-fe86910d0f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153611701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2153611701
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1950921520
Short name T330
Test name
Test status
Simulation time 1200511891 ps
CPU time 17.7 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 241140 kb
Host smart-8b43baae-120a-42f7-ab50-33068d7494f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950921520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1950921520
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1674105698
Short name T29
Test name
Test status
Simulation time 145277844 ps
CPU time 1.1 seconds
Started Jun 26 07:00:59 PM PDT 24
Finished Jun 26 07:01:01 PM PDT 24
Peak memory 218420 kb
Host smart-ec401310-9d14-4eed-946f-30bfef147f76
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674105698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1674105698
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1526810248
Short name T582
Test name
Test status
Simulation time 236059401 ps
CPU time 3.5 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:19 PM PDT 24
Peak memory 225076 kb
Host smart-1c8d7f00-fd30-4997-812c-b55296c1312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526810248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1526810248
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2222060940
Short name T602
Test name
Test status
Simulation time 5155234743 ps
CPU time 20.21 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:37 PM PDT 24
Peak memory 233308 kb
Host smart-fb0670a1-d56c-44c1-b5aa-e9a90cb36e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222060940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2222060940
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1715653260
Short name T327
Test name
Test status
Simulation time 3070796194 ps
CPU time 9.08 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:28 PM PDT 24
Peak memory 219600 kb
Host smart-9b62ebb0-ba9a-4753-bb21-7cd9f5f0457d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1715653260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1715653260
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.385894128
Short name T286
Test name
Test status
Simulation time 21370396022 ps
CPU time 182.97 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:04:20 PM PDT 24
Peak memory 256188 kb
Host smart-bf6ada29-785f-40a9-a163-735a1d38cdb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385894128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.385894128
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2881583368
Short name T354
Test name
Test status
Simulation time 14210382 ps
CPU time 0.79 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 206084 kb
Host smart-a060cf91-0524-4bf0-956e-440e00921702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881583368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2881583368
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2663915895
Short name T326
Test name
Test status
Simulation time 1620085536 ps
CPU time 4.79 seconds
Started Jun 26 07:01:02 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 216728 kb
Host smart-790fce9e-548b-42e0-b89a-7fa6c2d5d6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663915895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2663915895
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.272370588
Short name T910
Test name
Test status
Simulation time 21752127 ps
CPU time 0.74 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:18 PM PDT 24
Peak memory 206376 kb
Host smart-8c6fbf7e-c4a1-4719-b779-af392281a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272370588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.272370588
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3327034750
Short name T453
Test name
Test status
Simulation time 85226795 ps
CPU time 0.8 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:18 PM PDT 24
Peak memory 206380 kb
Host smart-903bf203-f693-459d-a15c-fbf2e3f0fe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327034750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3327034750
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2427786133
Short name T172
Test name
Test status
Simulation time 17903169608 ps
CPU time 9.89 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:26 PM PDT 24
Peak memory 233232 kb
Host smart-b2c2496c-b24e-42e5-b739-34556bc0ae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427786133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2427786133
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1784976378
Short name T629
Test name
Test status
Simulation time 12716045 ps
CPU time 0.73 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:21 PM PDT 24
Peak memory 205912 kb
Host smart-03777cf4-4dd3-4791-aeb1-a42f023c254f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784976378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1784976378
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1234203812
Short name T580
Test name
Test status
Simulation time 2016707639 ps
CPU time 9.97 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:31 PM PDT 24
Peak memory 233264 kb
Host smart-37edc44f-1265-40d9-b8cd-1fc479dbfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234203812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1234203812
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4196793275
Short name T598
Test name
Test status
Simulation time 54444437 ps
CPU time 0.76 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 205944 kb
Host smart-7d405609-5416-4ef0-a223-2a7667cd33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196793275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4196793275
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1097908716
Short name T824
Test name
Test status
Simulation time 35561456802 ps
CPU time 94.97 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 249624 kb
Host smart-b1b06a6b-ce50-4d72-b992-5e8d9ace0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097908716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1097908716
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1786814687
Short name T770
Test name
Test status
Simulation time 14616572254 ps
CPU time 139.76 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:03:36 PM PDT 24
Peak memory 250460 kb
Host smart-10b98f5d-6179-4c1e-b38c-3059e7591b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786814687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1786814687
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3968046533
Short name T724
Test name
Test status
Simulation time 23542114524 ps
CPU time 79.53 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:02:41 PM PDT 24
Peak memory 252928 kb
Host smart-97162128-9f7a-4461-bbf4-bdc64d0eeb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968046533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3968046533
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2006352562
Short name T592
Test name
Test status
Simulation time 207961110 ps
CPU time 3 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:24 PM PDT 24
Peak memory 233228 kb
Host smart-d4432686-243b-44a7-8b7a-a4c72aebd85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006352562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2006352562
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1426645678
Short name T927
Test name
Test status
Simulation time 2543885289 ps
CPU time 12.97 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 233272 kb
Host smart-474f97cf-051c-4324-9583-9373b3ac3f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426645678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1426645678
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3519151718
Short name T369
Test name
Test status
Simulation time 65251637 ps
CPU time 1.04 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 217176 kb
Host smart-2b98baba-a07e-4e48-b32a-bc0efe7e5f08
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519151718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3519151718
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2743818422
Short name T839
Test name
Test status
Simulation time 737796458 ps
CPU time 4.29 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 224952 kb
Host smart-62f7cf67-b7e7-4aca-b6d2-818f9c386286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743818422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2743818422
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1007324871
Short name T547
Test name
Test status
Simulation time 386075475 ps
CPU time 2.53 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:24 PM PDT 24
Peak memory 225040 kb
Host smart-acb95f1c-5b9f-4440-a465-9ad681b34e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007324871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1007324871
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.54140922
Short name T903
Test name
Test status
Simulation time 489521463 ps
CPU time 7.77 seconds
Started Jun 26 07:01:14 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 220736 kb
Host smart-7d931a00-18a4-4f52-9deb-c508c8cfc255
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=54140922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direc
t.54140922
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.931670692
Short name T329
Test name
Test status
Simulation time 4788176897 ps
CPU time 12.26 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:31 PM PDT 24
Peak memory 216888 kb
Host smart-66556e5c-0673-4550-ab2a-4f9980bf959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931670692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.931670692
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3590092509
Short name T636
Test name
Test status
Simulation time 681885627 ps
CPU time 4.32 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:24 PM PDT 24
Peak memory 216712 kb
Host smart-9e1ccf85-f6f0-4820-90df-c3e22141f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590092509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3590092509
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3740497148
Short name T569
Test name
Test status
Simulation time 75667681 ps
CPU time 1.69 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 216840 kb
Host smart-daabbb44-430d-45a0-bd9b-5878f3a20095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740497148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3740497148
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.668779989
Short name T405
Test name
Test status
Simulation time 131336724 ps
CPU time 0.9 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 207352 kb
Host smart-34786d90-5485-485e-968f-4542f11b785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668779989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.668779989
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3099991077
Short name T235
Test name
Test status
Simulation time 15893824990 ps
CPU time 10.36 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:28 PM PDT 24
Peak memory 233456 kb
Host smart-2dbdcf70-ba8e-4642-9e66-2526520a8fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099991077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3099991077
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1994575405
Short name T950
Test name
Test status
Simulation time 21250424 ps
CPU time 0.73 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 205860 kb
Host smart-48ab8d18-b6af-41f7-a436-76c208212012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994575405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1994575405
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3510793005
Short name T974
Test name
Test status
Simulation time 135248047 ps
CPU time 2.44 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:24 PM PDT 24
Peak memory 225016 kb
Host smart-bbfa2459-1486-4fcb-934d-834db1784968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510793005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3510793005
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1520194435
Short name T91
Test name
Test status
Simulation time 66629744 ps
CPU time 0.74 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:21 PM PDT 24
Peak memory 207300 kb
Host smart-db926e5b-d6ca-475a-a70a-d0d7934a5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520194435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1520194435
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2862270973
Short name T946
Test name
Test status
Simulation time 36837120625 ps
CPU time 254.51 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:05:34 PM PDT 24
Peak memory 249676 kb
Host smart-a4368eb8-8740-4494-a53a-215ef636d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862270973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2862270973
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1779678423
Short name T262
Test name
Test status
Simulation time 18551016101 ps
CPU time 106.54 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:03:05 PM PDT 24
Peak memory 251460 kb
Host smart-51863434-d169-4256-85c9-9ddb5b7de71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779678423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1779678423
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3100420607
Short name T606
Test name
Test status
Simulation time 1549739066 ps
CPU time 29.87 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:50 PM PDT 24
Peak memory 251216 kb
Host smart-3da53354-dd0c-4c31-aa7d-1b4903dc1124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100420607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3100420607
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.692759525
Short name T608
Test name
Test status
Simulation time 1086348876 ps
CPU time 8.76 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:10 PM PDT 24
Peak memory 241432 kb
Host smart-46a18d3b-3b1c-4617-8bc7-29efa621cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692759525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.692759525
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2440169879
Short name T552
Test name
Test status
Simulation time 2669203664 ps
CPU time 22.58 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:43 PM PDT 24
Peak memory 233232 kb
Host smart-d41add15-5022-4bf1-9891-b07049670704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440169879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2440169879
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3801473934
Short name T975
Test name
Test status
Simulation time 18421207276 ps
CPU time 85.34 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 233228 kb
Host smart-679a2f9f-ad2d-4767-8032-489a30cd47ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801473934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3801473934
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.894305604
Short name T301
Test name
Test status
Simulation time 54941583 ps
CPU time 1 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:23 PM PDT 24
Peak memory 218392 kb
Host smart-0c6a1e5c-00bf-4025-bf96-e223691445dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894305604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.894305604
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4001868335
Short name T669
Test name
Test status
Simulation time 1326824207 ps
CPU time 6.77 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:27 PM PDT 24
Peak memory 233188 kb
Host smart-8b68fa2e-bd0e-4b51-a266-1b5992ebef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001868335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4001868335
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1887495302
Short name T731
Test name
Test status
Simulation time 2351512988 ps
CPU time 10.06 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:31 PM PDT 24
Peak memory 233260 kb
Host smart-c4dcdf17-d85b-4677-b547-0e27426ded67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887495302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1887495302
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.679385407
Short name T513
Test name
Test status
Simulation time 11321025913 ps
CPU time 11.19 seconds
Started Jun 26 07:01:14 PM PDT 24
Finished Jun 26 07:01:25 PM PDT 24
Peak memory 221268 kb
Host smart-f3e3bd31-1e06-478a-85cf-d5404d1b6d08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679385407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.679385407
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3403251854
Short name T154
Test name
Test status
Simulation time 12862690965 ps
CPU time 110.02 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:03:08 PM PDT 24
Peak memory 256596 kb
Host smart-d5a3f218-35ea-4998-a118-3e709ea8cebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403251854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3403251854
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2740787282
Short name T462
Test name
Test status
Simulation time 6332156398 ps
CPU time 28.8 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:50 PM PDT 24
Peak memory 216936 kb
Host smart-df270b43-5d8d-475b-8fdf-209f2cd975b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740787282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2740787282
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3600706966
Short name T666
Test name
Test status
Simulation time 21584515 ps
CPU time 0.74 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 206044 kb
Host smart-ab7b6b5e-fe8d-4529-8784-924506a257e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600706966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3600706966
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3606888365
Short name T62
Test name
Test status
Simulation time 185535567 ps
CPU time 1.2 seconds
Started Jun 26 07:01:15 PM PDT 24
Finished Jun 26 07:01:18 PM PDT 24
Peak memory 208556 kb
Host smart-9063d25d-145a-4dc2-b8ac-ef563c1fc70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606888365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3606888365
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.202813057
Short name T932
Test name
Test status
Simulation time 52348674 ps
CPU time 0.79 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:22 PM PDT 24
Peak memory 206328 kb
Host smart-ba7226f9-fa50-4d52-a33f-0c2a6a157c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202813057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.202813057
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.472201660
Short name T714
Test name
Test status
Simulation time 13368851538 ps
CPU time 13.06 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 233188 kb
Host smart-71b5e7ea-0f01-4a87-8a47-41ffe2150a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472201660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.472201660
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.375962694
Short name T591
Test name
Test status
Simulation time 14626183 ps
CPU time 0.72 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 205312 kb
Host smart-5614e008-cc86-42d9-87b1-459694fa49e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375962694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.375962694
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4025477230
Short name T693
Test name
Test status
Simulation time 265596762 ps
CPU time 4.54 seconds
Started Jun 26 07:01:29 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 233196 kb
Host smart-4e9f8e72-6a21-43cc-9f96-c7f31212728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025477230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4025477230
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1927908091
Short name T337
Test name
Test status
Simulation time 29808844 ps
CPU time 0.79 seconds
Started Jun 26 07:01:19 PM PDT 24
Finished Jun 26 07:01:23 PM PDT 24
Peak memory 206996 kb
Host smart-99a44339-7407-4d22-809a-1fe90edbe3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927908091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1927908091
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3924674325
Short name T70
Test name
Test status
Simulation time 84870102101 ps
CPU time 598.86 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:11:30 PM PDT 24
Peak memory 266088 kb
Host smart-d6a37cc0-b392-4b51-801e-2c341ddc70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924674325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3924674325
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2451446479
Short name T195
Test name
Test status
Simulation time 563128133762 ps
CPU time 260.4 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:05:54 PM PDT 24
Peak memory 249680 kb
Host smart-e29dbf6c-e86f-40b6-adfa-e7620eceeea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451446479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2451446479
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3926847254
Short name T231
Test name
Test status
Simulation time 4070720961 ps
CPU time 38.02 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:02:09 PM PDT 24
Peak memory 241136 kb
Host smart-82596f74-d2bc-4bd6-9179-8cc271aacf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926847254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3926847254
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1475860290
Short name T565
Test name
Test status
Simulation time 826427071 ps
CPU time 16.34 seconds
Started Jun 26 07:01:29 PM PDT 24
Finished Jun 26 07:01:47 PM PDT 24
Peak memory 233168 kb
Host smart-0be2039c-51bd-422b-b9b0-f79f9424c6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475860290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1475860290
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.855710956
Short name T948
Test name
Test status
Simulation time 140825884 ps
CPU time 3.33 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:37 PM PDT 24
Peak memory 224932 kb
Host smart-61c518bf-4964-42af-b5e6-f0972af64798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855710956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.855710956
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.466844508
Short name T539
Test name
Test status
Simulation time 5246230458 ps
CPU time 14.29 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:48 PM PDT 24
Peak memory 233276 kb
Host smart-2fd2022e-9f6e-453d-9fc7-4b77bc6c81f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466844508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.466844508
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1041542736
Short name T570
Test name
Test status
Simulation time 46199343 ps
CPU time 1.05 seconds
Started Jun 26 07:01:17 PM PDT 24
Finished Jun 26 07:01:21 PM PDT 24
Peak memory 218460 kb
Host smart-bd585b28-f6de-47d3-904b-417701f241e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041542736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1041542736
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4099986808
Short name T248
Test name
Test status
Simulation time 116537931 ps
CPU time 2.29 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 224932 kb
Host smart-2bdcc9f6-9fdc-4bd4-8efb-65cfd81eeb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099986808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4099986808
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3682306522
Short name T790
Test name
Test status
Simulation time 4351651077 ps
CPU time 11.74 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:46 PM PDT 24
Peak memory 240752 kb
Host smart-eca91a95-a2e8-4ab8-a47c-44ed28de3dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682306522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3682306522
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2582725578
Short name T964
Test name
Test status
Simulation time 949449260 ps
CPU time 4.57 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:39 PM PDT 24
Peak memory 219288 kb
Host smart-7740cb6a-f7ee-4473-8d15-384bb7d4ad67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2582725578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2582725578
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1906406507
Short name T640
Test name
Test status
Simulation time 2058175052 ps
CPU time 22.81 seconds
Started Jun 26 07:01:18 PM PDT 24
Finished Jun 26 07:01:44 PM PDT 24
Peak memory 216976 kb
Host smart-68c25280-fdff-4c28-9ed3-373358368826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906406507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1906406507
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1306585211
Short name T674
Test name
Test status
Simulation time 253188599 ps
CPU time 1.51 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 208256 kb
Host smart-0d6ed65c-129c-41da-af29-1464122f294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306585211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1306585211
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3401003259
Short name T678
Test name
Test status
Simulation time 32609336 ps
CPU time 0.72 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 205988 kb
Host smart-e0d57f1d-ff0d-4f3b-a24e-1af21a1272b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401003259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3401003259
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4200579777
Short name T788
Test name
Test status
Simulation time 410082830 ps
CPU time 0.96 seconds
Started Jun 26 07:01:16 PM PDT 24
Finished Jun 26 07:01:20 PM PDT 24
Peak memory 206364 kb
Host smart-4292d3f9-2342-4244-adf8-f5a3cba3f9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200579777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4200579777
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2362125605
Short name T186
Test name
Test status
Simulation time 57800700864 ps
CPU time 12.07 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:45 PM PDT 24
Peak memory 237444 kb
Host smart-62dcdebd-db07-4787-8557-2afeb7c11932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362125605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2362125605
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1492361808
Short name T323
Test name
Test status
Simulation time 12685885 ps
CPU time 0.74 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 206248 kb
Host smart-ce45b758-2e74-4c28-9626-9ab481173a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492361808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1492361808
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1908105804
Short name T930
Test name
Test status
Simulation time 2020220423 ps
CPU time 5.45 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:37 PM PDT 24
Peak memory 224932 kb
Host smart-170b7fd6-2283-41d3-b05e-f97810fa8f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908105804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1908105804
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.700977882
Short name T566
Test name
Test status
Simulation time 79782309 ps
CPU time 0.82 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 206992 kb
Host smart-ca1bfee6-c806-4c94-9176-8ca2f75a2d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700977882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.700977882
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2490910997
Short name T852
Test name
Test status
Simulation time 14724511749 ps
CPU time 133.77 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 265864 kb
Host smart-8fae5a9b-1cc4-49d2-a06d-634c061f36b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490910997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2490910997
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.630101530
Short name T878
Test name
Test status
Simulation time 5689068893 ps
CPU time 15.65 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:51 PM PDT 24
Peak memory 217816 kb
Host smart-8e6b0a0a-56e2-4c6b-97dd-1c743c084fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630101530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.630101530
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.301849408
Short name T413
Test name
Test status
Simulation time 19305159375 ps
CPU time 158.18 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:04:10 PM PDT 24
Peak memory 256492 kb
Host smart-ad59d9a8-7f19-4a48-abda-880a7500c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301849408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.301849408
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1639827014
Short name T464
Test name
Test status
Simulation time 3818182431 ps
CPU time 41.41 seconds
Started Jun 26 07:01:34 PM PDT 24
Finished Jun 26 07:02:18 PM PDT 24
Peak memory 251204 kb
Host smart-a9a42cd1-c6b6-4eda-912f-34eef0d7dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639827014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1639827014
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2010396759
Short name T8
Test name
Test status
Simulation time 391766354 ps
CPU time 5.35 seconds
Started Jun 26 07:01:29 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 224960 kb
Host smart-65110ee6-8377-4a9a-8d6c-94eea2e507bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010396759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2010396759
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2923091857
Short name T465
Test name
Test status
Simulation time 31738441484 ps
CPU time 160.82 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 251104 kb
Host smart-e6ddf0f8-8f1d-4162-a35a-e3f43d50744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923091857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2923091857
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.726888957
Short name T30
Test name
Test status
Simulation time 15071778 ps
CPU time 1 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 218360 kb
Host smart-d08363bd-6649-4532-82a6-431c958d4f6b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726888957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.726888957
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3605517778
Short name T120
Test name
Test status
Simulation time 271140980 ps
CPU time 3.17 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:37 PM PDT 24
Peak memory 233152 kb
Host smart-03930f81-1784-4e41-8cb4-dd43d8088e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605517778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3605517778
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1201589003
Short name T915
Test name
Test status
Simulation time 140878667 ps
CPU time 3.62 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 233204 kb
Host smart-fb2944e4-77b5-4b0b-9995-c835735f2586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201589003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1201589003
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.786897872
Short name T624
Test name
Test status
Simulation time 11438317465 ps
CPU time 12.69 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:01:47 PM PDT 24
Peak memory 223804 kb
Host smart-df29c673-0338-4eae-9b72-54097a83fb2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=786897872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.786897872
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.891636794
Short name T603
Test name
Test status
Simulation time 6051998511 ps
CPU time 29.84 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:02:05 PM PDT 24
Peak memory 220488 kb
Host smart-69016fc8-ac52-4652-a8a9-d271beeca2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891636794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.891636794
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3159726512
Short name T823
Test name
Test status
Simulation time 15871781448 ps
CPU time 19.63 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:56 PM PDT 24
Peak memory 216816 kb
Host smart-1c7f0e9c-4e79-4b1a-988d-af51632bbd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159726512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3159726512
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4085807274
Short name T661
Test name
Test status
Simulation time 21723688 ps
CPU time 0.69 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 206008 kb
Host smart-9080f16b-ceeb-4ef3-bd49-e28f0dbbd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085807274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4085807274
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3411579602
Short name T717
Test name
Test status
Simulation time 298964424 ps
CPU time 0.85 seconds
Started Jun 26 07:01:28 PM PDT 24
Finished Jun 26 07:01:30 PM PDT 24
Peak memory 206372 kb
Host smart-e8ef1d20-95ea-45d6-a5aa-ad783518e56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411579602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3411579602
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2677241059
Short name T749
Test name
Test status
Simulation time 632132669 ps
CPU time 3.16 seconds
Started Jun 26 07:01:28 PM PDT 24
Finished Jun 26 07:01:32 PM PDT 24
Peak memory 233156 kb
Host smart-5072fac4-e0bf-43fb-a308-0a5a1277451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677241059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2677241059
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1113358196
Short name T626
Test name
Test status
Simulation time 16365684 ps
CPU time 0.76 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 206072 kb
Host smart-8be9e898-5708-4221-973c-d28743ac333c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113358196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1113358196
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2334573460
Short name T227
Test name
Test status
Simulation time 3274119048 ps
CPU time 6.97 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 225024 kb
Host smart-93e2a8af-1e31-49c0-a6e0-266b1ce4989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334573460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2334573460
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1183742222
Short name T310
Test name
Test status
Simulation time 20039462 ps
CPU time 0.8 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:33 PM PDT 24
Peak memory 206996 kb
Host smart-0eac8f00-27c2-4a80-a4d8-0fc7c86af8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183742222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1183742222
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2059320208
Short name T275
Test name
Test status
Simulation time 21830255917 ps
CPU time 141.72 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:03:54 PM PDT 24
Peak memory 233220 kb
Host smart-207d2545-652c-4ae0-be70-46a90c213abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059320208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2059320208
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2726539959
Short name T691
Test name
Test status
Simulation time 27621633089 ps
CPU time 174.06 seconds
Started Jun 26 07:01:27 PM PDT 24
Finished Jun 26 07:04:23 PM PDT 24
Peak memory 250820 kb
Host smart-289cb1bc-354f-4232-8aa2-c3bd86a00427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726539959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2726539959
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.347688279
Short name T27
Test name
Test status
Simulation time 7508492019 ps
CPU time 104.63 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:03:20 PM PDT 24
Peak memory 261392 kb
Host smart-0a39b058-9347-4296-99ee-920bb9f8574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347688279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.347688279
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3719442026
Short name T282
Test name
Test status
Simulation time 3100085219 ps
CPU time 8.8 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:41 PM PDT 24
Peak memory 233284 kb
Host smart-b244cdd7-8826-4ba5-b51d-45e55bcf9b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719442026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3719442026
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.453378668
Short name T679
Test name
Test status
Simulation time 915250639 ps
CPU time 14.25 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:47 PM PDT 24
Peak memory 219136 kb
Host smart-3c92f184-173e-493e-87ac-f35626b86381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453378668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.453378668
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3073813354
Short name T342
Test name
Test status
Simulation time 84631828 ps
CPU time 2.16 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 224944 kb
Host smart-ff13a688-cb4b-404d-9bf0-b1bd666b366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073813354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3073813354
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2757645524
Short name T879
Test name
Test status
Simulation time 45032604 ps
CPU time 1.07 seconds
Started Jun 26 07:01:38 PM PDT 24
Finished Jun 26 07:01:40 PM PDT 24
Peak memory 217184 kb
Host smart-ed26a6e5-369b-4986-bc43-18e31ae7b026
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757645524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2757645524
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2275789611
Short name T959
Test name
Test status
Simulation time 2779069434 ps
CPU time 3.88 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:01:39 PM PDT 24
Peak memory 233252 kb
Host smart-f592d91d-93dc-4061-a8de-18a1f4fd49fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275789611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2275789611
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2519932089
Short name T408
Test name
Test status
Simulation time 11162486112 ps
CPU time 6.96 seconds
Started Jun 26 07:01:29 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 225028 kb
Host smart-89a73f13-0cd1-4a65-998e-2187fcf8736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519932089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2519932089
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.343956665
Short name T415
Test name
Test status
Simulation time 339072462 ps
CPU time 3.42 seconds
Started Jun 26 07:01:29 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 220668 kb
Host smart-358ef51f-e779-4e76-a4df-d946bf281525
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343956665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.343956665
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1406492510
Short name T615
Test name
Test status
Simulation time 207056987 ps
CPU time 1.17 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:33 PM PDT 24
Peak memory 207160 kb
Host smart-f93b28e0-00e7-4709-a4f1-f2a97c6032de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406492510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1406492510
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4130050353
Short name T562
Test name
Test status
Simulation time 7596425971 ps
CPU time 24.92 seconds
Started Jun 26 07:01:28 PM PDT 24
Finished Jun 26 07:01:54 PM PDT 24
Peak memory 216892 kb
Host smart-296d9566-eb35-43d2-9b14-0d6f9e79f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130050353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4130050353
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.546502646
Short name T789
Test name
Test status
Simulation time 11359523 ps
CPU time 0.72 seconds
Started Jun 26 07:01:28 PM PDT 24
Finished Jun 26 07:01:30 PM PDT 24
Peak memory 206104 kb
Host smart-cd5e116d-30f2-45b2-ba62-b615ef15cbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546502646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.546502646
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1875369353
Short name T338
Test name
Test status
Simulation time 266418515 ps
CPU time 3.77 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:40 PM PDT 24
Peak memory 216892 kb
Host smart-742caf2e-4ac1-4c65-bbd4-0e1cab86e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875369353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1875369353
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2902792023
Short name T391
Test name
Test status
Simulation time 52869881 ps
CPU time 0.8 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 206352 kb
Host smart-aa802118-f89d-4626-9dfb-f7fba17d5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902792023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2902792023
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4272894480
Short name T836
Test name
Test status
Simulation time 975202470 ps
CPU time 8.52 seconds
Started Jun 26 07:01:34 PM PDT 24
Finished Jun 26 07:01:45 PM PDT 24
Peak memory 224816 kb
Host smart-c4b67595-3e9d-4f05-883f-0392031e5409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272894480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4272894480
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3183750771
Short name T122
Test name
Test status
Simulation time 43349502 ps
CPU time 0.72 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:01:58 PM PDT 24
Peak memory 205884 kb
Host smart-d810d5af-fb47-476b-bcdb-60e98b199161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183750771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3183750771
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2940465897
Short name T341
Test name
Test status
Simulation time 34212985 ps
CPU time 2.29 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:34 PM PDT 24
Peak memory 232840 kb
Host smart-1e6a7a56-5861-43d4-ab20-1bc67d1a5175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940465897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2940465897
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2984362697
Short name T427
Test name
Test status
Simulation time 30553916 ps
CPU time 0.75 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:33 PM PDT 24
Peak memory 206372 kb
Host smart-c8500829-12ae-4a03-be24-04a5ac32c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984362697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2984362697
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2309746457
Short name T249
Test name
Test status
Simulation time 9721504422 ps
CPU time 58.64 seconds
Started Jun 26 07:01:36 PM PDT 24
Finished Jun 26 07:02:36 PM PDT 24
Peak memory 255908 kb
Host smart-b78d296d-b4e3-48f6-82db-096c5f201f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309746457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2309746457
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1534731373
Short name T793
Test name
Test status
Simulation time 37108608393 ps
CPU time 383.77 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:08:00 PM PDT 24
Peak memory 266732 kb
Host smart-e3ea67e6-8d2a-4e0a-8436-49bf63c88c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534731373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1534731373
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1034205770
Short name T517
Test name
Test status
Simulation time 9656869712 ps
CPU time 18.98 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:02:15 PM PDT 24
Peak memory 217968 kb
Host smart-be167b2d-ee97-4c30-824e-cd34caf05881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034205770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1034205770
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1031275429
Short name T897
Test name
Test status
Simulation time 657364989 ps
CPU time 7.44 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:40 PM PDT 24
Peak memory 224896 kb
Host smart-f36e3503-6198-4911-a287-bf7538eeef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031275429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1031275429
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.714310315
Short name T500
Test name
Test status
Simulation time 6827332085 ps
CPU time 22.5 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:58 PM PDT 24
Peak memory 241100 kb
Host smart-d1bf2a8e-8f1f-4003-8e8d-88f9d1b3ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714310315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.714310315
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.126173214
Short name T954
Test name
Test status
Simulation time 63030117 ps
CPU time 1.06 seconds
Started Jun 26 07:01:33 PM PDT 24
Finished Jun 26 07:01:37 PM PDT 24
Peak memory 217176 kb
Host smart-e5a3c26b-515a-4aac-b30e-75f7362d52f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126173214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.126173214
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1186172570
Short name T940
Test name
Test status
Simulation time 348662564 ps
CPU time 3.47 seconds
Started Jun 26 07:01:34 PM PDT 24
Finished Jun 26 07:01:40 PM PDT 24
Peak memory 224700 kb
Host smart-9cdde6d2-e3c6-457b-be47-099bcde83961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186172570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1186172570
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4010077268
Short name T609
Test name
Test status
Simulation time 2928574442 ps
CPU time 3.12 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 233212 kb
Host smart-6f68ca57-49d6-4299-883a-64b279e86822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010077268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4010077268
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3086097819
Short name T605
Test name
Test status
Simulation time 2751045715 ps
CPU time 4.2 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:36 PM PDT 24
Peak memory 221036 kb
Host smart-41628ae6-5457-46ff-8186-00730605c173
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3086097819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3086097819
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.187663718
Short name T289
Test name
Test status
Simulation time 22675265280 ps
CPU time 26.53 seconds
Started Jun 26 07:01:30 PM PDT 24
Finished Jun 26 07:01:58 PM PDT 24
Peak memory 217200 kb
Host smart-d7e9ca76-02a2-474c-bf37-fdaa9ef95c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187663718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.187663718
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1902790195
Short name T697
Test name
Test status
Simulation time 12043228846 ps
CPU time 16.71 seconds
Started Jun 26 07:01:34 PM PDT 24
Finished Jun 26 07:01:53 PM PDT 24
Peak memory 216840 kb
Host smart-b5b87317-5be3-4b48-bf5b-df82614adab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902790195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1902790195
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2184109716
Short name T47
Test name
Test status
Simulation time 151504107 ps
CPU time 2.21 seconds
Started Jun 26 07:01:34 PM PDT 24
Finished Jun 26 07:01:39 PM PDT 24
Peak memory 216780 kb
Host smart-dc9fca28-d396-411e-8edc-ea4cf92dbdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184109716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2184109716
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1518000794
Short name T856
Test name
Test status
Simulation time 54306660 ps
CPU time 0.84 seconds
Started Jun 26 07:01:31 PM PDT 24
Finished Jun 26 07:01:35 PM PDT 24
Peak memory 206360 kb
Host smart-0e7744cc-7067-4cff-b6f0-4df34269a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518000794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1518000794
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3383184966
Short name T198
Test name
Test status
Simulation time 20945545665 ps
CPU time 30.35 seconds
Started Jun 26 07:01:32 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 225052 kb
Host smart-574cfda1-15ce-4797-a07a-048b2a332c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383184966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3383184966
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1122872705
Short name T659
Test name
Test status
Simulation time 13917891 ps
CPU time 0.75 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 205892 kb
Host smart-1991c092-9776-4926-b85b-e472cb6dcfd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122872705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
122872705
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3154512848
Short name T436
Test name
Test status
Simulation time 1694969491 ps
CPU time 9.59 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:26 PM PDT 24
Peak memory 233188 kb
Host smart-acfb0118-f2c4-4945-bdba-fc3de5bc9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154512848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3154512848
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1208993046
Short name T585
Test name
Test status
Simulation time 152358897 ps
CPU time 0.81 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:15 PM PDT 24
Peak memory 206992 kb
Host smart-838f94a7-e77c-458b-a7be-e3234f31a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208993046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1208993046
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2359709406
Short name T174
Test name
Test status
Simulation time 27222628974 ps
CPU time 75.5 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:01:31 PM PDT 24
Peak memory 255892 kb
Host smart-2ba410ee-5fdd-4032-9291-3e0cea198d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359709406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2359709406
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2013259131
Short name T183
Test name
Test status
Simulation time 73304037313 ps
CPU time 94.49 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:01:51 PM PDT 24
Peak memory 253836 kb
Host smart-c466d31a-e0f0-4ded-a713-a3c00dcff5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013259131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2013259131
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1443922836
Short name T791
Test name
Test status
Simulation time 160381348306 ps
CPU time 356.93 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:06:11 PM PDT 24
Peak memory 256840 kb
Host smart-9f9c9d5d-55d9-40a5-bf33-5c42056d5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443922836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1443922836
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3466252403
Short name T559
Test name
Test status
Simulation time 817470832 ps
CPU time 9.84 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 233136 kb
Host smart-5aa9c652-79c5-4b72-8eb6-6e704cd575e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466252403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3466252403
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1515165166
Short name T921
Test name
Test status
Simulation time 1858175282 ps
CPU time 8.14 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 224928 kb
Host smart-e85edc68-a6e3-4b0b-89db-8f74b6317868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515165166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1515165166
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.85691992
Short name T457
Test name
Test status
Simulation time 5488869347 ps
CPU time 56.89 seconds
Started Jun 26 07:00:08 PM PDT 24
Finished Jun 26 07:01:06 PM PDT 24
Peak memory 233416 kb
Host smart-2f8fa549-0a1d-4f59-b065-2ad9b17c285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85691992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.85691992
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1084143193
Short name T700
Test name
Test status
Simulation time 18277639 ps
CPU time 1.11 seconds
Started Jun 26 07:00:15 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 217352 kb
Host smart-805dce7c-5ed6-4ae3-821e-04fd0cf17477
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084143193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1084143193
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3216330258
Short name T256
Test name
Test status
Simulation time 144570833 ps
CPU time 2.29 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 224940 kb
Host smart-c969558e-0342-4b85-9377-023df787aae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216330258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3216330258
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2655685708
Short name T604
Test name
Test status
Simulation time 23084585844 ps
CPU time 18.41 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:36 PM PDT 24
Peak memory 233248 kb
Host smart-1c900c49-5e52-4c65-82b7-f26b51285d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655685708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2655685708
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3645393705
Short name T136
Test name
Test status
Simulation time 4862175701 ps
CPU time 8 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:25 PM PDT 24
Peak memory 219464 kb
Host smart-bb1b95b1-b2c0-430d-bb65-32d27e18c0e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3645393705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3645393705
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1628115438
Short name T61
Test name
Test status
Simulation time 245278263 ps
CPU time 1.08 seconds
Started Jun 26 07:00:09 PM PDT 24
Finished Jun 26 07:00:11 PM PDT 24
Peak memory 235852 kb
Host smart-f0a20098-ae65-4e27-b7c3-f97609b18004
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628115438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1628115438
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1285513768
Short name T28
Test name
Test status
Simulation time 36851179874 ps
CPU time 193.63 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:03:32 PM PDT 24
Peak memory 263464 kb
Host smart-242700da-d2df-439e-9d39-5b1a38e3a068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285513768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1285513768
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3181526859
Short name T708
Test name
Test status
Simulation time 3537495585 ps
CPU time 10.66 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 220368 kb
Host smart-88ad2bbe-79e7-4049-89d6-564bfbfb5d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181526859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3181526859
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2579683635
Short name T681
Test name
Test status
Simulation time 2873889283 ps
CPU time 2.39 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 208488 kb
Host smart-69eab972-0827-40f3-a025-d468c483ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579683635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2579683635
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2403895646
Short name T685
Test name
Test status
Simulation time 119680303 ps
CPU time 5.15 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 216944 kb
Host smart-2b1558b7-4a8f-4ec5-9f6c-b06598f3fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403895646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2403895646
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.739738367
Short name T722
Test name
Test status
Simulation time 90596780 ps
CPU time 0.78 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:17 PM PDT 24
Peak memory 206428 kb
Host smart-736c71e3-ec80-4552-bcff-aa2b3c02bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739738367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.739738367
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.829842921
Short name T305
Test name
Test status
Simulation time 156665008 ps
CPU time 2.29 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 223580 kb
Host smart-705a33cb-fb66-41fe-8e17-68a743d47976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829842921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.829842921
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2925679858
Short name T331
Test name
Test status
Simulation time 22408865 ps
CPU time 0.7 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:01:59 PM PDT 24
Peak memory 205912 kb
Host smart-05a03d59-dc02-4b18-8eba-84e9d30cd60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925679858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2925679858
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3748834746
Short name T80
Test name
Test status
Simulation time 1559389354 ps
CPU time 8.09 seconds
Started Jun 26 07:02:00 PM PDT 24
Finished Jun 26 07:02:10 PM PDT 24
Peak memory 233180 kb
Host smart-73845a29-6a92-47b9-b607-b40ac9a31824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748834746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3748834746
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.264866079
Short name T362
Test name
Test status
Simulation time 12914671 ps
CPU time 0.79 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:01:59 PM PDT 24
Peak memory 205964 kb
Host smart-88577010-ad94-48eb-b573-894b997cdb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264866079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.264866079
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.246791136
Short name T936
Test name
Test status
Simulation time 2561647104 ps
CPU time 37.21 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:36 PM PDT 24
Peak memory 250812 kb
Host smart-317e2537-4579-469b-94f5-f7df45c0e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246791136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.246791136
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1592986043
Short name T528
Test name
Test status
Simulation time 56854090979 ps
CPU time 63.03 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 257644 kb
Host smart-26f5a958-24a3-4ccc-8493-dcd4dd8826d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592986043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1592986043
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1678632505
Short name T711
Test name
Test status
Simulation time 239945320 ps
CPU time 3.7 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:03 PM PDT 24
Peak memory 224980 kb
Host smart-dc5f3b86-2e22-485d-8040-c99613784e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678632505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1678632505
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3872687789
Short name T884
Test name
Test status
Simulation time 1966931901 ps
CPU time 20.18 seconds
Started Jun 26 07:02:00 PM PDT 24
Finished Jun 26 07:02:22 PM PDT 24
Peak memory 239404 kb
Host smart-e506a4fd-b944-4a90-9925-efb9147d3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872687789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3872687789
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.737389041
Short name T37
Test name
Test status
Simulation time 38561789 ps
CPU time 2.53 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:03 PM PDT 24
Peak memory 233280 kb
Host smart-166d3667-9be6-4344-81d9-122595295e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737389041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.737389041
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.553112393
Short name T241
Test name
Test status
Simulation time 4910402147 ps
CPU time 7.27 seconds
Started Jun 26 07:01:59 PM PDT 24
Finished Jun 26 07:02:09 PM PDT 24
Peak memory 233220 kb
Host smart-5f9b1121-0c9b-4c5d-9ddf-79e3af6ff235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553112393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.553112393
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3957576809
Short name T334
Test name
Test status
Simulation time 1320100111 ps
CPU time 8.17 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:07 PM PDT 24
Peak memory 221352 kb
Host smart-dacf0864-acad-45ff-a2a3-862b9523a166
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3957576809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3957576809
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2244323691
Short name T612
Test name
Test status
Simulation time 5586826263 ps
CPU time 20.71 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:19 PM PDT 24
Peak memory 220632 kb
Host smart-0dcfe4b3-4448-418f-b726-c66dc867e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244323691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2244323691
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.938686025
Short name T670
Test name
Test status
Simulation time 987897587 ps
CPU time 7.44 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:02:05 PM PDT 24
Peak memory 216744 kb
Host smart-73e0fd88-e613-4d0a-b721-159c61484626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938686025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.938686025
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.743603665
Short name T291
Test name
Test status
Simulation time 297958887 ps
CPU time 2.28 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:02 PM PDT 24
Peak memory 216856 kb
Host smart-81446e2a-f473-4243-b4a1-543aaf248e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743603665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.743603665
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2758617874
Short name T76
Test name
Test status
Simulation time 48701647 ps
CPU time 0.83 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:01:58 PM PDT 24
Peak memory 206364 kb
Host smart-db40000c-4cb8-4dac-ba4c-04fd702190e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758617874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2758617874
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.738277628
Short name T389
Test name
Test status
Simulation time 9640676755 ps
CPU time 10.02 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:10 PM PDT 24
Peak memory 225012 kb
Host smart-a5d193f8-2a97-44cf-b7bb-2b81c7f7c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738277628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.738277628
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4185577568
Short name T319
Test name
Test status
Simulation time 14136999 ps
CPU time 0.74 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:01:57 PM PDT 24
Peak memory 205320 kb
Host smart-cf7e68c2-16a3-4488-905b-d8b6aacd3111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185577568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4185577568
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4074028833
Short name T339
Test name
Test status
Simulation time 411201764 ps
CPU time 5.04 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 224976 kb
Host smart-cc65b163-9e46-42c2-b214-9474b638c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074028833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4074028833
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.851249438
Short name T819
Test name
Test status
Simulation time 44262628 ps
CPU time 0.85 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:00 PM PDT 24
Peak memory 207180 kb
Host smart-73e539c6-cb71-45c7-99cd-ac13c9a6abce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851249438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.851249438
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2109332721
Short name T695
Test name
Test status
Simulation time 36873074684 ps
CPU time 261.86 seconds
Started Jun 26 07:02:00 PM PDT 24
Finished Jun 26 07:06:24 PM PDT 24
Peak memory 251112 kb
Host smart-6ecb2170-4afd-4d3a-abeb-b39c1f910c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109332721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2109332721
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3769343491
Short name T877
Test name
Test status
Simulation time 10397473675 ps
CPU time 73.65 seconds
Started Jun 26 07:01:52 PM PDT 24
Finished Jun 26 07:03:08 PM PDT 24
Peak memory 252216 kb
Host smart-f4f9df39-c211-4c10-aa84-a329fb6f4bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769343491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3769343491
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.330401316
Short name T782
Test name
Test status
Simulation time 108758202196 ps
CPU time 242.17 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 266096 kb
Host smart-f1b395e0-5fbd-4e7d-9c58-b1afb7bf6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330401316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.330401316
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1678914649
Short name T382
Test name
Test status
Simulation time 871489938 ps
CPU time 15.8 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:15 PM PDT 24
Peak memory 225112 kb
Host smart-9a9db1ba-856e-4ca0-a82d-942b06c23cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678914649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1678914649
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.818331248
Short name T254
Test name
Test status
Simulation time 518631941 ps
CPU time 5.92 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:06 PM PDT 24
Peak memory 228980 kb
Host smart-f0e7ef08-0c07-4ed4-89ba-838da09c95a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818331248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.818331248
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2050377279
Short name T963
Test name
Test status
Simulation time 588364114 ps
CPU time 18.24 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:02:13 PM PDT 24
Peak memory 239540 kb
Host smart-2883632a-aba0-4900-9d51-d012376a2595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050377279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2050377279
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4175671870
Short name T610
Test name
Test status
Simulation time 120480706 ps
CPU time 2.29 seconds
Started Jun 26 07:01:58 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 232968 kb
Host smart-c98738d9-1867-499f-b5a5-603b5597afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175671870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4175671870
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2623608006
Short name T255
Test name
Test status
Simulation time 3179700668 ps
CPU time 7.76 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:07 PM PDT 24
Peak memory 233292 kb
Host smart-0165cfd7-596e-4d1b-946d-f951ad501b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623608006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2623608006
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3264374337
Short name T379
Test name
Test status
Simulation time 1345095050 ps
CPU time 7.1 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:08 PM PDT 24
Peak memory 222896 kb
Host smart-1d046264-1fc2-457a-a5fa-c7a296856439
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3264374337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3264374337
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2541788684
Short name T207
Test name
Test status
Simulation time 49122950631 ps
CPU time 408.88 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:08:45 PM PDT 24
Peak memory 254128 kb
Host smart-2a5b670e-a854-451d-9109-330cf0b98ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541788684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2541788684
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4107027297
Short name T374
Test name
Test status
Simulation time 3510998144 ps
CPU time 20.9 seconds
Started Jun 26 07:01:53 PM PDT 24
Finished Jun 26 07:02:16 PM PDT 24
Peak memory 216824 kb
Host smart-3da5dab9-3515-4200-b54e-8def67b4ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107027297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4107027297
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2262011812
Short name T466
Test name
Test status
Simulation time 1228949719 ps
CPU time 3.46 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:02 PM PDT 24
Peak memory 216784 kb
Host smart-9dd79ff1-d316-4fd2-b6b4-3a2eaa292d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262011812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2262011812
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3177631003
Short name T715
Test name
Test status
Simulation time 196973422 ps
CPU time 1.71 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:00 PM PDT 24
Peak memory 216828 kb
Host smart-745664f4-3b3d-449b-ac2b-c1c805a7dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177631003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3177631003
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.914642407
Short name T866
Test name
Test status
Simulation time 28167659 ps
CPU time 0.78 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:01:59 PM PDT 24
Peak memory 206344 kb
Host smart-30924a20-6f88-4fc2-a65d-92a2aa466a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914642407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.914642407
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3938787478
Short name T215
Test name
Test status
Simulation time 1395385544 ps
CPU time 5.17 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 224992 kb
Host smart-66597ec1-844b-430c-8b8b-3d12dc8c6a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938787478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3938787478
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2781217095
Short name T119
Test name
Test status
Simulation time 30468734 ps
CPU time 0.84 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:01:59 PM PDT 24
Peak memory 205932 kb
Host smart-fb278678-84c2-46c0-ae3e-88c8e1f04297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781217095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2781217095
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2491116342
Short name T5
Test name
Test status
Simulation time 12497950155 ps
CPU time 15.06 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:14 PM PDT 24
Peak memory 233064 kb
Host smart-efda0e64-b482-40d6-a4d1-8d89989161d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491116342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2491116342
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1804927235
Short name T492
Test name
Test status
Simulation time 33316056 ps
CPU time 0.72 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:01 PM PDT 24
Peak memory 206320 kb
Host smart-963e8e2a-a3c1-491b-afdf-243a850a75d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804927235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1804927235
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1273147497
Short name T268
Test name
Test status
Simulation time 45465013335 ps
CPU time 99.43 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:03:39 PM PDT 24
Peak memory 253436 kb
Host smart-87f1132c-164f-4782-b2f7-75fc6ee930d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273147497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1273147497
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1699239867
Short name T909
Test name
Test status
Simulation time 19602505539 ps
CPU time 47.8 seconds
Started Jun 26 07:01:52 PM PDT 24
Finished Jun 26 07:02:42 PM PDT 24
Peak memory 225196 kb
Host smart-64a1dd57-166e-44f1-b3a9-9368bb28e766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699239867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1699239867
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.576601373
Short name T518
Test name
Test status
Simulation time 2351751642 ps
CPU time 56.66 seconds
Started Jun 26 07:01:50 PM PDT 24
Finished Jun 26 07:02:47 PM PDT 24
Peak memory 250148 kb
Host smart-88c0e465-06f7-4e68-a3e4-26907e114314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576601373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.576601373
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.27565549
Short name T943
Test name
Test status
Simulation time 2802512629 ps
CPU time 43.87 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 224972 kb
Host smart-b3bf9b90-b222-4ad1-bcf1-8d0d28722337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27565549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.27565549
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.975931099
Short name T650
Test name
Test status
Simulation time 781988127 ps
CPU time 8.99 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:09 PM PDT 24
Peak memory 233216 kb
Host smart-be380d70-3f69-49ae-83c2-c34aa49fa26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975931099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.975931099
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2917564057
Short name T200
Test name
Test status
Simulation time 955579908 ps
CPU time 18.36 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:19 PM PDT 24
Peak memory 249144 kb
Host smart-f3c4dd84-a6f3-4045-8134-7ff976feb64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917564057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2917564057
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2218703246
Short name T800
Test name
Test status
Simulation time 7229507054 ps
CPU time 17.88 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:02:16 PM PDT 24
Peak memory 249928 kb
Host smart-00b97db6-4a91-4c1d-8df9-9c4044ad4708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218703246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2218703246
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1067859744
Short name T66
Test name
Test status
Simulation time 1330162359 ps
CPU time 8.77 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:07 PM PDT 24
Peak memory 233160 kb
Host smart-f756421c-2cce-4bda-9186-4e6d420c80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067859744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1067859744
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3188355649
Short name T611
Test name
Test status
Simulation time 3259997744 ps
CPU time 10.16 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:02:07 PM PDT 24
Peak memory 223596 kb
Host smart-0a5a85c0-9c98-434a-8450-51f8065761af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3188355649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3188355649
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1890592207
Short name T488
Test name
Test status
Simulation time 52440932 ps
CPU time 0.98 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:01 PM PDT 24
Peak memory 207520 kb
Host smart-90d7c80a-a711-432b-bb15-7750f16e2d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890592207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1890592207
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4190985730
Short name T680
Test name
Test status
Simulation time 7982122118 ps
CPU time 22.91 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:02:21 PM PDT 24
Peak memory 216832 kb
Host smart-1aaa70c3-9fc5-48fc-b87b-5361617fded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190985730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4190985730
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.901344518
Short name T448
Test name
Test status
Simulation time 1915996497 ps
CPU time 3.23 seconds
Started Jun 26 07:01:59 PM PDT 24
Finished Jun 26 07:02:05 PM PDT 24
Peak memory 216756 kb
Host smart-d7eeec11-604d-4838-bc6c-a4fc06c303a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901344518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.901344518
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.487904740
Short name T675
Test name
Test status
Simulation time 453652561 ps
CPU time 2.12 seconds
Started Jun 26 07:01:52 PM PDT 24
Finished Jun 26 07:01:56 PM PDT 24
Peak memory 216820 kb
Host smart-52ab4c70-e28b-4ce4-84c0-fcb685292865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487904740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.487904740
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2284918086
Short name T652
Test name
Test status
Simulation time 113827565 ps
CPU time 1.11 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:00 PM PDT 24
Peak memory 207412 kb
Host smart-4d738014-1df3-4726-9eaf-ea8c361a0de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284918086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2284918086
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3603040477
Short name T533
Test name
Test status
Simulation time 622009779 ps
CPU time 3.88 seconds
Started Jun 26 07:01:55 PM PDT 24
Finished Jun 26 07:02:03 PM PDT 24
Peak memory 233260 kb
Host smart-4273affa-ea84-45f5-a2cc-1ee11d05ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603040477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3603040477
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.425975345
Short name T328
Test name
Test status
Simulation time 17130362 ps
CPU time 0.73 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:27 PM PDT 24
Peak memory 206236 kb
Host smart-0e9fc895-05ae-4fd3-b0e6-1881c25e9417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425975345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.425975345
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.975297863
Short name T473
Test name
Test status
Simulation time 1182699914 ps
CPU time 7.95 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 224816 kb
Host smart-0963d4f8-98e6-4427-a66e-b1bd6d28a914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975297863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.975297863
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2449258526
Short name T905
Test name
Test status
Simulation time 49639213 ps
CPU time 0.76 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:00 PM PDT 24
Peak memory 207008 kb
Host smart-c409ad16-9226-45a5-b68a-ced8b5f8b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449258526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2449258526
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1834400133
Short name T776
Test name
Test status
Simulation time 56782597015 ps
CPU time 426.53 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:09:31 PM PDT 24
Peak memory 270808 kb
Host smart-a5c5e242-b38e-47dc-addd-eadf90a70817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834400133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1834400133
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.119757741
Short name T48
Test name
Test status
Simulation time 15646177742 ps
CPU time 61.8 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:03:27 PM PDT 24
Peak memory 251508 kb
Host smart-b8c6ab8b-3338-46f2-9c03-84c019acee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119757741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.119757741
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.783487002
Short name T167
Test name
Test status
Simulation time 31732546174 ps
CPU time 145.88 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:04:54 PM PDT 24
Peak memory 249836 kb
Host smart-4c634445-c23d-40d3-93b2-e79bce09b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783487002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.783487002
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.81999122
Short name T750
Test name
Test status
Simulation time 3656690141 ps
CPU time 54.62 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:03:19 PM PDT 24
Peak memory 239412 kb
Host smart-477aaba3-6c60-4320-a15f-228dba40bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81999122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.81999122
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1659104741
Short name T596
Test name
Test status
Simulation time 586554170 ps
CPU time 4.52 seconds
Started Jun 26 07:01:59 PM PDT 24
Finished Jun 26 07:02:06 PM PDT 24
Peak memory 233228 kb
Host smart-1d71a35e-d504-453c-a2d2-10a1fe0f2ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659104741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1659104741
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.621126156
Short name T906
Test name
Test status
Simulation time 1524730686 ps
CPU time 20.78 seconds
Started Jun 26 07:01:57 PM PDT 24
Finished Jun 26 07:02:21 PM PDT 24
Peak memory 240500 kb
Host smart-0ad82358-e0dc-4fb5-9dc9-65a16bc1e5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621126156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.621126156
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.850583015
Short name T507
Test name
Test status
Simulation time 3728012120 ps
CPU time 8.4 seconds
Started Jun 26 07:01:56 PM PDT 24
Finished Jun 26 07:02:08 PM PDT 24
Peak memory 241476 kb
Host smart-f2e35366-a82b-4207-82c3-110a28f2e405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850583015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.850583015
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.173021819
Short name T438
Test name
Test status
Simulation time 29366697 ps
CPU time 1.99 seconds
Started Jun 26 07:01:54 PM PDT 24
Finished Jun 26 07:01:59 PM PDT 24
Peak memory 223588 kb
Host smart-7266771d-f768-42ea-9778-e8a3e7bfa950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173021819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.173021819
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1042245533
Short name T971
Test name
Test status
Simulation time 589120252 ps
CPU time 4.05 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:26 PM PDT 24
Peak memory 223160 kb
Host smart-53911e45-61e7-41f8-89a8-bcba91a80295
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1042245533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1042245533
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1209164044
Short name T277
Test name
Test status
Simulation time 127303521103 ps
CPU time 361.22 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:08:25 PM PDT 24
Peak memory 266092 kb
Host smart-6fc3f6e1-f44f-41f8-8d7e-bdf29cb8ac1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209164044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1209164044
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4150184745
Short name T859
Test name
Test status
Simulation time 1529580482 ps
CPU time 14.89 seconds
Started Jun 26 07:02:00 PM PDT 24
Finished Jun 26 07:02:17 PM PDT 24
Peak memory 216788 kb
Host smart-de7d35a5-6337-40ec-8471-d175cafd3bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150184745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4150184745
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4003062747
Short name T424
Test name
Test status
Simulation time 1755920904 ps
CPU time 3.87 seconds
Started Jun 26 07:01:59 PM PDT 24
Finished Jun 26 07:02:06 PM PDT 24
Peak memory 216724 kb
Host smart-0d9b2e04-cda8-44b4-aa78-fe97d50ec3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003062747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4003062747
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2731975848
Short name T900
Test name
Test status
Simulation time 242949161 ps
CPU time 5.45 seconds
Started Jun 26 07:01:59 PM PDT 24
Finished Jun 26 07:02:07 PM PDT 24
Peak memory 216740 kb
Host smart-ce6dd2df-bb36-4ef7-8ab8-b5896f1e0db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731975848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2731975848
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2363299559
Short name T4
Test name
Test status
Simulation time 62073268 ps
CPU time 0.93 seconds
Started Jun 26 07:01:52 PM PDT 24
Finished Jun 26 07:01:56 PM PDT 24
Peak memory 206556 kb
Host smart-5d2560db-22fe-4410-82bb-463f38ab920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363299559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2363299559
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.905116165
Short name T472
Test name
Test status
Simulation time 2512542333 ps
CPU time 11.66 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 233268 kb
Host smart-2e0dc33f-20aa-45e9-984e-517b37a5924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905116165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.905116165
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4049746409
Short name T752
Test name
Test status
Simulation time 12876685 ps
CPU time 0.77 seconds
Started Jun 26 07:02:20 PM PDT 24
Finished Jun 26 07:02:22 PM PDT 24
Peak memory 205864 kb
Host smart-b8754b75-2b8d-43e0-8b9e-954b68b7b885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049746409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4049746409
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1523863329
Short name T843
Test name
Test status
Simulation time 554505055 ps
CPU time 4.11 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 233324 kb
Host smart-f01d4691-d27e-480a-bf9e-30965cb78175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523863329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1523863329
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2880810870
Short name T300
Test name
Test status
Simulation time 25477546 ps
CPU time 0.79 seconds
Started Jun 26 07:02:20 PM PDT 24
Finished Jun 26 07:02:22 PM PDT 24
Peak memory 206996 kb
Host smart-51ee37c4-f1a9-4102-866e-e34103af3658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880810870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2880810870
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.486656688
Short name T904
Test name
Test status
Simulation time 2741559777 ps
CPU time 70.69 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:03:33 PM PDT 24
Peak memory 265216 kb
Host smart-4e6a97a0-e563-4d6b-b565-209e5c7ac56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486656688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.486656688
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.544992664
Short name T416
Test name
Test status
Simulation time 7445132283 ps
CPU time 26.98 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 249720 kb
Host smart-b0cca3a7-efd1-4db9-8ff8-a156e7eba25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544992664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.544992664
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3281068471
Short name T676
Test name
Test status
Simulation time 1362064281 ps
CPU time 4.78 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 224960 kb
Host smart-4aa852b0-4e86-41a8-b8f5-6f9eb10c3144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281068471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3281068471
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.508011131
Short name T665
Test name
Test status
Simulation time 75856495 ps
CPU time 3.37 seconds
Started Jun 26 07:02:20 PM PDT 24
Finished Jun 26 07:02:24 PM PDT 24
Peak memory 233236 kb
Host smart-eef6a04e-b1a8-4e1d-9b51-b8143cc7fef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508011131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.508011131
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4233919221
Short name T848
Test name
Test status
Simulation time 60417066697 ps
CPU time 111.08 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:04:17 PM PDT 24
Peak memory 249640 kb
Host smart-45a3873d-b96c-4b4b-b48a-802ff16c9a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233919221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4233919221
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4245485206
Short name T882
Test name
Test status
Simulation time 112163039 ps
CPU time 2.09 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:26 PM PDT 24
Peak memory 224940 kb
Host smart-ecbc28ed-148a-453f-bb9e-17a119b3a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245485206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4245485206
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4119372060
Short name T447
Test name
Test status
Simulation time 28903848 ps
CPU time 2.19 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:28 PM PDT 24
Peak memory 223764 kb
Host smart-fbec5202-8276-4b34-be51-9dcda5985b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119372060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4119372060
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2810370245
Short name T530
Test name
Test status
Simulation time 2347746854 ps
CPU time 17.07 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:42 PM PDT 24
Peak memory 220976 kb
Host smart-9e5b466f-b720-4b4c-a1bb-addfaca328a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810370245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2810370245
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4023274197
Short name T896
Test name
Test status
Simulation time 820831934 ps
CPU time 6.88 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 216868 kb
Host smart-d881ae80-16c2-46d3-a9b0-0aeeb2a385c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023274197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4023274197
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1461964957
Short name T743
Test name
Test status
Simulation time 9988313671 ps
CPU time 6.88 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:33 PM PDT 24
Peak memory 216832 kb
Host smart-8a7d56ac-c643-45c7-80b2-e1c11e62d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461964957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1461964957
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1048717775
Short name T363
Test name
Test status
Simulation time 48113359 ps
CPU time 2.86 seconds
Started Jun 26 07:02:20 PM PDT 24
Finished Jun 26 07:02:25 PM PDT 24
Peak memory 216756 kb
Host smart-408987e1-1ad1-456c-8c37-51ae66b088e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048717775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1048717775
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4207595880
Short name T916
Test name
Test status
Simulation time 18074152 ps
CPU time 0.75 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:29 PM PDT 24
Peak memory 206396 kb
Host smart-a78f0ae2-7448-488e-a349-c13019553985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207595880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4207595880
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1984686699
Short name T621
Test name
Test status
Simulation time 2201243920 ps
CPU time 9.35 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 225024 kb
Host smart-2724694a-631b-4bef-b9d5-e960906efd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984686699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1984686699
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4164493696
Short name T313
Test name
Test status
Simulation time 17212450 ps
CPU time 0.73 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:29 PM PDT 24
Peak memory 205344 kb
Host smart-1c1cef21-ec4d-4d57-9089-46670d3498c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164493696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4164493696
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2489728384
Short name T703
Test name
Test status
Simulation time 15573107775 ps
CPU time 12.89 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:36 PM PDT 24
Peak memory 233340 kb
Host smart-077ccbf6-ec83-43bf-b98e-26100b417d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489728384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2489728384
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.276570035
Short name T584
Test name
Test status
Simulation time 53286245 ps
CPU time 0.81 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:28 PM PDT 24
Peak memory 206996 kb
Host smart-221a1cc3-0378-4a2b-8444-50e636f05032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276570035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.276570035
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.118493341
Short name T205
Test name
Test status
Simulation time 6335250614 ps
CPU time 38.8 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 249692 kb
Host smart-e7b30e13-d2f0-4523-a731-a34d77ffd502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118493341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.118493341
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1965161605
Short name T739
Test name
Test status
Simulation time 23900116097 ps
CPU time 35.1 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 219844 kb
Host smart-5514b92b-4ae9-48a9-a50b-e411cf6c151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965161605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1965161605
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2470032689
Short name T765
Test name
Test status
Simulation time 14097815336 ps
CPU time 188.72 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:05:32 PM PDT 24
Peak memory 266588 kb
Host smart-9fc08e04-54f3-49fe-8390-fba9b2774b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470032689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2470032689
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2448905630
Short name T886
Test name
Test status
Simulation time 1099744364 ps
CPU time 23.21 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:47 PM PDT 24
Peak memory 241408 kb
Host smart-518b7766-bc0f-41a1-9e99-91df413ba6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448905630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2448905630
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.633272438
Short name T446
Test name
Test status
Simulation time 2791954770 ps
CPU time 14.15 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:40 PM PDT 24
Peak memory 228308 kb
Host smart-499e02db-24b0-4736-a253-8db9932956d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633272438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.633272438
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1562655763
Short name T214
Test name
Test status
Simulation time 5707141651 ps
CPU time 13.26 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:41 PM PDT 24
Peak memory 233224 kb
Host smart-51ef8b8e-e50e-451c-94f7-b3000a082cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562655763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1562655763
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.958967245
Short name T663
Test name
Test status
Simulation time 111222045 ps
CPU time 2.65 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:27 PM PDT 24
Peak memory 232896 kb
Host smart-e4e5d7f2-1f8b-4227-920d-af0018f714a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958967245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.958967245
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1989749964
Short name T756
Test name
Test status
Simulation time 29335068223 ps
CPU time 24.12 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 241508 kb
Host smart-0f5de5f3-5b13-4e61-bfc4-64acde4c5ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989749964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1989749964
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1387839798
Short name T872
Test name
Test status
Simulation time 1972010552 ps
CPU time 7.42 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 219708 kb
Host smart-3348dbbc-1933-464a-9ca6-200582911690
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1387839798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1387839798
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.389751211
Short name T272
Test name
Test status
Simulation time 38262203008 ps
CPU time 131.79 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:04:39 PM PDT 24
Peak memory 257868 kb
Host smart-cac3c6b9-23b2-4d5e-9e61-a1558af8f6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389751211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.389751211
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3672588452
Short name T441
Test name
Test status
Simulation time 2115187901 ps
CPU time 19.9 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 216748 kb
Host smart-ecff58ce-2071-40e4-ba6b-619ab8e8c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672588452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3672588452
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2563561272
Short name T357
Test name
Test status
Simulation time 24746686552 ps
CPU time 16.32 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:41 PM PDT 24
Peak memory 216668 kb
Host smart-f548d1a1-29c2-42f8-974a-d37fc24f134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563561272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2563561272
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3515105344
Short name T668
Test name
Test status
Simulation time 363350905 ps
CPU time 1.75 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:28 PM PDT 24
Peak memory 216800 kb
Host smart-0d52ed85-e7d2-46af-b657-b9d03ba5b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515105344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3515105344
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3531533520
Short name T962
Test name
Test status
Simulation time 46835739 ps
CPU time 0.77 seconds
Started Jun 26 07:02:32 PM PDT 24
Finished Jun 26 07:02:33 PM PDT 24
Peak memory 206380 kb
Host smart-ab498a0c-8e54-48eb-8e79-de3f3a49ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531533520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3531533520
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3708868240
Short name T825
Test name
Test status
Simulation time 1210461640 ps
CPU time 3.98 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 224964 kb
Host smart-00787470-f4a5-46e3-b4a9-e12472fd5312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708868240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3708868240
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3990651595
Short name T849
Test name
Test status
Simulation time 14171588 ps
CPU time 0.76 seconds
Started Jun 26 07:02:26 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 205388 kb
Host smart-8cf7aa27-90eb-4c56-91c6-2a992c68c793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990651595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3990651595
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4287407009
Short name T81
Test name
Test status
Simulation time 1474637176 ps
CPU time 7.89 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:35 PM PDT 24
Peak memory 233200 kb
Host smart-42efa695-5701-44f6-be4a-15e20bbb282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287407009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4287407009
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.140253158
Short name T373
Test name
Test status
Simulation time 46430842 ps
CPU time 0.84 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 206996 kb
Host smart-2edbd9fb-352f-414d-8e83-208bbdce272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140253158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.140253158
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.357404233
Short name T854
Test name
Test status
Simulation time 10344181442 ps
CPU time 13.73 seconds
Started Jun 26 07:02:27 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 240396 kb
Host smart-4b085aab-f454-4f4c-b8c0-154361e084c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357404233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.357404233
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1042290501
Short name T550
Test name
Test status
Simulation time 92555454 ps
CPU time 0.82 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 217704 kb
Host smart-173101a0-6860-42db-879b-dbfd3aabb153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042290501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1042290501
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.81324412
Short name T961
Test name
Test status
Simulation time 1174178858 ps
CPU time 20.6 seconds
Started Jun 26 07:02:28 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 241400 kb
Host smart-191b9127-3115-4d91-8c1b-7f436378fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81324412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.81324412
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2279844739
Short name T834
Test name
Test status
Simulation time 17370459287 ps
CPU time 42.35 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 233232 kb
Host smart-a69e6d08-4555-47b9-a8aa-b1726b7ce569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279844739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2279844739
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.557652987
Short name T857
Test name
Test status
Simulation time 297122453 ps
CPU time 5.95 seconds
Started Jun 26 07:02:21 PM PDT 24
Finished Jun 26 07:02:29 PM PDT 24
Peak memory 225036 kb
Host smart-a8bc9036-348f-4577-bf8b-111ca4e41080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557652987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.557652987
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.657366245
Short name T672
Test name
Test status
Simulation time 10916626239 ps
CPU time 29.33 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 233256 kb
Host smart-05ecff74-1516-4839-8c5d-34e5c0386bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657366245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.657366245
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3878380787
Short name T969
Test name
Test status
Simulation time 6619707111 ps
CPU time 7.74 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:36 PM PDT 24
Peak memory 233256 kb
Host smart-1f644660-a559-4dbf-954e-1c47e71b7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878380787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3878380787
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.846628717
Short name T7
Test name
Test status
Simulation time 12320703663 ps
CPU time 30.6 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 233228 kb
Host smart-a024d9d7-f13c-4f29-8886-a7cfeba0f04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846628717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.846628717
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2077256996
Short name T315
Test name
Test status
Simulation time 467789395 ps
CPU time 6.36 seconds
Started Jun 26 07:02:28 PM PDT 24
Finished Jun 26 07:02:37 PM PDT 24
Peak memory 223128 kb
Host smart-7f0d2e0f-af22-4609-8689-ec29fb976d6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077256996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2077256996
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.15200206
Short name T978
Test name
Test status
Simulation time 42368867 ps
CPU time 1 seconds
Started Jun 26 07:02:28 PM PDT 24
Finished Jun 26 07:02:32 PM PDT 24
Peak memory 207344 kb
Host smart-7a89b568-dc68-4521-abe2-c867e23018e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15200206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.15200206
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3386404173
Short name T601
Test name
Test status
Simulation time 15921285862 ps
CPU time 25.26 seconds
Started Jun 26 07:02:22 PM PDT 24
Finished Jun 26 07:02:50 PM PDT 24
Peak memory 216908 kb
Host smart-f0af2819-66a4-4b65-bd55-08f5a274f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386404173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3386404173
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.132791726
Short name T428
Test name
Test status
Simulation time 13940888340 ps
CPU time 16.88 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 216908 kb
Host smart-5a25b1a2-f67c-422b-8f33-30c40c490e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132791726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.132791726
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2053668014
Short name T560
Test name
Test status
Simulation time 176462679 ps
CPU time 2.87 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:32 PM PDT 24
Peak memory 216760 kb
Host smart-c8373136-c03f-451f-bd75-432ba5d6bc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053668014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2053668014
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3037942222
Short name T351
Test name
Test status
Simulation time 20580229 ps
CPU time 0.79 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 206404 kb
Host smart-eec7040c-9748-4f7b-b214-9a8d563813b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037942222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3037942222
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2267333541
Short name T684
Test name
Test status
Simulation time 7265861422 ps
CPU time 6.74 seconds
Started Jun 26 07:02:23 PM PDT 24
Finished Jun 26 07:02:32 PM PDT 24
Peak memory 225036 kb
Host smart-76c01518-8c75-40a8-bcac-b5b35047a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267333541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2267333541
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3923609408
Short name T730
Test name
Test status
Simulation time 22365565 ps
CPU time 0.73 seconds
Started Jun 26 07:02:43 PM PDT 24
Finished Jun 26 07:02:46 PM PDT 24
Peak memory 205316 kb
Host smart-3ac25b04-c836-4407-9a40-21ff5dd0f9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923609408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3923609408
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1878193907
Short name T234
Test name
Test status
Simulation time 1738223369 ps
CPU time 17.75 seconds
Started Jun 26 07:02:28 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 224936 kb
Host smart-59b64a35-d5da-4793-b1ba-6142ffee5490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878193907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1878193907
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1838649306
Short name T955
Test name
Test status
Simulation time 189972987 ps
CPU time 0.75 seconds
Started Jun 26 07:02:26 PM PDT 24
Finished Jun 26 07:02:30 PM PDT 24
Peak memory 206360 kb
Host smart-c27bb256-ec94-41f7-a8a8-c9adf439f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838649306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1838649306
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.176299824
Short name T232
Test name
Test status
Simulation time 39628759126 ps
CPU time 293.39 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:07:21 PM PDT 24
Peak memory 265140 kb
Host smart-f0979c38-9fdf-4288-9ef8-bfc82ca586ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176299824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.176299824
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1336356188
Short name T388
Test name
Test status
Simulation time 5534574681 ps
CPU time 74.32 seconds
Started Jun 26 07:02:25 PM PDT 24
Finished Jun 26 07:03:42 PM PDT 24
Peak memory 239920 kb
Host smart-db112127-e978-4735-b2dc-c05f867698ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336356188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1336356188
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1119814110
Short name T786
Test name
Test status
Simulation time 3460320254 ps
CPU time 16.31 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 233260 kb
Host smart-e619b570-92c0-49b9-821d-f674da6b1e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119814110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1119814110
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4270729381
Short name T219
Test name
Test status
Simulation time 127166838 ps
CPU time 2.55 seconds
Started Jun 26 07:02:29 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 227336 kb
Host smart-1d792f38-99f4-4b7d-8c8a-f88474b9838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270729381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4270729381
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4100487612
Short name T240
Test name
Test status
Simulation time 831525425 ps
CPU time 10.05 seconds
Started Jun 26 07:02:29 PM PDT 24
Finished Jun 26 07:02:42 PM PDT 24
Peak memory 233140 kb
Host smart-252fd830-da21-4aae-95e5-78820210f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100487612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4100487612
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3112480419
Short name T487
Test name
Test status
Simulation time 4279856877 ps
CPU time 14.01 seconds
Started Jun 26 07:02:30 PM PDT 24
Finished Jun 26 07:02:46 PM PDT 24
Peak memory 224964 kb
Host smart-17b6c7ae-9d39-476e-bde2-db8e26861c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112480419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3112480419
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1392816628
Short name T511
Test name
Test status
Simulation time 1021178570 ps
CPU time 4.72 seconds
Started Jun 26 07:02:30 PM PDT 24
Finished Jun 26 07:02:36 PM PDT 24
Peak memory 233116 kb
Host smart-6fc2ef1b-5fa6-44c2-966b-59f174123c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392816628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1392816628
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3981389847
Short name T706
Test name
Test status
Simulation time 695053575 ps
CPU time 10.45 seconds
Started Jun 26 07:02:26 PM PDT 24
Finished Jun 26 07:02:40 PM PDT 24
Peak memory 221140 kb
Host smart-b58b3244-c6ed-4da1-b493-aba2c4fb7195
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981389847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3981389847
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3742676455
Short name T169
Test name
Test status
Simulation time 18614602517 ps
CPU time 204.95 seconds
Started Jun 26 07:02:26 PM PDT 24
Finished Jun 26 07:05:55 PM PDT 24
Peak memory 266084 kb
Host smart-2d78363a-8fdf-4f6d-aa57-caf498d4a6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742676455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3742676455
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1270482267
Short name T887
Test name
Test status
Simulation time 45940449 ps
CPU time 0.73 seconds
Started Jun 26 07:02:27 PM PDT 24
Finished Jun 26 07:02:31 PM PDT 24
Peak memory 206184 kb
Host smart-03035654-4682-42dc-81a8-5b2b744e355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270482267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1270482267
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1151500243
Short name T553
Test name
Test status
Simulation time 6316960829 ps
CPU time 16.78 seconds
Started Jun 26 07:02:24 PM PDT 24
Finished Jun 26 07:02:45 PM PDT 24
Peak memory 216872 kb
Host smart-bb9c3783-a55c-4798-a8f1-65f84c2848df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151500243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1151500243
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3472177841
Short name T870
Test name
Test status
Simulation time 3506653649 ps
CPU time 2.73 seconds
Started Jun 26 07:02:30 PM PDT 24
Finished Jun 26 07:02:34 PM PDT 24
Peak memory 216728 kb
Host smart-727f1fbc-2e42-4b2b-9917-7254dec92a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472177841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3472177841
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4167388018
Short name T613
Test name
Test status
Simulation time 50008647 ps
CPU time 0.74 seconds
Started Jun 26 07:02:26 PM PDT 24
Finished Jun 26 07:02:31 PM PDT 24
Peak memory 206448 kb
Host smart-d0826039-bdef-4eb5-9718-a54a287116a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167388018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4167388018
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3046471617
Short name T484
Test name
Test status
Simulation time 65497773 ps
CPU time 2.23 seconds
Started Jun 26 07:02:02 PM PDT 24
Finished Jun 26 07:02:05 PM PDT 24
Peak memory 224908 kb
Host smart-e59b5f6f-5762-45e6-bc8f-b77e998b8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046471617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3046471617
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3010414150
Short name T820
Test name
Test status
Simulation time 60816023 ps
CPU time 0.73 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:02:40 PM PDT 24
Peak memory 205980 kb
Host smart-e2424fb8-b84f-4996-b527-5b4037fe4966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010414150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3010414150
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.646145539
Short name T393
Test name
Test status
Simulation time 6611029976 ps
CPU time 18.29 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:03:05 PM PDT 24
Peak memory 224988 kb
Host smart-4eb613df-5d9b-438c-bdf6-a65af04ff6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646145539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.646145539
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2122446004
Short name T748
Test name
Test status
Simulation time 46727963 ps
CPU time 0.82 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:41 PM PDT 24
Peak memory 207004 kb
Host smart-2ed0c1a8-a7a7-4ecc-bf9e-6b55fcb32159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122446004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2122446004
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.327923549
Short name T923
Test name
Test status
Simulation time 21101960603 ps
CPU time 108.23 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:04:27 PM PDT 24
Peak memory 255268 kb
Host smart-5e550eda-7e85-42b4-97f4-6d38d24eaa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327923549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.327923549
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3354332051
Short name T261
Test name
Test status
Simulation time 13576659041 ps
CPU time 235.2 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:06:38 PM PDT 24
Peak memory 266108 kb
Host smart-f63f5c77-e127-4bd0-b939-359d574b656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354332051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3354332051
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2335115967
Short name T156
Test name
Test status
Simulation time 23188351770 ps
CPU time 47.22 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 249636 kb
Host smart-f9862f19-b99c-4796-b4c2-ef457ab2091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335115967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2335115967
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.168358023
Short name T92
Test name
Test status
Simulation time 680044886 ps
CPU time 9.91 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 225008 kb
Host smart-8fdba37c-8dff-464f-9080-e307a56ea004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168358023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.168358023
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2520521740
Short name T419
Test name
Test status
Simulation time 5388784442 ps
CPU time 11.44 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:54 PM PDT 24
Peak memory 233296 kb
Host smart-705601cf-3c67-49f0-a248-56fcdc7f763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520521740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2520521740
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.391563034
Short name T735
Test name
Test status
Simulation time 3191651752 ps
CPU time 36.24 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:03:15 PM PDT 24
Peak memory 234196 kb
Host smart-c4c433d5-66c0-433a-bace-004c93a061a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391563034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.391563034
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2336996912
Short name T660
Test name
Test status
Simulation time 7396550898 ps
CPU time 15.11 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 233228 kb
Host smart-1d6ea7f6-bade-4950-a229-48d0bda3ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336996912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2336996912
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3202677517
Short name T901
Test name
Test status
Simulation time 416455727 ps
CPU time 5.68 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 249628 kb
Host smart-dea1bec5-0e32-4fe3-8c9e-e1dc364637da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202677517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3202677517
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2495156611
Short name T792
Test name
Test status
Simulation time 6287776893 ps
CPU time 12.23 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 219420 kb
Host smart-6732dc49-41e0-4343-95b6-8d56630f58b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2495156611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2495156611
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1330898438
Short name T627
Test name
Test status
Simulation time 54995855 ps
CPU time 1.17 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 207352 kb
Host smart-7e78a586-25d5-44e6-8ba7-3ba039cc8756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330898438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1330898438
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2314052118
Short name T104
Test name
Test status
Simulation time 4947433370 ps
CPU time 24.41 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 217088 kb
Host smart-827a010c-06e4-4273-96aa-00765a84dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314052118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2314052118
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1447223545
Short name T571
Test name
Test status
Simulation time 2268015626 ps
CPU time 5.87 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 216820 kb
Host smart-1df492bd-c1d0-409b-9ae5-e0629b3f2dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447223545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1447223545
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2630306637
Short name T726
Test name
Test status
Simulation time 57892251 ps
CPU time 0.94 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 207404 kb
Host smart-c2b93c13-e331-4689-9ac0-7ec7c2415a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630306637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2630306637
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4286792706
Short name T649
Test name
Test status
Simulation time 13033027 ps
CPU time 0.69 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 206032 kb
Host smart-30bdfe4f-9f4e-4d86-b71a-d63404c75ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286792706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4286792706
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2118707976
Short name T935
Test name
Test status
Simulation time 1621989976 ps
CPU time 10.59 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 233196 kb
Host smart-45f73ae4-d5b8-44a1-bd30-d7ba784f43d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118707976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2118707976
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2315633359
Short name T796
Test name
Test status
Simulation time 14594067 ps
CPU time 0.7 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:40 PM PDT 24
Peak memory 205876 kb
Host smart-17f30b26-1fe9-4b87-9470-b3f38900d62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315633359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2315633359
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2845591805
Short name T643
Test name
Test status
Simulation time 449117542 ps
CPU time 7.21 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 233156 kb
Host smart-57bc5df6-fb28-468a-ab87-057fcbd59d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845591805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2845591805
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.721718544
Short name T371
Test name
Test status
Simulation time 13395259 ps
CPU time 0.77 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:02:47 PM PDT 24
Peak memory 207004 kb
Host smart-9c243eb2-ac19-4a8f-be99-f41211fed32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721718544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.721718544
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1924337903
Short name T781
Test name
Test status
Simulation time 1429537181 ps
CPU time 13.46 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:02:51 PM PDT 24
Peak memory 224956 kb
Host smart-c89aab35-6b27-4643-a90c-87c89848b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924337903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1924337903
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3664340766
Short name T718
Test name
Test status
Simulation time 9610032409 ps
CPU time 55.38 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 217928 kb
Host smart-0a68fbc3-e6f2-439c-a3e8-cb72353763df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664340766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3664340766
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3667933002
Short name T501
Test name
Test status
Simulation time 6661002254 ps
CPU time 114.01 seconds
Started Jun 26 07:02:54 PM PDT 24
Finished Jun 26 07:04:51 PM PDT 24
Peak memory 249708 kb
Host smart-316dab8f-1082-4182-b4bf-b243896d0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667933002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3667933002
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1464942211
Short name T284
Test name
Test status
Simulation time 47646846 ps
CPU time 3.69 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:02:50 PM PDT 24
Peak memory 233164 kb
Host smart-7d9294f9-95ad-431b-8e45-88a97b997d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464942211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1464942211
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1415799071
Short name T813
Test name
Test status
Simulation time 416117513 ps
CPU time 9.21 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 225092 kb
Host smart-6b8a39f6-1213-4929-a834-8f71fb77883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415799071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1415799071
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1081891361
Short name T853
Test name
Test status
Simulation time 3227422790 ps
CPU time 39.65 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:03:24 PM PDT 24
Peak memory 241084 kb
Host smart-28d76efb-db18-4aa3-a6f4-61d4b418384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081891361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1081891361
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3726349991
Short name T698
Test name
Test status
Simulation time 404320831 ps
CPU time 4.64 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:48 PM PDT 24
Peak memory 225024 kb
Host smart-1c7d6e15-7770-4887-98ca-63e1e5dc19de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726349991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3726349991
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.955030011
Short name T67
Test name
Test status
Simulation time 17400064699 ps
CPU time 26.72 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 233220 kb
Host smart-00be34ca-0606-4729-81b9-3296d139b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955030011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.955030011
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2168612824
Short name T540
Test name
Test status
Simulation time 324307903 ps
CPU time 4.07 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:48 PM PDT 24
Peak memory 221352 kb
Host smart-7bbdd38d-f180-49ab-9e63-8bd67fe74447
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168612824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2168612824
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1452198862
Short name T476
Test name
Test status
Simulation time 64037588026 ps
CPU time 135.56 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:04:58 PM PDT 24
Peak memory 241688 kb
Host smart-281ee5ef-c7b6-4eff-bd3a-22e84500df93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452198862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1452198862
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2618314122
Short name T893
Test name
Test status
Simulation time 2150677522 ps
CPU time 33.64 seconds
Started Jun 26 07:02:37 PM PDT 24
Finished Jun 26 07:03:12 PM PDT 24
Peak memory 217212 kb
Host smart-0a9c80ae-68c2-4b73-8239-7522ea28f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618314122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2618314122
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1729384393
Short name T898
Test name
Test status
Simulation time 28745681189 ps
CPU time 21.37 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:03:04 PM PDT 24
Peak memory 216880 kb
Host smart-ff979d36-b602-40cc-9ddb-1a1d5c2ee5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729384393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1729384393
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1662835377
Short name T292
Test name
Test status
Simulation time 211856345 ps
CPU time 4.17 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:45 PM PDT 24
Peak memory 216752 kb
Host smart-bc7563d0-46cf-4d6b-a887-810c758ba0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662835377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1662835377
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1837187034
Short name T26
Test name
Test status
Simulation time 333000929 ps
CPU time 0.89 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 207392 kb
Host smart-248a6e94-7125-49e7-8c56-a05efbb32508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837187034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1837187034
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3589336961
Short name T671
Test name
Test status
Simulation time 174546922 ps
CPU time 2.92 seconds
Started Jun 26 07:02:43 PM PDT 24
Finished Jun 26 07:02:48 PM PDT 24
Peak memory 224932 kb
Host smart-8bbe720b-c074-42c6-b1f7-b2714d65f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589336961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3589336961
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.733898503
Short name T65
Test name
Test status
Simulation time 21674585 ps
CPU time 0.73 seconds
Started Jun 26 07:00:20 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 205344 kb
Host smart-df0bad8e-d994-44db-ae82-6421a57331e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733898503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.733898503
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2292219984
Short name T494
Test name
Test status
Simulation time 157055919 ps
CPU time 3.09 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:19 PM PDT 24
Peak memory 233216 kb
Host smart-ee3363f5-3ab8-42bc-a16c-fbd5a2f4dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292219984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2292219984
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.989719699
Short name T761
Test name
Test status
Simulation time 39240829 ps
CPU time 0.81 seconds
Started Jun 26 07:00:11 PM PDT 24
Finished Jun 26 07:00:15 PM PDT 24
Peak memory 207296 kb
Host smart-bae97f6c-3742-4c8c-9523-5ac06fbdc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989719699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.989719699
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2544101599
Short name T201
Test name
Test status
Simulation time 12359642831 ps
CPU time 80.3 seconds
Started Jun 26 07:00:25 PM PDT 24
Finished Jun 26 07:01:47 PM PDT 24
Peak memory 264444 kb
Host smart-379c0002-2211-42db-8276-0e3a3e6bbef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544101599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2544101599
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1874600477
Short name T278
Test name
Test status
Simulation time 631414159682 ps
CPU time 326.02 seconds
Started Jun 26 07:00:27 PM PDT 24
Finished Jun 26 07:05:54 PM PDT 24
Peak memory 266936 kb
Host smart-e24f9d71-ae64-4c86-86df-8ac1d143b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874600477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1874600477
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2496589238
Short name T837
Test name
Test status
Simulation time 5417236747 ps
CPU time 28.89 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 217924 kb
Host smart-4abe4009-b333-4922-b0ad-57bb254a0763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496589238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2496589238
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.328165539
Short name T279
Test name
Test status
Simulation time 818545032 ps
CPU time 11.61 seconds
Started Jun 26 07:00:10 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 240300 kb
Host smart-1bd8a5b7-7c97-4a98-9164-2c7d2d5b8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328165539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.328165539
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3431853933
Short name T771
Test name
Test status
Simulation time 5669235936 ps
CPU time 11.35 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:29 PM PDT 24
Peak memory 233288 kb
Host smart-d71ea409-0998-45a5-94c9-b91bbe6fc432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431853933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3431853933
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.613461022
Short name T829
Test name
Test status
Simulation time 282962473 ps
CPU time 5.49 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 224964 kb
Host smart-69003318-ea6c-45c4-8afb-c339078ac62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613461022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.613461022
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1492405734
Short name T333
Test name
Test status
Simulation time 119265120 ps
CPU time 1.18 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:16 PM PDT 24
Peak memory 217152 kb
Host smart-c649c047-7a8d-46da-97b6-3bb979261505
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492405734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1492405734
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1469818772
Short name T516
Test name
Test status
Simulation time 738114204 ps
CPU time 2.94 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 224964 kb
Host smart-ef33bc7e-9e05-42a8-846e-199c0b9523dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469818772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1469818772
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3432402183
Short name T645
Test name
Test status
Simulation time 96128041 ps
CPU time 2.48 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 233212 kb
Host smart-643c670d-a11c-4a7c-8073-b9b29eb235d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432402183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3432402183
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3654618300
Short name T618
Test name
Test status
Simulation time 118323725 ps
CPU time 3.68 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:00:36 PM PDT 24
Peak memory 222968 kb
Host smart-24daad85-d25a-477d-a438-b4a1f2c1f20d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654618300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3654618300
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3141311674
Short name T57
Test name
Test status
Simulation time 339853301 ps
CPU time 1.23 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:00:34 PM PDT 24
Peak memory 237296 kb
Host smart-1fa96a9a-ed40-439c-828c-53034131421b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141311674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3141311674
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3984786408
Short name T370
Test name
Test status
Simulation time 53731503 ps
CPU time 1.07 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:26 PM PDT 24
Peak memory 207500 kb
Host smart-35618632-9a92-4e03-8740-88e014c279de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984786408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3984786408
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2727990330
Short name T772
Test name
Test status
Simulation time 2256422026 ps
CPU time 24.75 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:42 PM PDT 24
Peak memory 216960 kb
Host smart-d1ffcd3e-f4a6-4efb-ade2-9b72f4a65861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727990330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2727990330
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3787921371
Short name T902
Test name
Test status
Simulation time 1658911636 ps
CPU time 3.11 seconds
Started Jun 26 07:00:15 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 216556 kb
Host smart-a72d5905-29ca-449a-bd00-f8ee9f50cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787921371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3787921371
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1837970843
Short name T296
Test name
Test status
Simulation time 452323683 ps
CPU time 3.44 seconds
Started Jun 26 07:00:12 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 216776 kb
Host smart-d2aeaf9d-c28b-4bb4-b04a-500644b584c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837970843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1837970843
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3006633069
Short name T814
Test name
Test status
Simulation time 99357520 ps
CPU time 1.06 seconds
Started Jun 26 07:00:14 PM PDT 24
Finished Jun 26 07:00:18 PM PDT 24
Peak memory 207376 kb
Host smart-d54b5855-ad6b-4bee-b909-68323cb40798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006633069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3006633069
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4196757044
Short name T581
Test name
Test status
Simulation time 843355203 ps
CPU time 2.62 seconds
Started Jun 26 07:00:13 PM PDT 24
Finished Jun 26 07:00:20 PM PDT 24
Peak memory 233120 kb
Host smart-ffa8f580-195f-4cc0-b5df-6d01657e19ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196757044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4196757044
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2210575991
Short name T302
Test name
Test status
Simulation time 119314581 ps
CPU time 0.74 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:41 PM PDT 24
Peak memory 205916 kb
Host smart-9db7f6a3-fa1d-4ad8-97f4-81a3144c71b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210575991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2210575991
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1931321444
Short name T924
Test name
Test status
Simulation time 190731731 ps
CPU time 4.44 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:48 PM PDT 24
Peak memory 233196 kb
Host smart-d4884438-1af5-4c93-8e69-3d5317d716fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931321444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1931321444
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3869713051
Short name T694
Test name
Test status
Simulation time 51096237 ps
CPU time 0.77 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 206144 kb
Host smart-7a029044-0286-4f1c-8ac7-c8ae550746c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869713051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3869713051
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.313007923
Short name T891
Test name
Test status
Simulation time 24897361292 ps
CPU time 49.72 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:03:29 PM PDT 24
Peak memory 249980 kb
Host smart-bbf68ccd-2f90-4ca2-94fa-37b408f77508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313007923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.313007923
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1960883959
Short name T128
Test name
Test status
Simulation time 6555562201 ps
CPU time 47.25 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:03:31 PM PDT 24
Peak memory 249732 kb
Host smart-37b527ce-6643-4325-a095-098e4ca2197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960883959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1960883959
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1079959211
Short name T736
Test name
Test status
Simulation time 9462179527 ps
CPU time 26.92 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:03:13 PM PDT 24
Peak memory 254000 kb
Host smart-ae8a8190-5360-48d4-92ed-47e8978d6f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079959211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1079959211
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3090298093
Short name T699
Test name
Test status
Simulation time 1145324792 ps
CPU time 7.83 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:50 PM PDT 24
Peak memory 249616 kb
Host smart-d876f127-bd02-457c-81af-5bf1bf95b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090298093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3090298093
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2254085199
Short name T775
Test name
Test status
Simulation time 487388127 ps
CPU time 7.35 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:02:54 PM PDT 24
Peak memory 233204 kb
Host smart-8b522ec6-ce28-4ae9-9525-3775170d51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254085199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2254085199
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3896216885
Short name T794
Test name
Test status
Simulation time 1685178913 ps
CPU time 15.25 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:03:02 PM PDT 24
Peak memory 233132 kb
Host smart-098194f4-309c-48e0-b246-865fe46986c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896216885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3896216885
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2741355961
Short name T209
Test name
Test status
Simulation time 32228231725 ps
CPU time 14.44 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 234184 kb
Host smart-7ef6f4a4-7711-4c9f-84bd-7645fe5343fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741355961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2741355961
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1242544853
Short name T474
Test name
Test status
Simulation time 4474254686 ps
CPU time 16.14 seconds
Started Jun 26 07:02:38 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 225068 kb
Host smart-6647d46b-632e-4572-97a9-a1b2ab731b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242544853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1242544853
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1229410150
Short name T335
Test name
Test status
Simulation time 5810456331 ps
CPU time 14.21 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 223688 kb
Host smart-3257706a-11b7-452c-8437-a6217db425ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1229410150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1229410150
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.344520645
Short name T634
Test name
Test status
Simulation time 6406929267 ps
CPU time 20.9 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:03:05 PM PDT 24
Peak memory 217076 kb
Host smart-edddbb3d-e7b6-449e-a482-d5f86d4bde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344520645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.344520645
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4275895445
Short name T638
Test name
Test status
Simulation time 1110865974 ps
CPU time 1.71 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 208356 kb
Host smart-10331d1a-1a47-4808-b103-dd286d40f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275895445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4275895445
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3094195890
Short name T705
Test name
Test status
Simulation time 288081455 ps
CPU time 1.6 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:44 PM PDT 24
Peak memory 216920 kb
Host smart-65a3afdf-629e-4be1-b40a-574a19d05138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094195890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3094195890
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1174967873
Short name T1
Test name
Test status
Simulation time 353529247 ps
CPU time 0.87 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:43 PM PDT 24
Peak memory 206124 kb
Host smart-fad95c9a-4472-42a4-967a-2272082d40d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174967873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1174967873
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1172573061
Short name T869
Test name
Test status
Simulation time 143585974 ps
CPU time 3.75 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 233192 kb
Host smart-edcfbdcc-8da9-42af-99f7-a6fbcd876b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172573061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1172573061
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2468875565
Short name T740
Test name
Test status
Simulation time 36019417 ps
CPU time 0.72 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:42 PM PDT 24
Peak memory 205532 kb
Host smart-50f9c337-c7f4-41ed-aa45-497717dd2e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468875565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2468875565
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1414144947
Short name T139
Test name
Test status
Simulation time 1264001075 ps
CPU time 6.01 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:02:53 PM PDT 24
Peak memory 224996 kb
Host smart-3d461e97-e8aa-4051-b265-fb4ae0420108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414144947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1414144947
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3806804162
Short name T318
Test name
Test status
Simulation time 24604794 ps
CPU time 0.81 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:45 PM PDT 24
Peak memory 206964 kb
Host smart-cd2ab58c-39e1-4846-ae92-2e2374e4ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806804162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3806804162
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3489721694
Short name T493
Test name
Test status
Simulation time 28407731 ps
CPU time 0.77 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 216284 kb
Host smart-a5cf7a34-0d22-4c30-8ff1-d72d54ecbedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489721694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3489721694
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4159935244
Short name T193
Test name
Test status
Simulation time 459013770756 ps
CPU time 369.72 seconds
Started Jun 26 07:02:47 PM PDT 24
Finished Jun 26 07:08:59 PM PDT 24
Peak memory 274236 kb
Host smart-c297bd00-a1d6-458d-8f18-2bc4fbf8db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159935244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4159935244
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.689525346
Short name T593
Test name
Test status
Simulation time 166917090 ps
CPU time 3.86 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 231212 kb
Host smart-a5527739-d087-4d32-a85a-7c54556c6132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689525346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.689525346
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3859775684
Short name T399
Test name
Test status
Simulation time 169916625 ps
CPU time 2.31 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:46 PM PDT 24
Peak memory 224960 kb
Host smart-0511cc3f-5f23-4e21-bc77-ca2a5400a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859775684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3859775684
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2601829705
Short name T861
Test name
Test status
Simulation time 1132505786 ps
CPU time 4.5 seconds
Started Jun 26 07:02:47 PM PDT 24
Finished Jun 26 07:02:54 PM PDT 24
Peak memory 224892 kb
Host smart-52fc7b2f-7f4f-487f-96d5-08874d3a5513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601829705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2601829705
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.282321108
Short name T563
Test name
Test status
Simulation time 1501347821 ps
CPU time 3.23 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:47 PM PDT 24
Peak memory 224948 kb
Host smart-21f8d4ba-0bab-47ae-a0c3-344ae4345d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282321108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.282321108
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4015903641
Short name T723
Test name
Test status
Simulation time 1420442047 ps
CPU time 3.81 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:51 PM PDT 24
Peak memory 224948 kb
Host smart-b5557663-d028-4dbd-9d59-121a328ac4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015903641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4015903641
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3201637702
Short name T544
Test name
Test status
Simulation time 116685843 ps
CPU time 3.76 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:46 PM PDT 24
Peak memory 221100 kb
Host smart-77357f74-0d2c-4128-b82e-32d34bd26113
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201637702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3201637702
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3700140090
Short name T809
Test name
Test status
Simulation time 2678478046 ps
CPU time 31.69 seconds
Started Jun 26 07:02:43 PM PDT 24
Finished Jun 26 07:03:17 PM PDT 24
Peak memory 241488 kb
Host smart-a2438725-c4d5-43ae-b7e1-9d2408e3e022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700140090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3700140090
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.83834276
Short name T522
Test name
Test status
Simulation time 1601333491 ps
CPU time 3.26 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:02:51 PM PDT 24
Peak memory 216824 kb
Host smart-61e63e73-e0be-4bd8-8366-38697c8880fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83834276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.83834276
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4286113363
Short name T471
Test name
Test status
Simulation time 1030709374 ps
CPU time 3.95 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:48 PM PDT 24
Peak memory 216760 kb
Host smart-1e756916-6862-427d-a574-8d45c053c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286113363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4286113363
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.483199267
Short name T439
Test name
Test status
Simulation time 38324721 ps
CPU time 2 seconds
Started Jun 26 07:02:45 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 216748 kb
Host smart-0fb7ce97-4b0a-44f8-9eab-dc56d49a675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483199267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.483199267
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1263200349
Short name T572
Test name
Test status
Simulation time 35516965 ps
CPU time 0.84 seconds
Started Jun 26 07:02:41 PM PDT 24
Finished Jun 26 07:02:45 PM PDT 24
Peak memory 206652 kb
Host smart-4feb045f-7b4c-4b9e-b201-4dcf8e03025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263200349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1263200349
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1224035879
Short name T746
Test name
Test status
Simulation time 22427152232 ps
CPU time 19.23 seconds
Started Jun 26 07:02:46 PM PDT 24
Finished Jun 26 07:03:07 PM PDT 24
Peak memory 237412 kb
Host smart-272957e3-7ea4-4217-948c-fa70986fd456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224035879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1224035879
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1345739912
Short name T454
Test name
Test status
Simulation time 27830026 ps
CPU time 0.71 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:09 PM PDT 24
Peak memory 205304 kb
Host smart-03c8e464-23e2-4edd-bd0c-7a5667f6ab1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345739912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1345739912
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3436539182
Short name T495
Test name
Test status
Simulation time 175797626 ps
CPU time 3.85 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:03:00 PM PDT 24
Peak memory 233132 kb
Host smart-bb82e7d5-38c5-455c-9fea-ff044f397abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436539182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3436539182
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1744084173
Short name T713
Test name
Test status
Simulation time 42550086 ps
CPU time 0.73 seconds
Started Jun 26 07:02:47 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 205920 kb
Host smart-7d97de75-ac48-4898-bfc5-1d57cac988c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744084173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1744084173
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4252206870
Short name T908
Test name
Test status
Simulation time 170644838583 ps
CPU time 292.09 seconds
Started Jun 26 07:02:54 PM PDT 24
Finished Jun 26 07:07:50 PM PDT 24
Peak memory 260004 kb
Host smart-7b7e9a15-73b9-437e-87ed-c5b221c540fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252206870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4252206870
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2092078510
Short name T218
Test name
Test status
Simulation time 73482231954 ps
CPU time 155.55 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:05:32 PM PDT 24
Peak memory 239732 kb
Host smart-8122a581-ca8c-4d08-8986-b5f42c8fb362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092078510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2092078510
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2088712844
Short name T622
Test name
Test status
Simulation time 6911591661 ps
CPU time 59.25 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 250332 kb
Host smart-916bb7c0-16ac-4370-9b0c-34cdb9fd1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088712844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2088712844
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2928749736
Short name T555
Test name
Test status
Simulation time 832344898 ps
CPU time 17.1 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:03:12 PM PDT 24
Peak memory 225024 kb
Host smart-21faf559-fe88-4033-8e14-5af3f639a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928749736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2928749736
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.183222195
Short name T199
Test name
Test status
Simulation time 13940741885 ps
CPU time 35.94 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:03:19 PM PDT 24
Peak memory 225016 kb
Host smart-e3e345a4-aa95-4854-b3d4-0a6b73d3d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183222195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.183222195
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2208720675
Short name T82
Test name
Test status
Simulation time 976976021 ps
CPU time 14.64 seconds
Started Jun 26 07:02:40 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 233220 kb
Host smart-06965553-f602-4208-a18a-2763a1a100ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208720675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2208720675
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1995476400
Short name T817
Test name
Test status
Simulation time 1288231620 ps
CPU time 7.21 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 233208 kb
Host smart-dfe38a52-4a87-475b-96c3-7bf61df2207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995476400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1995476400
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.323549837
Short name T176
Test name
Test status
Simulation time 1955989790 ps
CPU time 3.43 seconds
Started Jun 26 07:02:44 PM PDT 24
Finished Jun 26 07:02:49 PM PDT 24
Peak memory 224940 kb
Host smart-43513ce4-842c-4195-9a5f-4b9a6614a1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323549837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.323549837
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.98259389
Short name T34
Test name
Test status
Simulation time 1134428194 ps
CPU time 5.53 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:03:01 PM PDT 24
Peak memory 219204 kb
Host smart-f3836377-b954-41d9-a77a-f7a52d3a2bb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98259389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.98259389
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3826919516
Short name T390
Test name
Test status
Simulation time 57494787 ps
CPU time 1.09 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 207608 kb
Host smart-88c527a3-e21c-41e9-a0d9-b30cc3ebcc60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826919516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3826919516
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2869688328
Short name T944
Test name
Test status
Simulation time 4811530868 ps
CPU time 24.55 seconds
Started Jun 26 07:02:47 PM PDT 24
Finished Jun 26 07:03:13 PM PDT 24
Peak memory 216848 kb
Host smart-b78e28d6-48bb-4347-b6dd-731cd77946f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869688328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2869688328
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.199195924
Short name T912
Test name
Test status
Simulation time 1471353667 ps
CPU time 9.58 seconds
Started Jun 26 07:02:42 PM PDT 24
Finished Jun 26 07:02:54 PM PDT 24
Peak memory 216680 kb
Host smart-7dcdc049-96f3-417f-80ff-149144dc1d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199195924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.199195924
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4264960382
Short name T293
Test name
Test status
Simulation time 138596838 ps
CPU time 1.69 seconds
Started Jun 26 07:02:47 PM PDT 24
Finished Jun 26 07:02:50 PM PDT 24
Peak memory 216728 kb
Host smart-0f08ed72-4bbb-4c2c-a060-48766f101d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264960382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4264960382
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.721007189
Short name T934
Test name
Test status
Simulation time 323281498 ps
CPU time 0.86 seconds
Started Jun 26 07:02:42 PM PDT 24
Finished Jun 26 07:02:46 PM PDT 24
Peak memory 206312 kb
Host smart-9ac71a14-080f-4f91-b219-8270be62c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721007189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.721007189
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.777297957
Short name T710
Test name
Test status
Simulation time 6390541407 ps
CPU time 8.75 seconds
Started Jun 26 07:02:39 PM PDT 24
Finished Jun 26 07:02:51 PM PDT 24
Peak memory 225028 kb
Host smart-144fd49a-4c44-43b6-80d7-b35e7a39ca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777297957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.777297957
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3091091656
Short name T420
Test name
Test status
Simulation time 13515096 ps
CPU time 0.72 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 206232 kb
Host smart-d4e5b922-490d-423c-9b0f-1b7dae5d2dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091091656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3091091656
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3502638891
Short name T236
Test name
Test status
Simulation time 937008522 ps
CPU time 3.25 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 224880 kb
Host smart-475eba73-1b69-41cb-a4d6-4a207eae6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502638891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3502638891
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2279162282
Short name T437
Test name
Test status
Simulation time 54236215 ps
CPU time 0.81 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:02:53 PM PDT 24
Peak memory 207060 kb
Host smart-c1d7d0ce-7362-45f3-ad67-35a43fa0cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279162282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2279162282
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1094547188
Short name T728
Test name
Test status
Simulation time 6978933941 ps
CPU time 66.03 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:03:58 PM PDT 24
Peak memory 249688 kb
Host smart-97b3345d-47f2-42a1-90b2-bc9c431e1723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094547188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1094547188
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.927140494
Short name T784
Test name
Test status
Simulation time 1133738238 ps
CPU time 14.04 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:03:05 PM PDT 24
Peak memory 233236 kb
Host smart-38dd1fc5-76b3-4114-9302-c201fe6417f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927140494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.927140494
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2494561568
Short name T690
Test name
Test status
Simulation time 10435856918 ps
CPU time 29.48 seconds
Started Jun 26 07:02:55 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 225048 kb
Host smart-99e76cef-fd22-477a-a7cb-32ecba4f0709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494561568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2494561568
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2225855579
Short name T587
Test name
Test status
Simulation time 395311250 ps
CPU time 4.25 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 233172 kb
Host smart-1f9113ec-cfb2-4232-9e45-128452998fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225855579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2225855579
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4070595832
Short name T551
Test name
Test status
Simulation time 1504441200 ps
CPU time 8.67 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:03:00 PM PDT 24
Peak memory 233228 kb
Host smart-99ae45ad-216c-41c8-a4d2-7716344b344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070595832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4070595832
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.46176804
Short name T468
Test name
Test status
Simulation time 2175417093 ps
CPU time 21.87 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:03:16 PM PDT 24
Peak memory 241212 kb
Host smart-d2a1ab69-004b-41b9-a63e-a4f6d474f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46176804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.46176804
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1904946006
Short name T252
Test name
Test status
Simulation time 3946203188 ps
CPU time 12.17 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:03:03 PM PDT 24
Peak memory 233276 kb
Host smart-9f9a38ea-b709-4046-805b-052bf56abbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904946006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1904946006
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2911953946
Short name T378
Test name
Test status
Simulation time 1020048864 ps
CPU time 3.35 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 225008 kb
Host smart-19282c60-4993-4419-81a8-15ecc77519a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911953946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2911953946
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2380091575
Short name T452
Test name
Test status
Simulation time 468813717 ps
CPU time 4.42 seconds
Started Jun 26 07:02:54 PM PDT 24
Finished Jun 26 07:03:02 PM PDT 24
Peak memory 223672 kb
Host smart-66ac6c58-364c-4454-ab1e-142ffe8fa729
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380091575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2380091575
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2099913366
Short name T899
Test name
Test status
Simulation time 6065161980 ps
CPU time 19.46 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:03:13 PM PDT 24
Peak memory 216884 kb
Host smart-e5ba1ff2-eae0-483f-9796-ec4fb8225a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099913366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2099913366
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1479769387
Short name T298
Test name
Test status
Simulation time 21183053 ps
CPU time 0.75 seconds
Started Jun 26 07:02:50 PM PDT 24
Finished Jun 26 07:02:52 PM PDT 24
Peak memory 206288 kb
Host smart-f432bfd6-d593-43b8-9d95-392e84a50079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479769387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1479769387
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3856623012
Short name T651
Test name
Test status
Simulation time 587848404 ps
CPU time 1.87 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 216760 kb
Host smart-769165f4-4c13-4d01-8373-a84a2a11891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856623012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3856623012
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4013055119
Short name T931
Test name
Test status
Simulation time 527377074 ps
CPU time 0.85 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:54 PM PDT 24
Peak memory 206472 kb
Host smart-dbb8199b-b58e-4102-8573-da059992a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013055119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4013055119
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2620341777
Short name T50
Test name
Test status
Simulation time 86387542 ps
CPU time 2.13 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:56 PM PDT 24
Peak memory 224920 kb
Host smart-7412e8eb-c715-4589-b818-8851e540d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620341777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2620341777
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1549976996
Short name T914
Test name
Test status
Simulation time 14568963 ps
CPU time 0.73 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:08 PM PDT 24
Peak memory 205328 kb
Host smart-7a4bfa2e-a722-4175-9a44-459f24147b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549976996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1549976996
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.781323915
Short name T223
Test name
Test status
Simulation time 6024770150 ps
CPU time 10.34 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:18 PM PDT 24
Peak memory 233108 kb
Host smart-b93db51f-475e-4940-a338-41b44274bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781323915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.781323915
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2961534606
Short name T366
Test name
Test status
Simulation time 59110811 ps
CPU time 0.78 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 207012 kb
Host smart-acd3ab8f-e118-4891-b987-b1cebd605405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961534606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2961534606
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2780938013
Short name T744
Test name
Test status
Simulation time 1794073479 ps
CPU time 24.23 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:03:18 PM PDT 24
Peak memory 240776 kb
Host smart-92dfbe35-72ec-4e44-85bc-5f22d988cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780938013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2780938013
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1902521170
Short name T475
Test name
Test status
Simulation time 35817674023 ps
CPU time 197.84 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:06:15 PM PDT 24
Peak memory 249608 kb
Host smart-fada0655-b792-4fad-9b18-d65c1b91cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902521170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1902521170
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.961463124
Short name T764
Test name
Test status
Simulation time 3210982459 ps
CPU time 68.41 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:04:05 PM PDT 24
Peak memory 253924 kb
Host smart-ec037d9f-f907-4c3f-a97a-4ee1d96eccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961463124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.961463124
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3792592752
Short name T630
Test name
Test status
Simulation time 336842839 ps
CPU time 4.11 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:03:02 PM PDT 24
Peak memory 233204 kb
Host smart-e60076be-41fa-4590-bac4-bd6228c8e961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792592752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3792592752
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.816448321
Short name T257
Test name
Test status
Simulation time 1057495334 ps
CPU time 15.48 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 224984 kb
Host smart-a70267fd-5e07-4eae-82d6-8fb7e3a94efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816448321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.816448321
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.918506546
Short name T521
Test name
Test status
Simulation time 3090712168 ps
CPU time 15.41 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 249168 kb
Host smart-35b11993-8f3d-4999-b0f5-8aee97486dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918506546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.918506546
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4052781764
Short name T642
Test name
Test status
Simulation time 487506377 ps
CPU time 4.32 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 224972 kb
Host smart-c082ac3a-ce07-431b-950c-721bbb4e1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052781764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4052781764
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2438967501
Short name T845
Test name
Test status
Simulation time 16027057475 ps
CPU time 11.32 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 225044 kb
Host smart-7530eead-7e8d-4655-a01f-b7770815f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438967501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2438967501
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1934787651
Short name T827
Test name
Test status
Simulation time 2066625449 ps
CPU time 3.37 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 221192 kb
Host smart-6d8725a4-2809-4902-9183-b1615e252c86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1934787651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1934787651
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2659052690
Short name T433
Test name
Test status
Simulation time 30196020829 ps
CPU time 202.78 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:06:31 PM PDT 24
Peak memory 255868 kb
Host smart-4863bf5e-54af-4881-a78a-88d5b290eb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659052690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2659052690
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3170843622
Short name T406
Test name
Test status
Simulation time 535781475 ps
CPU time 4.96 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:03:01 PM PDT 24
Peak memory 216760 kb
Host smart-0dc68bd0-4362-4201-9432-44072a97d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170843622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3170843622
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2212295090
Short name T758
Test name
Test status
Simulation time 25314497656 ps
CPU time 17.4 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 218044 kb
Host smart-ed981d86-b74d-4466-a522-79d713e1df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212295090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2212295090
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1612807778
Short name T881
Test name
Test status
Simulation time 17306367 ps
CPU time 0.88 seconds
Started Jun 26 07:02:52 PM PDT 24
Finished Jun 26 07:02:57 PM PDT 24
Peak memory 207396 kb
Host smart-bda4bd6a-fefd-435b-a79a-c2642bb35079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612807778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1612807778
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2040007028
Short name T617
Test name
Test status
Simulation time 78156983 ps
CPU time 0.8 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 206428 kb
Host smart-cf9a55ca-7364-454d-a8dc-c8aa9df83a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040007028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2040007028
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3291258162
Short name T239
Test name
Test status
Simulation time 10093460022 ps
CPU time 29.88 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:38 PM PDT 24
Peak memory 240724 kb
Host smart-521fa784-599f-4a3d-8fd4-45ed4b2090d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291258162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3291258162
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2655028585
Short name T367
Test name
Test status
Simulation time 12478798 ps
CPU time 0.71 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 206164 kb
Host smart-d95719a6-ffe4-4f90-be08-6e35d7a0cd97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655028585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2655028585
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3199372610
Short name T863
Test name
Test status
Simulation time 376390548 ps
CPU time 3.37 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:07 PM PDT 24
Peak memory 233192 kb
Host smart-8232c416-8151-4a52-aca4-6b06128981c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199372610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3199372610
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2317773469
Short name T973
Test name
Test status
Simulation time 38056634 ps
CPU time 0.79 seconds
Started Jun 26 07:02:53 PM PDT 24
Finished Jun 26 07:02:58 PM PDT 24
Peak memory 207336 kb
Host smart-85d15f02-5d8a-4708-98b1-dafef927f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317773469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2317773469
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3672947382
Short name T812
Test name
Test status
Simulation time 144235695298 ps
CPU time 244.1 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:07:09 PM PDT 24
Peak memory 256784 kb
Host smart-20b0eb67-f24a-4a99-bfb3-30ee7cc17d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672947382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3672947382
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2400597774
Short name T945
Test name
Test status
Simulation time 57937477107 ps
CPU time 247.69 seconds
Started Jun 26 07:03:06 PM PDT 24
Finished Jun 26 07:07:16 PM PDT 24
Peak memory 265956 kb
Host smart-37249b87-6328-4056-81e6-c337babdd528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400597774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2400597774
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4245497578
Short name T185
Test name
Test status
Simulation time 5230995592 ps
CPU time 66.79 seconds
Started Jun 26 07:03:04 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 262316 kb
Host smart-a2212443-65ef-4271-82f7-fc06fd70a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245497578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4245497578
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.393951631
Short name T833
Test name
Test status
Simulation time 1306910308 ps
CPU time 27.11 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:32 PM PDT 24
Peak memory 234248 kb
Host smart-7675104b-1272-4aa7-af62-10e59d49e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393951631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.393951631
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.605909132
Short name T838
Test name
Test status
Simulation time 544597561 ps
CPU time 8.11 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 221004 kb
Host smart-5046f9ec-13be-4a5a-b194-cb6b71e39c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605909132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.605909132
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3796750001
Short name T810
Test name
Test status
Simulation time 429704917 ps
CPU time 2.47 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 232924 kb
Host smart-4a7854d7-89ca-48b3-a7f6-835a3e9516cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796750001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3796750001
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2606043506
Short name T707
Test name
Test status
Simulation time 234788709 ps
CPU time 2.72 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 224904 kb
Host smart-bbd67879-5dba-47aa-af00-4dcff421784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606043506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2606043506
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1074955142
Short name T623
Test name
Test status
Simulation time 26759172497 ps
CPU time 17.86 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 233248 kb
Host smart-90e037b4-6e1c-4172-ab14-cdef063cf0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074955142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1074955142
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4198484539
Short name T577
Test name
Test status
Simulation time 4810681425 ps
CPU time 9.54 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:14 PM PDT 24
Peak memory 222448 kb
Host smart-e086aeab-0b99-438e-a05b-e43a168b5f95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198484539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4198484539
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1624773288
Short name T967
Test name
Test status
Simulation time 43114868749 ps
CPU time 98.31 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:04:42 PM PDT 24
Peak memory 257144 kb
Host smart-aa5d1e66-0c3e-4bcb-9444-a48aeb4ecd85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624773288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1624773288
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4278690088
Short name T832
Test name
Test status
Simulation time 12256540522 ps
CPU time 28.55 seconds
Started Jun 26 07:02:55 PM PDT 24
Finished Jun 26 07:03:27 PM PDT 24
Peak memory 216868 kb
Host smart-af31127a-b268-42b6-bda7-2b213472800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278690088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4278690088
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.872796253
Short name T573
Test name
Test status
Simulation time 1323403206 ps
CPU time 1.57 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:09 PM PDT 24
Peak memory 207448 kb
Host smart-da9d114b-0d5b-409c-b9b1-347d138d8416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872796253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.872796253
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2069448475
Short name T504
Test name
Test status
Simulation time 24657071 ps
CPU time 0.86 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:09 PM PDT 24
Peak memory 206964 kb
Host smart-4b55afa2-bdf1-485d-b0f1-9419bf8d3df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069448475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2069448475
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3005859135
Short name T312
Test name
Test status
Simulation time 33303334 ps
CPU time 0.88 seconds
Started Jun 26 07:02:51 PM PDT 24
Finished Jun 26 07:02:55 PM PDT 24
Peak memory 206376 kb
Host smart-c2eaee8c-d3e4-49ef-9bf8-138ca4847855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005859135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3005859135
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4211474093
Short name T556
Test name
Test status
Simulation time 1419349420 ps
CPU time 6.31 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:11 PM PDT 24
Peak memory 233144 kb
Host smart-13e7e38e-89f0-49e6-9d29-2246d262b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211474093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4211474093
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.326865745
Short name T979
Test name
Test status
Simulation time 12973388 ps
CPU time 0.73 seconds
Started Jun 26 07:03:49 PM PDT 24
Finished Jun 26 07:03:52 PM PDT 24
Peak memory 205336 kb
Host smart-478174b8-d0d3-4625-a6fe-3deb2597f819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326865745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.326865745
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.342490224
Short name T720
Test name
Test status
Simulation time 20471514 ps
CPU time 0.81 seconds
Started Jun 26 07:03:04 PM PDT 24
Finished Jun 26 07:03:07 PM PDT 24
Peak memory 206992 kb
Host smart-2a6072e8-6e4d-44f9-a842-4e207fd18a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342490224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.342490224
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.355939314
Short name T828
Test name
Test status
Simulation time 104716537457 ps
CPU time 180.84 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:06:20 PM PDT 24
Peak memory 264272 kb
Host smart-a6da0b88-a09c-4001-9733-00385ca93e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355939314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.355939314
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1350540357
Short name T575
Test name
Test status
Simulation time 4253887457 ps
CPU time 27.87 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 233348 kb
Host smart-facd6030-8e2c-4937-884c-6f6360c243e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350540357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1350540357
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1625899787
Short name T822
Test name
Test status
Simulation time 19373054086 ps
CPU time 41.67 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:04:00 PM PDT 24
Peak memory 233320 kb
Host smart-57496379-59a9-47ee-ba42-ddcf9b486c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625899787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1625899787
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3472037244
Short name T280
Test name
Test status
Simulation time 11040540364 ps
CPU time 30.03 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 241396 kb
Host smart-67e36365-4bac-47db-b103-535aa6d406cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472037244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3472037244
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.21494019
Short name T225
Test name
Test status
Simulation time 2816695041 ps
CPU time 8.55 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:30 PM PDT 24
Peak memory 225024 kb
Host smart-3892b824-c354-430b-8fd5-c50d97e6287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21494019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.21494019
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1519163105
Short name T527
Test name
Test status
Simulation time 112387489 ps
CPU time 2.25 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:23 PM PDT 24
Peak memory 232972 kb
Host smart-64044235-f82e-46a7-9b9f-268cfac41660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519163105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1519163105
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4093869266
Short name T594
Test name
Test status
Simulation time 2665329232 ps
CPU time 5.3 seconds
Started Jun 26 07:03:06 PM PDT 24
Finished Jun 26 07:03:14 PM PDT 24
Peak memory 241232 kb
Host smart-3e370883-94b8-4cdc-bbfe-8d509e2ea8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093869266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4093869266
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3377221876
Short name T242
Test name
Test status
Simulation time 2493999975 ps
CPU time 9.6 seconds
Started Jun 26 07:03:01 PM PDT 24
Finished Jun 26 07:03:12 PM PDT 24
Peak memory 241276 kb
Host smart-b887b561-7d6d-4e1e-a7ee-40af9c4f3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377221876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3377221876
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1903437962
Short name T631
Test name
Test status
Simulation time 130074886 ps
CPU time 4.42 seconds
Started Jun 26 07:03:23 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 223644 kb
Host smart-6700bcce-e3a4-442d-826d-91e89340fd14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1903437962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1903437962
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3897486143
Short name T43
Test name
Test status
Simulation time 41075392072 ps
CPU time 392.25 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:09:49 PM PDT 24
Peak memory 252100 kb
Host smart-a2ce5b81-0d4f-45f5-8ab3-ff189c290598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897486143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3897486143
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2719033120
Short name T732
Test name
Test status
Simulation time 251109642 ps
CPU time 2.28 seconds
Started Jun 26 07:03:05 PM PDT 24
Finished Jun 26 07:03:10 PM PDT 24
Peak memory 216840 kb
Host smart-ded4065c-29b9-41f9-b1a6-2160aecf5f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719033120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2719033120
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.927841745
Short name T590
Test name
Test status
Simulation time 23065579 ps
CPU time 0.77 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:04 PM PDT 24
Peak memory 206100 kb
Host smart-71a8340d-0131-4704-b515-9be0f0598700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927841745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.927841745
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1313244932
Short name T754
Test name
Test status
Simulation time 81958395 ps
CPU time 1.04 seconds
Started Jun 26 07:03:03 PM PDT 24
Finished Jun 26 07:03:06 PM PDT 24
Peak memory 208540 kb
Host smart-a0fd7066-80ef-40fe-98e1-19a048feaec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313244932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1313244932
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2050217825
Short name T368
Test name
Test status
Simulation time 39093256 ps
CPU time 0.87 seconds
Started Jun 26 07:03:02 PM PDT 24
Finished Jun 26 07:03:04 PM PDT 24
Peak memory 206360 kb
Host smart-2800a37e-24d2-4fd7-9c10-4e8189ab50ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050217825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2050217825
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4099605409
Short name T949
Test name
Test status
Simulation time 1189111639 ps
CPU time 3.86 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 233188 kb
Host smart-a89b565c-f91c-45fa-91e9-d90f4fbd0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099605409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4099605409
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3922622073
Short name T716
Test name
Test status
Simulation time 22482782 ps
CPU time 0.72 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:21 PM PDT 24
Peak memory 205888 kb
Host smart-9447b139-c727-4097-b51e-878ab2bf9b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922622073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3922622073
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.145308595
Short name T737
Test name
Test status
Simulation time 1415211952 ps
CPU time 4.55 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 233264 kb
Host smart-9cdee410-2c79-43bb-a3ff-20c7f25966ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145308595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.145308595
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.852855547
Short name T444
Test name
Test status
Simulation time 78336020 ps
CPU time 0.8 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 206996 kb
Host smart-abfb6489-19d8-473e-8386-3ff4ad935c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852855547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.852855547
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1101421447
Short name T941
Test name
Test status
Simulation time 7494697451 ps
CPU time 95.06 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:04:52 PM PDT 24
Peak memory 263592 kb
Host smart-92b57f1b-91e9-4724-ad53-75692d58f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101421447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1101421447
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4143966868
Short name T173
Test name
Test status
Simulation time 176699248503 ps
CPU time 453.22 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:10:54 PM PDT 24
Peak memory 266112 kb
Host smart-77a7e905-0b93-406e-a778-565e8971d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143966868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4143966868
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3662009941
Short name T202
Test name
Test status
Simulation time 3987739462 ps
CPU time 84.2 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:04:45 PM PDT 24
Peak memory 263528 kb
Host smart-6ece8bc0-c82f-44f4-8e83-47e1363c1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662009941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3662009941
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1483380366
Short name T138
Test name
Test status
Simulation time 1170407191 ps
CPU time 14.95 seconds
Started Jun 26 07:03:15 PM PDT 24
Finished Jun 26 07:03:31 PM PDT 24
Peak memory 241380 kb
Host smart-20827882-1889-47a6-9353-ea7959f1f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483380366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1483380366
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1668902510
Short name T228
Test name
Test status
Simulation time 3127355620 ps
CPU time 18.57 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:39 PM PDT 24
Peak memory 225024 kb
Host smart-1939983f-b96d-4f0e-8af8-01c450975aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668902510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1668902510
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2034195007
Short name T855
Test name
Test status
Simulation time 107379285 ps
CPU time 2.14 seconds
Started Jun 26 07:03:20 PM PDT 24
Finished Jun 26 07:03:24 PM PDT 24
Peak memory 223536 kb
Host smart-284b550b-b58c-4569-89ff-ebc5ef4d20c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034195007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2034195007
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4002251039
Short name T247
Test name
Test status
Simulation time 11500690622 ps
CPU time 17.79 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:38 PM PDT 24
Peak memory 233232 kb
Host smart-89c7efdc-6629-4cb1-aa2e-96e90435840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002251039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4002251039
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3630375158
Short name T386
Test name
Test status
Simulation time 186896993 ps
CPU time 2.67 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 233200 kb
Host smart-463ac20b-39ed-45f3-af39-7fe292a18c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630375158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3630375158
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3844459245
Short name T403
Test name
Test status
Simulation time 422466499 ps
CPU time 7.12 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 220912 kb
Host smart-5fd8739d-4708-4042-98cd-0cbf7540f9be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844459245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3844459245
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3241420245
Short name T75
Test name
Test status
Simulation time 478488101 ps
CPU time 8.68 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:29 PM PDT 24
Peak memory 217068 kb
Host smart-3b3188fc-c38c-416e-9d64-26de1a3d0e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241420245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3241420245
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1438719835
Short name T387
Test name
Test status
Simulation time 1862521541 ps
CPU time 10.46 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 216728 kb
Host smart-30c89a02-18fc-4328-9a42-31b30ba919ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438719835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1438719835
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1146855602
Short name T785
Test name
Test status
Simulation time 55841685 ps
CPU time 3.57 seconds
Started Jun 26 07:03:15 PM PDT 24
Finished Jun 26 07:03:20 PM PDT 24
Peak memory 216864 kb
Host smart-80ab8169-bf30-425b-988d-bc19cdc25fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146855602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1146855602
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3056020928
Short name T619
Test name
Test status
Simulation time 12038829 ps
CPU time 0.69 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:21 PM PDT 24
Peak memory 206032 kb
Host smart-7617f2bf-7377-47f6-ac19-0906f361a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056020928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3056020928
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3733685769
Short name T721
Test name
Test status
Simulation time 16813081138 ps
CPU time 11.88 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:30 PM PDT 24
Peak memory 230840 kb
Host smart-35399f66-66d8-4d7f-bd41-9533c15f84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733685769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3733685769
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.529278864
Short name T55
Test name
Test status
Simulation time 22571445 ps
CPU time 0.76 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 205892 kb
Host smart-bcad26fe-bcff-4e0c-9ddd-aacce6e745b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529278864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.529278864
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3244289835
Short name T496
Test name
Test status
Simulation time 96419662 ps
CPU time 2.78 seconds
Started Jun 26 07:03:20 PM PDT 24
Finished Jun 26 07:03:25 PM PDT 24
Peak memory 233144 kb
Host smart-915411db-1b5e-469f-8fff-277d3a5585bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244289835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3244289835
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3888858763
Short name T126
Test name
Test status
Simulation time 37770690 ps
CPU time 0.77 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:21 PM PDT 24
Peak memory 206804 kb
Host smart-679e5dc2-e5b7-400b-ad5d-c25a42229ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888858763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3888858763
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.794297511
Short name T907
Test name
Test status
Simulation time 21270821257 ps
CPU time 156.85 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:05:57 PM PDT 24
Peak memory 251288 kb
Host smart-2571966c-eb91-4e3c-a52c-97a20698058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794297511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.794297511
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3469102706
Short name T188
Test name
Test status
Simulation time 48192463221 ps
CPU time 158.2 seconds
Started Jun 26 07:03:28 PM PDT 24
Finished Jun 26 07:06:09 PM PDT 24
Peak memory 250752 kb
Host smart-72d2fd8c-8316-4fca-87f8-6b2f5af6decb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469102706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3469102706
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1460278105
Short name T360
Test name
Test status
Simulation time 17449026507 ps
CPU time 22.9 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 233240 kb
Host smart-c4388f36-813d-45ef-9476-7279b560f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460278105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1460278105
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1476023291
Short name T762
Test name
Test status
Simulation time 38930970 ps
CPU time 2.8 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:22 PM PDT 24
Peak memory 233244 kb
Host smart-b7e45239-de20-4a84-809b-31510e6093f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476023291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1476023291
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1102490550
Short name T348
Test name
Test status
Simulation time 462782105 ps
CPU time 5.09 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:24 PM PDT 24
Peak memory 233404 kb
Host smart-6da3002d-106b-4553-8865-c184bb0504c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102490550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1102490550
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3663472098
Short name T567
Test name
Test status
Simulation time 448460127 ps
CPU time 7.87 seconds
Started Jun 26 07:03:20 PM PDT 24
Finished Jun 26 07:03:30 PM PDT 24
Peak memory 224892 kb
Host smart-33235f02-285e-4135-bce1-84d2d4231b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663472098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3663472098
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2867668030
Short name T190
Test name
Test status
Simulation time 1321863571 ps
CPU time 7.35 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 241420 kb
Host smart-0b3e0b49-d428-4e12-b74c-06311a024355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867668030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2867668030
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4033417021
Short name T957
Test name
Test status
Simulation time 6985668349 ps
CPU time 6.2 seconds
Started Jun 26 07:03:16 PM PDT 24
Finished Jun 26 07:03:24 PM PDT 24
Peak memory 225036 kb
Host smart-d09b6387-fdb6-4e2d-9c10-46da7fe2402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033417021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4033417021
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.288202554
Short name T653
Test name
Test status
Simulation time 2719084433 ps
CPU time 11.31 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:31 PM PDT 24
Peak memory 222408 kb
Host smart-4ff02704-fb32-40c3-b909-c074434e995e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288202554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.288202554
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1854745484
Short name T19
Test name
Test status
Simulation time 9627400805 ps
CPU time 30.31 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:04:04 PM PDT 24
Peak memory 222440 kb
Host smart-97fb8a1c-fd68-4d2f-be8b-94a4fb42b7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854745484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1854745484
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.140999542
Short name T774
Test name
Test status
Simulation time 11730621493 ps
CPU time 24.92 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 216816 kb
Host smart-75dd762b-a4dd-4918-9a85-ce1b6495a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140999542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.140999542
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1688598817
Short name T557
Test name
Test status
Simulation time 3046638973 ps
CPU time 8.89 seconds
Started Jun 26 07:03:19 PM PDT 24
Finished Jun 26 07:03:30 PM PDT 24
Peak memory 216824 kb
Host smart-999f747a-5482-4a7b-9989-696341abbb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688598817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1688598817
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3686822063
Short name T647
Test name
Test status
Simulation time 491587557 ps
CPU time 3.97 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:25 PM PDT 24
Peak memory 216904 kb
Host smart-710be630-6209-4e39-a4e3-25fa850d2429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686822063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3686822063
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3398593241
Short name T802
Test name
Test status
Simulation time 138218636 ps
CPU time 0.82 seconds
Started Jun 26 07:03:18 PM PDT 24
Finished Jun 26 07:03:21 PM PDT 24
Peak memory 206184 kb
Host smart-80a403f0-7524-44b7-898f-d6e204a4eb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398593241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3398593241
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3424997916
Short name T482
Test name
Test status
Simulation time 1047156815 ps
CPU time 5.38 seconds
Started Jun 26 07:03:17 PM PDT 24
Finished Jun 26 07:03:25 PM PDT 24
Peak memory 224956 kb
Host smart-8ea0ff12-f221-4619-abc5-9ccbcb80bdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424997916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3424997916
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3043548727
Short name T418
Test name
Test status
Simulation time 19781485 ps
CPU time 0.74 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:33 PM PDT 24
Peak memory 206296 kb
Host smart-dd85bdaf-c73f-4c29-b33d-8f7fe4d2923f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043548727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3043548727
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.654271823
Short name T830
Test name
Test status
Simulation time 335695075 ps
CPU time 3.3 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:37 PM PDT 24
Peak memory 224988 kb
Host smart-389ab032-fa8b-4ac2-9d0a-3738ac721d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654271823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.654271823
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1674129045
Short name T316
Test name
Test status
Simulation time 27918263 ps
CPU time 0.82 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 207088 kb
Host smart-9fcd7b5a-8cf6-4d13-9647-21d468f5bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674129045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1674129045
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1343195409
Short name T38
Test name
Test status
Simulation time 50228612873 ps
CPU time 107.65 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:05:22 PM PDT 24
Peak memory 254276 kb
Host smart-3bacf7b4-282b-4e21-85a7-0272d60d44e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343195409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1343195409
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.40418030
Short name T508
Test name
Test status
Simulation time 11706808445 ps
CPU time 80.42 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:04:52 PM PDT 24
Peak memory 257884 kb
Host smart-1769e069-eb34-45a5-8381-657d58d55958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40418030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.40418030
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2365539734
Short name T180
Test name
Test status
Simulation time 3373271563 ps
CPU time 44.5 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:04:20 PM PDT 24
Peak memory 257144 kb
Host smart-46c198f1-e084-4ba5-a252-64efc0c0953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365539734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2365539734
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.639177299
Short name T911
Test name
Test status
Simulation time 9352908759 ps
CPU time 68.61 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:04:42 PM PDT 24
Peak memory 249668 kb
Host smart-aee3836c-cbb0-44af-91d3-7a1702ef4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639177299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.639177299
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3129698897
Short name T181
Test name
Test status
Simulation time 3451988920 ps
CPU time 23.53 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 241024 kb
Host smart-a2e7fb86-440c-474a-8ff2-1bb456aff503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129698897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3129698897
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4205007445
Short name T251
Test name
Test status
Simulation time 28470915142 ps
CPU time 15.9 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:48 PM PDT 24
Peak memory 225020 kb
Host smart-5cf844e5-29d5-47da-89d0-73357ec1d599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205007445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4205007445
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2928067197
Short name T554
Test name
Test status
Simulation time 246587060 ps
CPU time 2.31 seconds
Started Jun 26 07:03:35 PM PDT 24
Finished Jun 26 07:03:39 PM PDT 24
Peak memory 225008 kb
Host smart-f9330d46-c58d-4143-a3d1-6260beaf5810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928067197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2928067197
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.161367596
Short name T343
Test name
Test status
Simulation time 5505090591 ps
CPU time 16.02 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 222780 kb
Host smart-7d686bf1-4c83-4c55-9e7c-0373410342bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161367596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.161367596
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.565063435
Short name T71
Test name
Test status
Simulation time 28269145030 ps
CPU time 201.88 seconds
Started Jun 26 07:03:34 PM PDT 24
Finished Jun 26 07:06:58 PM PDT 24
Peak memory 274260 kb
Host smart-3967495f-2306-4d04-90c3-512ee378d104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565063435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.565063435
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.664575417
Short name T288
Test name
Test status
Simulation time 1167668047 ps
CPU time 18.27 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 217008 kb
Host smart-3e64a82f-75fd-4dd2-abbe-e7e3a8c4f17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664575417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.664575417
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3635781653
Short name T873
Test name
Test status
Simulation time 342458430 ps
CPU time 1.76 seconds
Started Jun 26 07:03:28 PM PDT 24
Finished Jun 26 07:03:32 PM PDT 24
Peak memory 208352 kb
Host smart-bb2b9cd9-57a0-4db1-b334-6a22f2a6bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635781653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3635781653
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3904058481
Short name T290
Test name
Test status
Simulation time 853416316 ps
CPU time 1.96 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:35 PM PDT 24
Peak memory 216824 kb
Host smart-45548392-caba-47b7-9f07-fa28c8c5feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904058481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3904058481
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1165114808
Short name T546
Test name
Test status
Simulation time 66441644 ps
CPU time 0.92 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:33 PM PDT 24
Peak memory 207408 kb
Host smart-731eb06f-cef8-4556-a0a7-8c89064d5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165114808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1165114808
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3901573447
Short name T532
Test name
Test status
Simulation time 2738935809 ps
CPU time 10.62 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 233252 kb
Host smart-19d8e13b-6cd4-4bf5-a04c-cc7268180bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901573447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3901573447
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3397808827
Short name T664
Test name
Test status
Simulation time 29042459 ps
CPU time 0.76 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:00:34 PM PDT 24
Peak memory 205880 kb
Host smart-96d7ada6-bb19-4f94-9d7e-d9698a9c4bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397808827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
397808827
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3354657534
Short name T929
Test name
Test status
Simulation time 487017888 ps
CPU time 5.4 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:00:38 PM PDT 24
Peak memory 233108 kb
Host smart-dc4ab41c-d80f-444f-ae06-acdd3ae92014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354657534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3354657534
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3741442746
Short name T885
Test name
Test status
Simulation time 22503662 ps
CPU time 0.78 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:23 PM PDT 24
Peak memory 205964 kb
Host smart-aa571e96-9952-42ba-a1aa-17cf710b3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741442746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3741442746
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2171637109
Short name T607
Test name
Test status
Simulation time 7453942817 ps
CPU time 103.02 seconds
Started Jun 26 07:00:19 PM PDT 24
Finished Jun 26 07:02:04 PM PDT 24
Peak memory 266108 kb
Host smart-348c9cf6-0a0b-446a-b2cb-88bded549604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171637109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2171637109
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1432746952
Short name T919
Test name
Test status
Simulation time 64550886726 ps
CPU time 308.5 seconds
Started Jun 26 07:00:31 PM PDT 24
Finished Jun 26 07:05:41 PM PDT 24
Peak memory 253640 kb
Host smart-f69b5107-b4a6-4679-9a2d-082e9fd1ce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432746952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1432746952
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3267682968
Short name T780
Test name
Test status
Simulation time 31981595226 ps
CPU time 39.26 seconds
Started Jun 26 07:00:27 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 217956 kb
Host smart-40727bcd-f0c2-4c06-b9de-183e729c45a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267682968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3267682968
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1305434373
Short name T125
Test name
Test status
Simulation time 1949853064 ps
CPU time 11.32 seconds
Started Jun 26 07:00:27 PM PDT 24
Finished Jun 26 07:00:40 PM PDT 24
Peak memory 224944 kb
Host smart-b1bb8f8c-38ab-43bf-9a3c-d5f6d4b88780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305434373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1305434373
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4101518389
Short name T469
Test name
Test status
Simulation time 3366022757 ps
CPU time 3.66 seconds
Started Jun 26 07:00:29 PM PDT 24
Finished Jun 26 07:00:35 PM PDT 24
Peak memory 225020 kb
Host smart-2166de47-569d-45a1-8550-98333c9e99b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101518389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4101518389
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2698448634
Short name T443
Test name
Test status
Simulation time 1070400551 ps
CPU time 6.28 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:31 PM PDT 24
Peak memory 233224 kb
Host smart-5f247c43-c61d-4f95-8e5f-73454093a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698448634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2698448634
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.87171292
Short name T956
Test name
Test status
Simulation time 27050149 ps
CPU time 1.05 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 218360 kb
Host smart-fd9ab31e-68cb-4836-98d4-971226b7e3e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87171292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.87171292
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1351746296
Short name T430
Test name
Test status
Simulation time 10918633650 ps
CPU time 9.93 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:33 PM PDT 24
Peak memory 233220 kb
Host smart-15410052-99c8-43fc-b790-dbed4021dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351746296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1351746296
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1510804978
Short name T928
Test name
Test status
Simulation time 11903818214 ps
CPU time 16.73 seconds
Started Jun 26 07:00:19 PM PDT 24
Finished Jun 26 07:00:37 PM PDT 24
Peak memory 233332 kb
Host smart-cd83b3d7-ffd1-4252-9365-dcee9b7c50ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510804978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1510804978
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2833095134
Short name T933
Test name
Test status
Simulation time 632026568 ps
CPU time 5.31 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:30 PM PDT 24
Peak memory 223316 kb
Host smart-698f85af-e3ef-482f-98d8-e2b72341d19e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2833095134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2833095134
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1917904964
Short name T59
Test name
Test status
Simulation time 226411074 ps
CPU time 1.07 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:26 PM PDT 24
Peak memory 235904 kb
Host smart-57c93ab0-c81b-4316-912c-799d1a8e1101
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917904964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1917904964
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4143188337
Short name T269
Test name
Test status
Simulation time 33542554952 ps
CPU time 243.33 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:04:28 PM PDT 24
Peak memory 252596 kb
Host smart-7a447c70-60d7-4b6b-80ae-050abf439132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143188337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4143188337
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1162613779
Short name T662
Test name
Test status
Simulation time 2376136741 ps
CPU time 20.6 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 216904 kb
Host smart-97972914-28d7-48a1-980c-78617a8b65db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162613779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1162613779
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.265040014
Short name T385
Test name
Test status
Simulation time 10606683764 ps
CPU time 6.64 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:33 PM PDT 24
Peak memory 216800 kb
Host smart-d62e59d0-6881-4935-9b67-7b8ff7746c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265040014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.265040014
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2264004533
Short name T332
Test name
Test status
Simulation time 60388244 ps
CPU time 0.88 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 207112 kb
Host smart-c6842302-5ad3-4aec-89e3-0bc1ac77f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264004533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2264004533
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3919926828
Short name T741
Test name
Test status
Simulation time 42277919 ps
CPU time 0.78 seconds
Started Jun 26 07:00:27 PM PDT 24
Finished Jun 26 07:00:30 PM PDT 24
Peak memory 206352 kb
Host smart-f6d60965-44b4-4066-9a0b-7e517f04b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919926828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3919926828
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1744172810
Short name T920
Test name
Test status
Simulation time 1591512638 ps
CPU time 6.89 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:32 PM PDT 24
Peak memory 224956 kb
Host smart-1f6f579b-d080-470a-855c-cf9105b12bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744172810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1744172810
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1251951237
Short name T709
Test name
Test status
Simulation time 38638517 ps
CPU time 0.73 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:36 PM PDT 24
Peak memory 205200 kb
Host smart-8ca35dd3-0012-4a5a-86b1-e9d7d1d71116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251951237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1251951237
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1299278236
Short name T244
Test name
Test status
Simulation time 1212723552 ps
CPU time 6.86 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:41 PM PDT 24
Peak memory 224612 kb
Host smart-4ee6ecbd-fe4c-4eab-8eca-5799f25ac4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299278236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1299278236
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1483018572
Short name T742
Test name
Test status
Simulation time 14976698 ps
CPU time 0.77 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:36 PM PDT 24
Peak memory 207248 kb
Host smart-b9b2c962-d200-426d-974c-2bc2994f0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483018572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1483018572
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3697890229
Short name T383
Test name
Test status
Simulation time 3472723165 ps
CPU time 63.05 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:04:36 PM PDT 24
Peak memory 249692 kb
Host smart-8a2dd2ce-e830-42e1-aa90-8f506ca92c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697890229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3697890229
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.900215244
Short name T400
Test name
Test status
Simulation time 18111516364 ps
CPU time 43.7 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:04:17 PM PDT 24
Peak memory 241236 kb
Host smart-8f717a11-9960-4073-b323-aa6ee3a820a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900215244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.900215244
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2705038311
Short name T42
Test name
Test status
Simulation time 25506972991 ps
CPU time 102.49 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:05:15 PM PDT 24
Peak memory 249720 kb
Host smart-4fab4b81-81eb-4467-9cdb-9a6ae42e6444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705038311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2705038311
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2381924190
Short name T425
Test name
Test status
Simulation time 285820109 ps
CPU time 2.53 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:37 PM PDT 24
Peak memory 224972 kb
Host smart-3d2fe6a1-4219-4ca5-8887-6b619c41c524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381924190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2381924190
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2882983381
Short name T477
Test name
Test status
Simulation time 1853721660 ps
CPU time 13.37 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 224952 kb
Host smart-7db081ba-d5b1-483e-b5e6-1bc1b6400c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882983381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2882983381
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2049689070
Short name T211
Test name
Test status
Simulation time 358105136 ps
CPU time 11.36 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 249460 kb
Host smart-7babd45a-d90c-46d8-96d2-5285d952d8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049689070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2049689070
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.66963871
Short name T208
Test name
Test status
Simulation time 20649947384 ps
CPU time 27.96 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:04:01 PM PDT 24
Peak memory 240952 kb
Host smart-77ae28b7-d90f-4627-98a9-e87d917fd473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66963871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.66963871
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.952737258
Short name T719
Test name
Test status
Simulation time 701194614 ps
CPU time 3.68 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:37 PM PDT 24
Peak memory 233160 kb
Host smart-980875a7-2b49-467a-8a9e-79586d1940ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952737258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.952737258
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2629260638
Short name T458
Test name
Test status
Simulation time 11099156442 ps
CPU time 8.27 seconds
Started Jun 26 07:03:34 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 223240 kb
Host smart-44fd3430-e115-4c82-a7eb-1884e542290e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2629260638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2629260638
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1197645881
Short name T155
Test name
Test status
Simulation time 6158112127 ps
CPU time 128.43 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:05:40 PM PDT 24
Peak memory 274084 kb
Host smart-d4e3a357-d3b6-41d7-8b9b-01e7c1b1a9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197645881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1197645881
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2752965753
Short name T287
Test name
Test status
Simulation time 1210433765 ps
CPU time 17.56 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:52 PM PDT 24
Peak memory 216808 kb
Host smart-4634260d-7829-4594-98fe-626babf953d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752965753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2752965753
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.366735317
Short name T509
Test name
Test status
Simulation time 976815953 ps
CPU time 6.88 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:40 PM PDT 24
Peak memory 216728 kb
Host smart-d027300b-2aef-438e-9e71-5b4b075aec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366735317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.366735317
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3138615869
Short name T322
Test name
Test status
Simulation time 125540690 ps
CPU time 4.2 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:39 PM PDT 24
Peak memory 216396 kb
Host smart-ab8de41f-9355-4559-bbc0-cd79f258cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138615869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3138615869
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.110548849
Short name T656
Test name
Test status
Simulation time 91185783 ps
CPU time 0.95 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:36 PM PDT 24
Peak memory 206320 kb
Host smart-a04225b2-a8e5-4176-b176-6f0411cdf444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110548849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.110548849
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.504730393
Short name T889
Test name
Test status
Simulation time 9161584719 ps
CPU time 16.13 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:49 PM PDT 24
Peak memory 232968 kb
Host smart-cb53a97d-cd7e-4aab-a32d-9d8c51a15c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504730393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.504730393
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3039552722
Short name T821
Test name
Test status
Simulation time 13958781 ps
CPU time 0.75 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 205788 kb
Host smart-7048f20e-19ab-4178-af7a-c881f13b4981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039552722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3039552722
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.969847186
Short name T491
Test name
Test status
Simulation time 255136080 ps
CPU time 2.76 seconds
Started Jun 26 07:03:34 PM PDT 24
Finished Jun 26 07:03:39 PM PDT 24
Peak memory 224924 kb
Host smart-652d738e-9558-45ca-b928-dc856f2fdd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969847186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.969847186
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1117838496
Short name T868
Test name
Test status
Simulation time 12328230 ps
CPU time 0.76 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 205964 kb
Host smart-3244c330-427d-4935-b509-6a6daaf28da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117838496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1117838496
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4165883919
Short name T807
Test name
Test status
Simulation time 12885880 ps
CPU time 0.76 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:35 PM PDT 24
Peak memory 216324 kb
Host smart-408dcf2c-f454-4932-b3a8-bfc09f29066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165883919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4165883919
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2213737285
Short name T270
Test name
Test status
Simulation time 36090319452 ps
CPU time 401.63 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:10:28 PM PDT 24
Peak memory 264156 kb
Host smart-2c32122b-2239-4618-921f-7ffd2b5e3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213737285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2213737285
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2445226631
Short name T456
Test name
Test status
Simulation time 1115560843 ps
CPU time 17.65 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 241388 kb
Host smart-73838c0f-5ff9-4508-82cf-e5d566c53d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445226631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2445226631
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1069374300
Short name T404
Test name
Test status
Simulation time 645087268 ps
CPU time 6.79 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:40 PM PDT 24
Peak memory 233228 kb
Host smart-b2e8576e-97b7-4fd2-b391-ab2a200455a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069374300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1069374300
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2211037631
Short name T375
Test name
Test status
Simulation time 345911055 ps
CPU time 6.02 seconds
Started Jun 26 07:03:34 PM PDT 24
Finished Jun 26 07:03:43 PM PDT 24
Peak memory 233176 kb
Host smart-dc8c76e6-0ad3-4d0a-80a0-6e0c706f0870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211037631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2211037631
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.812811766
Short name T922
Test name
Test status
Simulation time 8458660153 ps
CPU time 23.35 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:59 PM PDT 24
Peak memory 241212 kb
Host smart-675cbd3d-ed14-4491-b039-657c0e9ba0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812811766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.812811766
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3745205030
Short name T767
Test name
Test status
Simulation time 1108912805 ps
CPU time 7.07 seconds
Started Jun 26 07:03:30 PM PDT 24
Finished Jun 26 07:03:40 PM PDT 24
Peak memory 233188 kb
Host smart-5b501564-e527-4c2d-98f7-4536c389010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745205030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3745205030
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3680913302
Short name T396
Test name
Test status
Simulation time 6637389209 ps
CPU time 11.55 seconds
Started Jun 26 07:03:33 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 221156 kb
Host smart-899fb286-d7b0-4c01-8431-919511f7e1ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3680913302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3680913302
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.366550702
Short name T25
Test name
Test status
Simulation time 2332110462 ps
CPU time 9.07 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:43 PM PDT 24
Peak memory 217112 kb
Host smart-67b3169f-1b2f-4532-9465-bc4fed18065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366550702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.366550702
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1131961326
Short name T883
Test name
Test status
Simulation time 9821182347 ps
CPU time 12.46 seconds
Started Jun 26 07:03:32 PM PDT 24
Finished Jun 26 07:03:48 PM PDT 24
Peak memory 216696 kb
Host smart-5c1b50c5-adea-48d9-b053-156bb44313be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131961326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1131961326
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4048345405
Short name T514
Test name
Test status
Simulation time 202622197 ps
CPU time 1.89 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:36 PM PDT 24
Peak memory 216716 kb
Host smart-8ccada02-7cd5-41bf-b17c-46426e829db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048345405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4048345405
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.202811240
Short name T489
Test name
Test status
Simulation time 19922897 ps
CPU time 0.75 seconds
Started Jun 26 07:03:29 PM PDT 24
Finished Jun 26 07:03:34 PM PDT 24
Peak memory 206176 kb
Host smart-d50573c1-19fc-47b3-a9a6-1af84e699a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202811240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.202811240
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1477216668
Short name T105
Test name
Test status
Simulation time 3482958691 ps
CPU time 6.91 seconds
Started Jun 26 07:03:31 PM PDT 24
Finished Jun 26 07:03:41 PM PDT 24
Peak memory 233180 kb
Host smart-f945b103-beab-49eb-959d-0622408d697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477216668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1477216668
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1253977750
Short name T755
Test name
Test status
Simulation time 20307806 ps
CPU time 0.72 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 205384 kb
Host smart-9a1596af-734c-435b-923f-e894ed307904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253977750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1253977750
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.980394104
Short name T939
Test name
Test status
Simulation time 2131546561 ps
CPU time 6.38 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 233188 kb
Host smart-b00f7d7e-fa9e-4593-92dc-6c6d4ca46b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980394104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.980394104
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2615274507
Short name T953
Test name
Test status
Simulation time 17650190 ps
CPU time 0.76 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 206268 kb
Host smart-e558f112-4326-427b-ad5d-344c76f98938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615274507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2615274507
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2812519341
Short name T860
Test name
Test status
Simulation time 2470876466 ps
CPU time 57.53 seconds
Started Jun 26 07:03:41 PM PDT 24
Finished Jun 26 07:04:39 PM PDT 24
Peak memory 265448 kb
Host smart-02fb6692-db48-4037-9690-ec5946eef32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812519341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2812519341
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2032269283
Short name T692
Test name
Test status
Simulation time 3540434964 ps
CPU time 79.68 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:05:03 PM PDT 24
Peak memory 249612 kb
Host smart-0c4470ec-ee09-41ef-9b26-fa60a3043cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032269283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2032269283
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2343123138
Short name T177
Test name
Test status
Simulation time 224014500348 ps
CPU time 591.82 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:13:40 PM PDT 24
Peak memory 255608 kb
Host smart-7669de78-61f7-437e-b202-27c25c528c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343123138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2343123138
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1058943257
Short name T283
Test name
Test status
Simulation time 344265277 ps
CPU time 11.86 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:55 PM PDT 24
Peak memory 234732 kb
Host smart-2ff7abf2-1059-40be-bc66-caa184cb0230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058943257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1058943257
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3137898176
Short name T727
Test name
Test status
Simulation time 1262840349 ps
CPU time 5.95 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:49 PM PDT 24
Peak memory 224972 kb
Host smart-ee1ce273-974f-41e2-be48-39e5e98bd575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137898176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3137898176
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2365611941
Short name T221
Test name
Test status
Simulation time 9375208564 ps
CPU time 89.2 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:05:14 PM PDT 24
Peak memory 234004 kb
Host smart-7a4c4183-18b1-4d5c-933f-fbc1d9d8bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365611941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2365611941
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2848678766
Short name T599
Test name
Test status
Simulation time 230665432 ps
CPU time 4.05 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 224884 kb
Host smart-12fa97ef-2963-45d6-aa6c-cb8902375347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848678766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2848678766
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1337577028
Short name T574
Test name
Test status
Simulation time 8076152110 ps
CPU time 11.44 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 233228 kb
Host smart-4f98f25f-9e89-4ac9-846d-42cd79ea8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337577028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1337577028
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.97522798
Short name T344
Test name
Test status
Simulation time 8956438571 ps
CPU time 11.48 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 223636 kb
Host smart-6bc4c6d2-b749-4b77-95ac-6eeed5c4ee1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=97522798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.97522798
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3898856206
Short name T850
Test name
Test status
Simulation time 32915618646 ps
CPU time 323.91 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:09:07 PM PDT 24
Peak memory 266108 kb
Host smart-6b260560-d863-4718-be3f-2b39236ac410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898856206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3898856206
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4131011525
Short name T712
Test name
Test status
Simulation time 61520182858 ps
CPU time 31.77 seconds
Started Jun 26 07:03:45 PM PDT 24
Finished Jun 26 07:04:19 PM PDT 24
Peak memory 216808 kb
Host smart-7a5c6dd3-248f-4c5b-9fea-6d92eaca396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131011525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4131011525
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2713066935
Short name T336
Test name
Test status
Simulation time 37470132 ps
CPU time 0.72 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 206108 kb
Host smart-784f1099-c4ab-4624-9898-351374022ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713066935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2713066935
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.235816283
Short name T12
Test name
Test status
Simulation time 15172106 ps
CPU time 0.94 seconds
Started Jun 26 07:03:40 PM PDT 24
Finished Jun 26 07:03:41 PM PDT 24
Peak memory 207484 kb
Host smart-dcc76e5c-d366-4b7c-8a4f-45c3411215cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235816283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.235816283
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.301571574
Short name T311
Test name
Test status
Simulation time 72805539 ps
CPU time 0.97 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:45 PM PDT 24
Peak memory 206356 kb
Host smart-2b890eaf-8e4d-43a7-ad6f-e254d6aa051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301571574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.301571574
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2717554414
Short name T222
Test name
Test status
Simulation time 116175496 ps
CPU time 3.37 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 233144 kb
Host smart-67aa1142-ec5c-4916-af71-508a2f409364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717554414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2717554414
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1088681593
Short name T384
Test name
Test status
Simulation time 33471622 ps
CPU time 0.79 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:03:48 PM PDT 24
Peak memory 206440 kb
Host smart-9cefdd8b-543b-4c4e-9a2a-71c4026edd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088681593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1088681593
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2819777263
Short name T352
Test name
Test status
Simulation time 291937007 ps
CPU time 4.06 seconds
Started Jun 26 07:03:45 PM PDT 24
Finished Jun 26 07:03:52 PM PDT 24
Peak memory 233200 kb
Host smart-b640b286-b5e6-4da2-8a30-94d7801fc88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819777263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2819777263
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1466653874
Short name T455
Test name
Test status
Simulation time 18604861 ps
CPU time 0.81 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:44 PM PDT 24
Peak memory 207080 kb
Host smart-2a8c8ca4-ddc0-4246-b175-ab6f56efa876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466653874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1466653874
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2357180367
Short name T263
Test name
Test status
Simulation time 150301390626 ps
CPU time 329.26 seconds
Started Jun 26 07:03:45 PM PDT 24
Finished Jun 26 07:09:17 PM PDT 24
Peak memory 254968 kb
Host smart-41d04ef6-c5db-4500-88ca-cd22925c8aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357180367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2357180367
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3292071679
Short name T69
Test name
Test status
Simulation time 2886337916 ps
CPU time 86.62 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:05:13 PM PDT 24
Peak memory 251960 kb
Host smart-f71f3f07-f067-42ce-9d7a-db663126d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292071679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3292071679
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2840459438
Short name T537
Test name
Test status
Simulation time 2525926822 ps
CPU time 12.15 seconds
Started Jun 26 07:03:41 PM PDT 24
Finished Jun 26 07:03:54 PM PDT 24
Peak memory 217796 kb
Host smart-879494e8-3db9-4027-ab0e-0e470209f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840459438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2840459438
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3747840859
Short name T364
Test name
Test status
Simulation time 376240015 ps
CPU time 4.11 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:49 PM PDT 24
Peak memory 233216 kb
Host smart-52bd5d6f-da88-4dfe-8eb1-471d94c61c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747840859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3747840859
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1990719576
Short name T238
Test name
Test status
Simulation time 2667414591 ps
CPU time 27.46 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:04:14 PM PDT 24
Peak memory 225012 kb
Host smart-462914e3-e55e-4ae5-a6d9-668134f4b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990719576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1990719576
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1997520350
Short name T947
Test name
Test status
Simulation time 105682521 ps
CPU time 2.54 seconds
Started Jun 26 07:03:45 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 232960 kb
Host smart-a6448f61-c099-4aa5-83b6-f47a06c8a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997520350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1997520350
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2996962807
Short name T840
Test name
Test status
Simulation time 271403429 ps
CPU time 2.66 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:48 PM PDT 24
Peak memory 225016 kb
Host smart-4aa0b463-9e6d-4009-8c11-32ebf75ece43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996962807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2996962807
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3088918773
Short name T648
Test name
Test status
Simulation time 11051365889 ps
CPU time 11.04 seconds
Started Jun 26 07:03:42 PM PDT 24
Finished Jun 26 07:03:55 PM PDT 24
Peak memory 233232 kb
Host smart-a8784e39-2aca-4423-9f60-c66a7e95d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088918773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3088918773
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.713237513
Short name T350
Test name
Test status
Simulation time 4065094786 ps
CPU time 9.53 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:55 PM PDT 24
Peak memory 221008 kb
Host smart-962bc15c-a4f7-4e09-9452-fcd1fb44b7c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=713237513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.713237513
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.41055962
Short name T797
Test name
Test status
Simulation time 90050249340 ps
CPU time 244.97 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:07:54 PM PDT 24
Peak memory 265864 kb
Host smart-f6924540-6302-4042-98ea-ed96b2dc588d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41055962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress
_all.41055962
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4119287267
Short name T925
Test name
Test status
Simulation time 9136705698 ps
CPU time 27.64 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 216856 kb
Host smart-3baa08d6-defc-4802-8698-f5a7cc0fa099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119287267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4119287267
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1296238526
Short name T44
Test name
Test status
Simulation time 1569703407 ps
CPU time 4.16 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 216744 kb
Host smart-9ee9ca26-7552-4287-898e-ce7e14b72396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296238526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1296238526
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1316580351
Short name T951
Test name
Test status
Simulation time 75460303 ps
CPU time 0.95 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 207484 kb
Host smart-d3d8feab-c6f1-42db-9d4b-f0205162c16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316580351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1316580351
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4142150700
Short name T806
Test name
Test status
Simulation time 88322764 ps
CPU time 0.83 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:46 PM PDT 24
Peak memory 206328 kb
Host smart-9c9ecb48-912e-493c-b0fa-1acd833401d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142150700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4142150700
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1786108483
Short name T803
Test name
Test status
Simulation time 2603904698 ps
CPU time 3.81 seconds
Started Jun 26 07:03:41 PM PDT 24
Finished Jun 26 07:03:46 PM PDT 24
Peak memory 224964 kb
Host smart-1a91bace-282b-46ec-bdf2-00e123133023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786108483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1786108483
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2523968343
Short name T952
Test name
Test status
Simulation time 94390987 ps
CPU time 0.71 seconds
Started Jun 26 07:03:48 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 206284 kb
Host smart-8488ddb6-1fe7-4c8f-99bb-33179d97e1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523968343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2523968343
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1968332458
Short name T773
Test name
Test status
Simulation time 794913437 ps
CPU time 9.77 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 233160 kb
Host smart-df3fc6ab-e45e-4125-836c-601998c7a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968332458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1968332458
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1696634921
Short name T673
Test name
Test status
Simulation time 43164379 ps
CPU time 0.75 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 205976 kb
Host smart-abdc8091-950f-4fcf-8edd-2e8b9bcaa061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696634921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1696634921
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3766195905
Short name T264
Test name
Test status
Simulation time 35956005645 ps
CPU time 250.58 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:07:57 PM PDT 24
Peak memory 250440 kb
Host smart-a7233655-9dc5-4a1e-9cf8-c61c961646a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766195905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3766195905
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2142713665
Short name T46
Test name
Test status
Simulation time 21882600004 ps
CPU time 111.05 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:05:40 PM PDT 24
Peak memory 257912 kb
Host smart-e9b93caf-5e48-4dc3-aa2c-48473c1a446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142713665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2142713665
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4046241551
Short name T515
Test name
Test status
Simulation time 504484483 ps
CPU time 3.03 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:52 PM PDT 24
Peak memory 224996 kb
Host smart-4c4bb7ce-268f-405e-923b-ac94a5614943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046241551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4046241551
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.720693456
Short name T682
Test name
Test status
Simulation time 15057104095 ps
CPU time 17.4 seconds
Started Jun 26 07:03:51 PM PDT 24
Finished Jun 26 07:04:10 PM PDT 24
Peak memory 225048 kb
Host smart-9edd285c-4f6c-48d0-90f8-3f20c5b7c0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720693456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.720693456
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2212937385
Short name T422
Test name
Test status
Simulation time 2818397713 ps
CPU time 13.23 seconds
Started Jun 26 07:03:49 PM PDT 24
Finished Jun 26 07:04:04 PM PDT 24
Peak memory 225028 kb
Host smart-d7a3620b-4108-4bfa-862b-03f18ab0f064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212937385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2212937385
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1327832912
Short name T688
Test name
Test status
Simulation time 114179391 ps
CPU time 2.17 seconds
Started Jun 26 07:03:51 PM PDT 24
Finished Jun 26 07:03:54 PM PDT 24
Peak memory 224924 kb
Host smart-981a9af3-3ef2-4e4f-9bec-b80f7624414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327832912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1327832912
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3180360818
Short name T459
Test name
Test status
Simulation time 1571391977 ps
CPU time 2.78 seconds
Started Jun 26 07:03:51 PM PDT 24
Finished Jun 26 07:03:55 PM PDT 24
Peak memory 225036 kb
Host smart-b31f2942-6cc3-4540-b5b8-5f62305c8396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180360818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3180360818
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.304037076
Short name T314
Test name
Test status
Simulation time 614064104 ps
CPU time 8.13 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:58 PM PDT 24
Peak memory 223024 kb
Host smart-4b99e661-4a60-4aeb-a1e2-115e8ba618ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=304037076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.304037076
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4167735238
Short name T17
Test name
Test status
Simulation time 123743668264 ps
CPU time 227.56 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:07:34 PM PDT 24
Peak memory 249680 kb
Host smart-7aab8d2b-bc91-44b5-9944-945c11df00d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167735238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4167735238
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.959644450
Short name T505
Test name
Test status
Simulation time 13357866392 ps
CPU time 25.42 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:04:10 PM PDT 24
Peak memory 216840 kb
Host smart-0d773b77-d14f-4788-9053-8eb975ef11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959644450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.959644450
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2211189802
Short name T461
Test name
Test status
Simulation time 2637264634 ps
CPU time 5.55 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:54 PM PDT 24
Peak memory 216828 kb
Host smart-d902e1b6-c8fb-4b2e-a797-33073b46e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211189802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2211189802
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.154155700
Short name T818
Test name
Test status
Simulation time 44473402 ps
CPU time 2.4 seconds
Started Jun 26 07:03:45 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 216848 kb
Host smart-95e5d6fc-6561-4f65-9adc-0679e94cdd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154155700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.154155700
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1306351419
Short name T358
Test name
Test status
Simulation time 113913311 ps
CPU time 0.88 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:47 PM PDT 24
Peak memory 206568 kb
Host smart-499cad3e-82a5-49e0-867d-42c7b51cd83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306351419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1306351419
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.121154638
Short name T243
Test name
Test status
Simulation time 2562317528 ps
CPU time 6.69 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 233260 kb
Host smart-7e055301-475e-4623-af44-96b24e5d9510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121154638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.121154638
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2279982201
Short name T381
Test name
Test status
Simulation time 22733176 ps
CPU time 0.72 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:01 PM PDT 24
Peak memory 206208 kb
Host smart-211ecab2-c082-488f-aef5-385ea168585f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279982201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2279982201
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3732637135
Short name T303
Test name
Test status
Simulation time 118105029 ps
CPU time 2.45 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 224584 kb
Host smart-1d9c4f8d-c101-4c23-a95f-67b87b7bcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732637135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3732637135
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2382293588
Short name T874
Test name
Test status
Simulation time 22404346 ps
CPU time 0.74 seconds
Started Jun 26 07:03:51 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 205980 kb
Host smart-129c81ca-ce9e-47fb-a960-10cc05621b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382293588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2382293588
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1613126610
Short name T204
Test name
Test status
Simulation time 1586669722 ps
CPU time 39.47 seconds
Started Jun 26 07:03:47 PM PDT 24
Finished Jun 26 07:04:29 PM PDT 24
Peak memory 253816 kb
Host smart-20f5f2a1-93d5-4125-bfca-4a10b83cc6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613126610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1613126610
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4208014980
Short name T157
Test name
Test status
Simulation time 61851765881 ps
CPU time 118.43 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:06:00 PM PDT 24
Peak memory 250716 kb
Host smart-eb86a57c-8762-4dc2-99c2-83a895805a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208014980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4208014980
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.952274439
Short name T639
Test name
Test status
Simulation time 30608592154 ps
CPU time 177.38 seconds
Started Jun 26 07:04:04 PM PDT 24
Finished Jun 26 07:07:02 PM PDT 24
Peak memory 249736 kb
Host smart-59f069df-6846-4fee-95e1-f32e622546f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952274439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.952274439
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1336641871
Short name T137
Test name
Test status
Simulation time 705985817 ps
CPU time 14.01 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:04:00 PM PDT 24
Peak memory 239124 kb
Host smart-e23d5c35-89a5-499a-abc8-4ee9326916bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336641871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1336641871
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.153470539
Short name T361
Test name
Test status
Simulation time 292371321 ps
CPU time 2.62 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 227452 kb
Host smart-e685bfbb-a7fd-4306-b1dc-81cea2a45d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153470539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.153470539
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1996615925
Short name T578
Test name
Test status
Simulation time 379131911 ps
CPU time 5.42 seconds
Started Jun 26 07:03:48 PM PDT 24
Finished Jun 26 07:03:56 PM PDT 24
Peak memory 233256 kb
Host smart-80da82dd-7658-46a5-b5cd-77f0a319d5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996615925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1996615925
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.223153105
Short name T346
Test name
Test status
Simulation time 32950635 ps
CPU time 2.26 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:51 PM PDT 24
Peak memory 232936 kb
Host smart-db01a136-9663-4ba9-adeb-adb014d90cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223153105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.223153105
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2372867679
Short name T233
Test name
Test status
Simulation time 2790806771 ps
CPU time 2.98 seconds
Started Jun 26 07:03:44 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 225028 kb
Host smart-c91c197d-bd2d-4e3b-83e5-4a276b88dc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372867679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2372867679
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.798272478
Short name T103
Test name
Test status
Simulation time 94896375 ps
CPU time 4 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:53 PM PDT 24
Peak memory 223608 kb
Host smart-3e470406-dc45-40fb-a094-7e9a7b36cc44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798272478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.798272478
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.283029705
Short name T41
Test name
Test status
Simulation time 70432351860 ps
CPU time 163.15 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:06:41 PM PDT 24
Peak memory 233284 kb
Host smart-f3ae1ff4-6754-400e-8a77-3e07d685dcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283029705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.283029705
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1287798421
Short name T646
Test name
Test status
Simulation time 1197069457 ps
CPU time 11.14 seconds
Started Jun 26 07:03:48 PM PDT 24
Finished Jun 26 07:04:01 PM PDT 24
Peak memory 218988 kb
Host smart-6ee54b23-6d2a-431b-82e6-b5136a4a0ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287798421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1287798421
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.87819672
Short name T568
Test name
Test status
Simulation time 1040256837 ps
CPU time 5.06 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:50 PM PDT 24
Peak memory 216768 kb
Host smart-a1a1b67d-cbd9-49ce-a4c2-061ae1ddbb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87819672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.87819672
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.510110568
Short name T667
Test name
Test status
Simulation time 2476278465 ps
CPU time 2.74 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:52 PM PDT 24
Peak memory 216804 kb
Host smart-f5177f11-b5e0-444a-9840-7c1644ef8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510110568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.510110568
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.52051006
Short name T340
Test name
Test status
Simulation time 226978449 ps
CPU time 0.87 seconds
Started Jun 26 07:03:43 PM PDT 24
Finished Jun 26 07:03:46 PM PDT 24
Peak memory 206364 kb
Host smart-19e9c476-0ccd-4206-a5cd-3cfa116c4087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52051006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.52051006
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3251139447
Short name T347
Test name
Test status
Simulation time 939269053 ps
CPU time 5.31 seconds
Started Jun 26 07:03:46 PM PDT 24
Finished Jun 26 07:03:54 PM PDT 24
Peak memory 233132 kb
Host smart-7f9db351-7695-4119-94e5-32f18fb070b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251139447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3251139447
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2057452294
Short name T321
Test name
Test status
Simulation time 85552415 ps
CPU time 0.71 seconds
Started Jun 26 07:04:01 PM PDT 24
Finished Jun 26 07:04:03 PM PDT 24
Peak memory 205876 kb
Host smart-855d5268-0940-4c17-b9bd-562dd0d7a2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057452294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2057452294
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.29297458
Short name T421
Test name
Test status
Simulation time 289690715 ps
CPU time 4.09 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:04:06 PM PDT 24
Peak memory 233364 kb
Host smart-62ab0232-0493-4044-b334-26fb3b75be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29297458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.29297458
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.173022816
Short name T68
Test name
Test status
Simulation time 21113187 ps
CPU time 0.78 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:00 PM PDT 24
Peak memory 207332 kb
Host smart-a17144a5-57bc-484f-a8d5-f3cd29b74137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173022816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.173022816
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3829973671
Short name T160
Test name
Test status
Simulation time 3636862898 ps
CPU time 31.62 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:04:33 PM PDT 24
Peak memory 241536 kb
Host smart-791e5b69-c100-4dd4-9b0d-5eeb188c3932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829973671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3829973671
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.568424603
Short name T159
Test name
Test status
Simulation time 96321178029 ps
CPU time 263.89 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:08:36 PM PDT 24
Peak memory 262152 kb
Host smart-e0f77864-7648-4fed-8bb0-19671601814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568424603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.568424603
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2333618361
Short name T871
Test name
Test status
Simulation time 279703837043 ps
CPU time 289.48 seconds
Started Jun 26 07:04:05 PM PDT 24
Finished Jun 26 07:08:56 PM PDT 24
Peak memory 251344 kb
Host smart-3ca52d07-1196-4969-9a4d-6842dac428e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333618361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2333618361
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2379672445
Short name T701
Test name
Test status
Simulation time 286692349 ps
CPU time 3.24 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:04 PM PDT 24
Peak memory 225032 kb
Host smart-8c50a4f1-169c-4960-bb05-290d9c0d7419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379672445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2379672445
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.678042312
Short name T558
Test name
Test status
Simulation time 347246818 ps
CPU time 5.73 seconds
Started Jun 26 07:04:05 PM PDT 24
Finished Jun 26 07:04:12 PM PDT 24
Peak memory 225044 kb
Host smart-1d35ddb4-412b-4675-b830-391c959636f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678042312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.678042312
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3628141795
Short name T432
Test name
Test status
Simulation time 595624443 ps
CPU time 11.36 seconds
Started Jun 26 07:03:55 PM PDT 24
Finished Jun 26 07:04:09 PM PDT 24
Peak memory 249372 kb
Host smart-00553e37-3f7b-48c6-a227-a49fb8917f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628141795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3628141795
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.744483718
Short name T926
Test name
Test status
Simulation time 200356905 ps
CPU time 2.96 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:04 PM PDT 24
Peak memory 233224 kb
Host smart-4966e211-1d7e-4483-a033-f516d5a45c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744483718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.744483718
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.510925989
Short name T417
Test name
Test status
Simulation time 964827934 ps
CPU time 3.16 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:03 PM PDT 24
Peak memory 224932 kb
Host smart-529a8c65-9b47-44f6-a1ea-34112c4c7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510925989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.510925989
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1555437876
Short name T917
Test name
Test status
Simulation time 1656773629 ps
CPU time 8.69 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:09 PM PDT 24
Peak memory 223628 kb
Host smart-1669e6bb-c9ad-45cc-8657-45ca15da5891
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1555437876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1555437876
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2451236224
Short name T178
Test name
Test status
Simulation time 11513367654 ps
CPU time 150.57 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:06:29 PM PDT 24
Peak memory 255872 kb
Host smart-7b4ea86f-f994-4add-a673-ed87244deeb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451236224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2451236224
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2305477344
Short name T409
Test name
Test status
Simulation time 8138057864 ps
CPU time 23.35 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:23 PM PDT 24
Peak memory 216852 kb
Host smart-0bfa1b8c-8620-40a2-b0f3-b641037bd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305477344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2305477344
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3816006777
Short name T913
Test name
Test status
Simulation time 103506107164 ps
CPU time 20.43 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:20 PM PDT 24
Peak memory 216620 kb
Host smart-7c93b7bc-d880-4f60-90c7-8cdd4427707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816006777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3816006777
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1583125382
Short name T641
Test name
Test status
Simulation time 157866424 ps
CPU time 2.04 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:02 PM PDT 24
Peak memory 216736 kb
Host smart-c336dd46-e26c-46a3-92b2-9c144fc51bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583125382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1583125382
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2009799402
Short name T561
Test name
Test status
Simulation time 44735972 ps
CPU time 0.88 seconds
Started Jun 26 07:04:01 PM PDT 24
Finished Jun 26 07:04:03 PM PDT 24
Peak memory 206368 kb
Host smart-ea2673a5-8cdf-4599-86e0-66d2605646f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009799402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2009799402
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3762407782
Short name T586
Test name
Test status
Simulation time 3646742894 ps
CPU time 12.87 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:04:11 PM PDT 24
Peak memory 233260 kb
Host smart-334f4c81-89c4-47ea-aadf-83b9305fccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762407782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3762407782
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3583468954
Short name T463
Test name
Test status
Simulation time 21014427 ps
CPU time 0.77 seconds
Started Jun 26 07:04:05 PM PDT 24
Finished Jun 26 07:04:07 PM PDT 24
Peak memory 206256 kb
Host smart-e1cc7fe8-6c6e-4ffa-a499-c2b610d81282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583468954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3583468954
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3794720976
Short name T230
Test name
Test status
Simulation time 154594735 ps
CPU time 4.14 seconds
Started Jun 26 07:04:01 PM PDT 24
Finished Jun 26 07:04:07 PM PDT 24
Peak memory 225008 kb
Host smart-589ea356-3203-4020-bb9b-071674e54567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794720976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3794720976
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1952420156
Short name T524
Test name
Test status
Simulation time 45026875 ps
CPU time 0.76 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:00 PM PDT 24
Peak memory 205980 kb
Host smart-3bd7fa09-0d0c-4e5b-9fb2-7cacb585df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952420156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1952420156
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2373087959
Short name T274
Test name
Test status
Simulation time 3593918857 ps
CPU time 85 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:05:25 PM PDT 24
Peak memory 267040 kb
Host smart-16bd1d28-3708-42b0-b600-948dbcb772a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373087959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2373087959
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4138981449
Short name T168
Test name
Test status
Simulation time 36159780708 ps
CPU time 81.14 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:05:22 PM PDT 24
Peak memory 251704 kb
Host smart-580803ce-f45e-4258-be9c-676686f0c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138981449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4138981449
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.721270781
Short name T259
Test name
Test status
Simulation time 11267180373 ps
CPU time 70.21 seconds
Started Jun 26 07:04:05 PM PDT 24
Finished Jun 26 07:05:17 PM PDT 24
Peak memory 266112 kb
Host smart-a93471b6-f407-4e1a-9491-058e3c2a4f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721270781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.721270781
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2380202905
Short name T285
Test name
Test status
Simulation time 2300697703 ps
CPU time 11.49 seconds
Started Jun 26 07:04:00 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 225096 kb
Host smart-9c830bdb-280b-4f2f-8bec-6345c7bda225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380202905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2380202905
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4042861090
Short name T394
Test name
Test status
Simulation time 32441346 ps
CPU time 2.52 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:02 PM PDT 24
Peak memory 233012 kb
Host smart-22474fc4-dfdd-461b-963e-de0c618b6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042861090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4042861090
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1141158070
Short name T467
Test name
Test status
Simulation time 1719285592 ps
CPU time 27.29 seconds
Started Jun 26 07:04:00 PM PDT 24
Finished Jun 26 07:04:29 PM PDT 24
Peak memory 239240 kb
Host smart-1b0fd530-e9eb-4f4e-ba7d-198f9455dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141158070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1141158070
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2575414064
Short name T862
Test name
Test status
Simulation time 4462834615 ps
CPU time 6.79 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:04:05 PM PDT 24
Peak memory 233240 kb
Host smart-ab1795e1-36b2-43f8-b13c-15a3fb1e7221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575414064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2575414064
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2021505191
Short name T502
Test name
Test status
Simulation time 399612093 ps
CPU time 2.32 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:04:01 PM PDT 24
Peak memory 224312 kb
Host smart-83db1843-aecd-482b-993a-aa2e1e6ff013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021505191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2021505191
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.905745227
Short name T23
Test name
Test status
Simulation time 116209014 ps
CPU time 4.3 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:04 PM PDT 24
Peak memory 223564 kb
Host smart-21905731-a915-4f31-81d2-ac51e38820f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905745227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.905745227
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3105378641
Short name T151
Test name
Test status
Simulation time 2594624331 ps
CPU time 51.75 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:04:50 PM PDT 24
Peak memory 241300 kb
Host smart-6cf10319-7eee-4820-a24a-a6c38781ff67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105378641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3105378641
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2992918484
Short name T535
Test name
Test status
Simulation time 10854451723 ps
CPU time 56.9 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:57 PM PDT 24
Peak memory 216876 kb
Host smart-24c71d8b-bf11-4bea-bf5c-f6097692dfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992918484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2992918484
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1548033907
Short name T355
Test name
Test status
Simulation time 4883967980 ps
CPU time 13.22 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:04:15 PM PDT 24
Peak memory 216988 kb
Host smart-fc04dd32-ae0b-45f0-98be-856802abcabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548033907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1548033907
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.404347571
Short name T414
Test name
Test status
Simulation time 16165848 ps
CPU time 0.89 seconds
Started Jun 26 07:03:59 PM PDT 24
Finished Jun 26 07:04:02 PM PDT 24
Peak memory 207404 kb
Host smart-7eeddd09-405b-4e9c-9bc1-6fec3b1fe6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404347571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.404347571
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1989722411
Short name T548
Test name
Test status
Simulation time 156110074 ps
CPU time 0.83 seconds
Started Jun 26 07:04:04 PM PDT 24
Finished Jun 26 07:04:06 PM PDT 24
Peak memory 206388 kb
Host smart-077368d5-ba5b-41c9-bd81-9b6ea9eb5591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989722411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1989722411
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4287063981
Short name T503
Test name
Test status
Simulation time 1809109863 ps
CPU time 9.03 seconds
Started Jun 26 07:03:58 PM PDT 24
Finished Jun 26 07:04:09 PM PDT 24
Peak memory 224912 kb
Host smart-bd7e8572-f946-4a97-b827-70fdb622bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287063981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4287063981
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1310515685
Short name T481
Test name
Test status
Simulation time 12099069 ps
CPU time 0.69 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 206240 kb
Host smart-a343a3f3-347b-433a-b5bc-cdb4ff4822ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310515685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1310515685
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1462510548
Short name T140
Test name
Test status
Simulation time 1629141289 ps
CPU time 4.49 seconds
Started Jun 26 07:04:17 PM PDT 24
Finished Jun 26 07:04:23 PM PDT 24
Peak memory 224996 kb
Host smart-3642b704-5c7b-4ff4-bced-c453fcbb8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462510548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1462510548
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.666062914
Short name T299
Test name
Test status
Simulation time 91368571 ps
CPU time 0.8 seconds
Started Jun 26 07:03:56 PM PDT 24
Finished Jun 26 07:03:59 PM PDT 24
Peak memory 206980 kb
Host smart-9df65669-f42b-4f16-b188-db54a9c29c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666062914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.666062914
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2980152619
Short name T658
Test name
Test status
Simulation time 366518411 ps
CPU time 8.6 seconds
Started Jun 26 07:04:12 PM PDT 24
Finished Jun 26 07:04:24 PM PDT 24
Peak memory 236688 kb
Host smart-096de0f8-d6a3-4cc4-b64b-615d7c072304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980152619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2980152619
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2138499032
Short name T958
Test name
Test status
Simulation time 100211863974 ps
CPU time 204.93 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:07:38 PM PDT 24
Peak memory 257124 kb
Host smart-f54ac0ce-3928-4758-8fcb-60f3b1cdf2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138499032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2138499032
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2240893009
Short name T938
Test name
Test status
Simulation time 1199601400 ps
CPU time 14.89 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:28 PM PDT 24
Peak memory 233256 kb
Host smart-f7ad4043-4204-42b9-a401-22a7a2225453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240893009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2240893009
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1833330096
Short name T220
Test name
Test status
Simulation time 245771767 ps
CPU time 6.86 seconds
Started Jun 26 07:04:12 PM PDT 24
Finished Jun 26 07:04:22 PM PDT 24
Peak memory 225148 kb
Host smart-1a3bf41a-2193-44e0-b67b-59808bf9dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833330096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1833330096
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3777441051
Short name T182
Test name
Test status
Simulation time 2355872575 ps
CPU time 17.05 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:31 PM PDT 24
Peak memory 225036 kb
Host smart-1352e6ac-9d81-45e0-8774-8744202a09d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777441051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3777441051
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1491394389
Short name T486
Test name
Test status
Simulation time 3370885941 ps
CPU time 20.99 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:35 PM PDT 24
Peak memory 241028 kb
Host smart-ad9ccde0-7c0e-4144-9e14-6639c030d2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491394389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1491394389
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1162576146
Short name T654
Test name
Test status
Simulation time 6343448225 ps
CPU time 12.79 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:27 PM PDT 24
Peak memory 233264 kb
Host smart-2e79422d-cb0b-4226-8063-fd3d6e90c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162576146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1162576146
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3064019400
Short name T210
Test name
Test status
Simulation time 3749634293 ps
CPU time 13.31 seconds
Started Jun 26 07:04:17 PM PDT 24
Finished Jun 26 07:04:31 PM PDT 24
Peak memory 233304 kb
Host smart-09f1c8c9-fb92-4b4f-97b0-0611f0135b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064019400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3064019400
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4028212082
Short name T597
Test name
Test status
Simulation time 321189437 ps
CPU time 4.16 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:17 PM PDT 24
Peak memory 220712 kb
Host smart-3b7b9c6f-ef0e-4046-bee0-197a0413d6db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4028212082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4028212082
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1517930398
Short name T16
Test name
Test status
Simulation time 551075872 ps
CPU time 1.08 seconds
Started Jun 26 07:04:12 PM PDT 24
Finished Jun 26 07:04:17 PM PDT 24
Peak memory 207364 kb
Host smart-a27deea1-b0b0-476f-8a52-dfa7c8eed88d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517930398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1517930398
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4286899356
Short name T294
Test name
Test status
Simulation time 1546967638 ps
CPU time 12.42 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:12 PM PDT 24
Peak memory 220468 kb
Host smart-f329a0b6-6e12-4578-9d90-2cb886bc311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286899356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4286899356
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3485647527
Short name T751
Test name
Test status
Simulation time 14930712756 ps
CPU time 19.79 seconds
Started Jun 26 07:03:57 PM PDT 24
Finished Jun 26 07:04:19 PM PDT 24
Peak memory 216776 kb
Host smart-6eb0c707-54f9-43ae-ba39-c6655be0c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485647527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3485647527
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2676403203
Short name T402
Test name
Test status
Simulation time 50678571 ps
CPU time 1.35 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:14 PM PDT 24
Peak memory 208568 kb
Host smart-df31bf78-c914-4b37-beb1-29d7d439bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676403203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2676403203
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.836595740
Short name T808
Test name
Test status
Simulation time 141086396 ps
CPU time 0.89 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:14 PM PDT 24
Peak memory 206732 kb
Host smart-385b4c2f-955b-4901-8f7d-10cb9aff422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836595740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.836595740
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2432443338
Short name T846
Test name
Test status
Simulation time 338749963 ps
CPU time 5.03 seconds
Started Jun 26 07:04:13 PM PDT 24
Finished Jun 26 07:04:21 PM PDT 24
Peak memory 224996 kb
Host smart-14e6a98a-d362-4791-b489-6f0bb6334c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432443338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2432443338
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1722404751
Short name T844
Test name
Test status
Simulation time 43592921 ps
CPU time 0.75 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:15 PM PDT 24
Peak memory 205144 kb
Host smart-866f99a7-f721-4158-8e98-f7bf8fbc1db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722404751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1722404751
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1169920865
Short name T805
Test name
Test status
Simulation time 9594642101 ps
CPU time 17.81 seconds
Started Jun 26 07:04:12 PM PDT 24
Finished Jun 26 07:04:33 PM PDT 24
Peak memory 225140 kb
Host smart-8618b4c0-7e7b-44b1-a55e-3468e3a176e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169920865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1169920865
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2915625011
Short name T918
Test name
Test status
Simulation time 45272130 ps
CPU time 0.77 seconds
Started Jun 26 07:04:12 PM PDT 24
Finished Jun 26 07:04:16 PM PDT 24
Peak memory 206804 kb
Host smart-750c9570-2147-4d69-8185-7cf8a72291e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915625011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2915625011
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.671017514
Short name T579
Test name
Test status
Simulation time 14599183182 ps
CPU time 30.46 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:04:45 PM PDT 24
Peak memory 249664 kb
Host smart-3c2af6f5-82f7-4e79-8f0b-472fcb593b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671017514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.671017514
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.970112156
Short name T407
Test name
Test status
Simulation time 34873095716 ps
CPU time 136.1 seconds
Started Jun 26 07:04:09 PM PDT 24
Finished Jun 26 07:06:27 PM PDT 24
Peak memory 249708 kb
Host smart-3ebfca38-9965-441c-a578-ef5d81099411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970112156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.970112156
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2342517981
Short name T216
Test name
Test status
Simulation time 92384984531 ps
CPU time 255.6 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:08:29 PM PDT 24
Peak memory 263436 kb
Host smart-fd64c362-170b-4b7c-98f3-035fb5084901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342517981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2342517981
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1382407991
Short name T689
Test name
Test status
Simulation time 1635052881 ps
CPU time 8.33 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:21 PM PDT 24
Peak memory 249644 kb
Host smart-7c24fed8-dc0d-4ee0-8c15-4b5bc9be0a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382407991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1382407991
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.177773362
Short name T213
Test name
Test status
Simulation time 161385035 ps
CPU time 3.51 seconds
Started Jun 26 07:04:22 PM PDT 24
Finished Jun 26 07:04:28 PM PDT 24
Peak memory 224972 kb
Host smart-9a8274fb-5b5d-442b-8466-4b7da9f2c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177773362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.177773362
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2575739884
Short name T64
Test name
Test status
Simulation time 5726934905 ps
CPU time 52.49 seconds
Started Jun 26 07:04:09 PM PDT 24
Finished Jun 26 07:05:04 PM PDT 24
Peak memory 237548 kb
Host smart-330248a7-94f5-485a-a654-a12893204fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575739884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2575739884
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1271385056
Short name T412
Test name
Test status
Simulation time 10832887320 ps
CPU time 13.92 seconds
Started Jun 26 07:04:17 PM PDT 24
Finished Jun 26 07:04:32 PM PDT 24
Peak memory 224956 kb
Host smart-7fb9ae2c-d197-495e-9779-541afffc1b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271385056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1271385056
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.971986630
Short name T734
Test name
Test status
Simulation time 468474884 ps
CPU time 9.1 seconds
Started Jun 26 07:04:17 PM PDT 24
Finished Jun 26 07:04:27 PM PDT 24
Peak memory 249152 kb
Host smart-2f2314cb-a170-4b9c-8561-9da6f10b3a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971986630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.971986630
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3703429657
Short name T359
Test name
Test status
Simulation time 1393486704 ps
CPU time 14.98 seconds
Started Jun 26 07:04:14 PM PDT 24
Finished Jun 26 07:04:31 PM PDT 24
Peak memory 220948 kb
Host smart-3ce8e54a-9cf0-4534-9564-cf99b377e5a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3703429657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3703429657
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.401996293
Short name T258
Test name
Test status
Simulation time 55060973882 ps
CPU time 659.73 seconds
Started Jun 26 07:04:11 PM PDT 24
Finished Jun 26 07:15:13 PM PDT 24
Peak memory 303272 kb
Host smart-29afb9f2-b603-4097-ad79-e2c3b355be37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401996293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.401996293
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1362763025
Short name T966
Test name
Test status
Simulation time 8222167260 ps
CPU time 25.39 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:37 PM PDT 24
Peak memory 216868 kb
Host smart-180596c3-c804-46c1-95f6-8d96674bc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362763025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1362763025
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3757114612
Short name T534
Test name
Test status
Simulation time 2079646495 ps
CPU time 6.3 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:18 PM PDT 24
Peak memory 216716 kb
Host smart-46b79301-1289-4697-9d6d-c37578c7fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757114612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3757114612
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.455467868
Short name T309
Test name
Test status
Simulation time 21176002 ps
CPU time 0.76 seconds
Started Jun 26 07:04:10 PM PDT 24
Finished Jun 26 07:04:13 PM PDT 24
Peak memory 206316 kb
Host smart-8de029bc-f075-41bf-85b8-339794d07fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455467868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.455467868
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3502846849
Short name T45
Test name
Test status
Simulation time 49501482 ps
CPU time 0.82 seconds
Started Jun 26 07:04:22 PM PDT 24
Finished Jun 26 07:04:26 PM PDT 24
Peak memory 206388 kb
Host smart-b7555104-18ff-48f8-9489-6e892f4d870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502846849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3502846849
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3599495259
Short name T842
Test name
Test status
Simulation time 1176006015 ps
CPU time 8.55 seconds
Started Jun 26 07:04:22 PM PDT 24
Finished Jun 26 07:04:33 PM PDT 24
Peak memory 233208 kb
Host smart-a0a55423-a2d0-40c5-b044-e9412bf06edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599495259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3599495259
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1883175332
Short name T54
Test name
Test status
Simulation time 14155727 ps
CPU time 0.77 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:27 PM PDT 24
Peak memory 206236 kb
Host smart-14ec6b52-4cec-422f-88b1-f941a1f964c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883175332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
883175332
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3803834469
Short name T52
Test name
Test status
Simulation time 390765307 ps
CPU time 4.75 seconds
Started Jun 26 07:00:25 PM PDT 24
Finished Jun 26 07:00:32 PM PDT 24
Peak memory 233176 kb
Host smart-886037e7-0e28-4b42-8169-6b00e3b299ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803834469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3803834469
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1420773673
Short name T542
Test name
Test status
Simulation time 159194193 ps
CPU time 0.77 seconds
Started Jun 26 07:00:28 PM PDT 24
Finished Jun 26 07:00:30 PM PDT 24
Peak memory 206968 kb
Host smart-7e61e4a3-56db-4df9-a84d-81f34b906e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420773673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1420773673
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2480063787
Short name T888
Test name
Test status
Simulation time 1400537323 ps
CPU time 11.02 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:36 PM PDT 24
Peak memory 234696 kb
Host smart-cfa10728-ead2-4f4a-a058-10566f2bf6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480063787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2480063787
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2512147149
Short name T267
Test name
Test status
Simulation time 19560277762 ps
CPU time 71.11 seconds
Started Jun 26 07:00:25 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 252788 kb
Host smart-7442f9cd-e757-4ed4-819a-4de215f00f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512147149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2512147149
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2984591691
Short name T895
Test name
Test status
Simulation time 596225600 ps
CPU time 17.14 seconds
Started Jun 26 07:00:18 PM PDT 24
Finished Jun 26 07:00:37 PM PDT 24
Peak memory 250412 kb
Host smart-78d99dbc-6d8c-4ef2-893c-e590439db7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984591691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2984591691
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3523031652
Short name T229
Test name
Test status
Simulation time 315194145 ps
CPU time 3.79 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:28 PM PDT 24
Peak memory 225024 kb
Host smart-3f7d439d-055b-4372-bb84-ae501d9f4765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523031652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3523031652
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.312861144
Short name T835
Test name
Test status
Simulation time 292474303 ps
CPU time 7.13 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:34 PM PDT 24
Peak memory 240964 kb
Host smart-5b342694-53df-41f9-8724-5180b3a216b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312861144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.312861144
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1780795888
Short name T506
Test name
Test status
Simulation time 30971693 ps
CPU time 1.07 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 218412 kb
Host smart-88eb7008-e224-4327-b61d-832c63ff1f72
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780795888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1780795888
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1287383733
Short name T273
Test name
Test status
Simulation time 3634891674 ps
CPU time 13.95 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:37 PM PDT 24
Peak memory 241424 kb
Host smart-5b769680-9483-404f-ab41-7791521b3e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287383733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1287383733
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4116225039
Short name T237
Test name
Test status
Simulation time 1366414225 ps
CPU time 5.73 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:31 PM PDT 24
Peak memory 224804 kb
Host smart-8e44df5f-5c26-448b-857d-cb0c388a08e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116225039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4116225039
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2145520993
Short name T531
Test name
Test status
Simulation time 849455685 ps
CPU time 7.98 seconds
Started Jun 26 07:00:26 PM PDT 24
Finished Jun 26 07:00:36 PM PDT 24
Peak memory 222768 kb
Host smart-72da0dc7-8583-4bb0-ac16-be11a8377a84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2145520993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2145520993
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.423438176
Short name T965
Test name
Test status
Simulation time 16072256066 ps
CPU time 135.47 seconds
Started Jun 26 07:00:28 PM PDT 24
Finished Jun 26 07:02:45 PM PDT 24
Peak memory 265548 kb
Host smart-6c746934-2080-4c81-93d0-d99d8abea344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423438176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.423438176
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1553470506
Short name T483
Test name
Test status
Simulation time 2146321481 ps
CPU time 20.61 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 216772 kb
Host smart-20506bc6-d1c5-4b6f-8bc8-5c9430c924c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553470506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1553470506
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2584626574
Short name T795
Test name
Test status
Simulation time 11069589688 ps
CPU time 13.4 seconds
Started Jun 26 07:00:30 PM PDT 24
Finished Jun 26 07:00:45 PM PDT 24
Peak memory 216864 kb
Host smart-23d3c813-4cae-4172-9d34-71b75bc81ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584626574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2584626574
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3198711903
Short name T725
Test name
Test status
Simulation time 79845152 ps
CPU time 1.7 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:27 PM PDT 24
Peak memory 216820 kb
Host smart-9a84b02b-5856-4019-8d32-097571b57a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198711903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3198711903
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3554996319
Short name T377
Test name
Test status
Simulation time 77443360 ps
CPU time 0.88 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:24 PM PDT 24
Peak memory 206192 kb
Host smart-f8ff3a4c-b437-4ebd-9575-8a722f064ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554996319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3554996319
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.11755348
Short name T769
Test name
Test status
Simulation time 4038217733 ps
CPU time 15.34 seconds
Started Jun 26 07:00:32 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 233224 kb
Host smart-57050b80-39e1-4971-a531-0328a41b9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11755348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.11755348
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3366133284
Short name T826
Test name
Test status
Simulation time 93921452 ps
CPU time 0.72 seconds
Started Jun 26 07:00:43 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 205308 kb
Host smart-5a72d45c-dbb1-4331-b5a5-892529bfcefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366133284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
366133284
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2883537194
Short name T226
Test name
Test status
Simulation time 1508913601 ps
CPU time 15.16 seconds
Started Jun 26 07:00:33 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 224928 kb
Host smart-74c8b836-b384-4d57-b019-902faa0dacfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883537194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2883537194
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1320522857
Short name T616
Test name
Test status
Simulation time 32883193 ps
CPU time 0.82 seconds
Started Jun 26 07:00:22 PM PDT 24
Finished Jun 26 07:00:25 PM PDT 24
Peak memory 207000 kb
Host smart-df7af02f-9fde-4694-8b46-5d1ecae1c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320522857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1320522857
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1823983927
Short name T588
Test name
Test status
Simulation time 167857725915 ps
CPU time 289.58 seconds
Started Jun 26 07:00:45 PM PDT 24
Finished Jun 26 07:05:36 PM PDT 24
Peak memory 252148 kb
Host smart-afb11ff8-5e71-44ee-afb3-3052c33470bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823983927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1823983927
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3342731497
Short name T520
Test name
Test status
Simulation time 19563717988 ps
CPU time 16.51 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:01:00 PM PDT 24
Peak memory 224896 kb
Host smart-2e4082c6-c25f-401b-b023-e42d25bfda01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342731497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3342731497
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2569432194
Short name T937
Test name
Test status
Simulation time 655858154 ps
CPU time 6.29 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:32 PM PDT 24
Peak memory 224960 kb
Host smart-e4975d0d-e72b-4ea4-883f-1ac7b02d5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569432194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2569432194
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1473241168
Short name T10
Test name
Test status
Simulation time 38815748844 ps
CPU time 60.47 seconds
Started Jun 26 07:00:26 PM PDT 24
Finished Jun 26 07:01:28 PM PDT 24
Peak memory 233192 kb
Host smart-56606b83-0d4c-48e5-9f89-172a112e43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473241168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1473241168
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1484735217
Short name T875
Test name
Test status
Simulation time 85065970 ps
CPU time 1.05 seconds
Started Jun 26 07:00:20 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 217132 kb
Host smart-ac9ece14-5ebf-4d5d-860b-7f55792545c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484735217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1484735217
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3111348614
Short name T189
Test name
Test status
Simulation time 3714968155 ps
CPU time 13.83 seconds
Started Jun 26 07:00:21 PM PDT 24
Finished Jun 26 07:00:37 PM PDT 24
Peak memory 233184 kb
Host smart-46cb0432-6a07-4790-9427-07458d6f0521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111348614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3111348614
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.755127147
Short name T380
Test name
Test status
Simulation time 314427471 ps
CPU time 3.29 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:29 PM PDT 24
Peak memory 233192 kb
Host smart-714887f1-a49b-42a5-aedf-86df1397ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755127147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.755127147
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2827821969
Short name T768
Test name
Test status
Simulation time 153292866 ps
CPU time 4.29 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:48 PM PDT 24
Peak memory 223616 kb
Host smart-9e14aa7d-2a18-4345-b5d4-867a0d28cacd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2827821969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2827821969
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3826342747
Short name T150
Test name
Test status
Simulation time 1405031130 ps
CPU time 1.16 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 207348 kb
Host smart-f6e2f583-2d4a-4b40-b673-45a13f02c3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826342747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3826342747
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1835800020
Short name T529
Test name
Test status
Simulation time 2365776062 ps
CPU time 19.69 seconds
Started Jun 26 07:00:23 PM PDT 24
Finished Jun 26 07:00:45 PM PDT 24
Peak memory 216904 kb
Host smart-42720ab4-c7bf-4287-b682-49fce57d8cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835800020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1835800020
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4222709141
Short name T308
Test name
Test status
Simulation time 147657749 ps
CPU time 1.48 seconds
Started Jun 26 07:00:28 PM PDT 24
Finished Jun 26 07:00:31 PM PDT 24
Peak memory 208380 kb
Host smart-9034ef9e-8039-4f9d-bcce-309caf2a994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222709141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4222709141
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2598053192
Short name T894
Test name
Test status
Simulation time 663495385 ps
CPU time 8.21 seconds
Started Jun 26 07:00:20 PM PDT 24
Finished Jun 26 07:00:30 PM PDT 24
Peak memory 216876 kb
Host smart-15a7134f-66e4-4e73-82e3-bcb74e4a9847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598053192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2598053192
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2182127970
Short name T564
Test name
Test status
Simulation time 41182864 ps
CPU time 0.76 seconds
Started Jun 26 07:00:24 PM PDT 24
Finished Jun 26 07:00:27 PM PDT 24
Peak memory 206360 kb
Host smart-c65e978a-717b-4334-af16-6a8f97200d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182127970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2182127970
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2898381277
Short name T847
Test name
Test status
Simulation time 381693266 ps
CPU time 2.26 seconds
Started Jun 26 07:00:26 PM PDT 24
Finished Jun 26 07:00:30 PM PDT 24
Peak memory 223608 kb
Host smart-b172c4f9-0b1c-47e9-8959-2dbbc3afeffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898381277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2898381277
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1725296749
Short name T600
Test name
Test status
Simulation time 43413998 ps
CPU time 0.74 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:00:40 PM PDT 24
Peak memory 205952 kb
Host smart-566f32b3-b22f-40f9-802a-272d9e5d5793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725296749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
725296749
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2152573167
Short name T892
Test name
Test status
Simulation time 67814049 ps
CPU time 2.97 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 232936 kb
Host smart-5d2464b4-1041-48df-9f09-713857cef307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152573167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2152573167
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4107218009
Short name T637
Test name
Test status
Simulation time 104102803 ps
CPU time 0.77 seconds
Started Jun 26 07:00:38 PM PDT 24
Finished Jun 26 07:00:39 PM PDT 24
Peak memory 206316 kb
Host smart-f8187fba-940d-4ea6-ac75-0d35a88c77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107218009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4107218009
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1334475283
Short name T655
Test name
Test status
Simulation time 53184988801 ps
CPU time 100.66 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:02:24 PM PDT 24
Peak memory 249948 kb
Host smart-a76e27b5-c199-472c-9dbb-b7161a68aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334475283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1334475283
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2521600457
Short name T194
Test name
Test status
Simulation time 165303354457 ps
CPU time 206.69 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:04:10 PM PDT 24
Peak memory 255188 kb
Host smart-365f3b17-2765-4f67-a020-2f94b9f43b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521600457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2521600457
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.128286465
Short name T276
Test name
Test status
Simulation time 25673295941 ps
CPU time 104.42 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:02:28 PM PDT 24
Peak memory 255624 kb
Host smart-21d6a679-01b6-44ac-907f-b55f7ab50e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128286465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
128286465
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2228129011
Short name T632
Test name
Test status
Simulation time 936478026 ps
CPU time 3.33 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:44 PM PDT 24
Peak memory 233184 kb
Host smart-c0f57850-65bd-4ec7-ad4d-4bfc550e0f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228129011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2228129011
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2053252068
Short name T224
Test name
Test status
Simulation time 200581684 ps
CPU time 2.69 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:44 PM PDT 24
Peak memory 225004 kb
Host smart-ceb0b61d-a5cf-41bc-b3d8-9faf4496a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053252068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2053252068
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2794145695
Short name T702
Test name
Test status
Simulation time 4923978120 ps
CPU time 27.31 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:01:08 PM PDT 24
Peak memory 241408 kb
Host smart-0a11b911-0854-47b7-89af-86718ab779a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794145695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2794145695
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1776062998
Short name T306
Test name
Test status
Simulation time 164752172 ps
CPU time 1.13 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:00:44 PM PDT 24
Peak memory 217140 kb
Host smart-9d4fb655-86d7-4f6f-8e62-9070bd9bd360
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776062998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1776062998
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3115368477
Short name T625
Test name
Test status
Simulation time 22768352622 ps
CPU time 16.9 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:59 PM PDT 24
Peak memory 233224 kb
Host smart-591be02a-87b8-4555-8bbb-797ba5674410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115368477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3115368477
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1861483941
Short name T397
Test name
Test status
Simulation time 121031465 ps
CPU time 3.68 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 224952 kb
Host smart-a429c0f8-05be-4065-ae07-d89022fd0ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861483941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1861483941
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1333881150
Short name T135
Test name
Test status
Simulation time 887679610 ps
CPU time 9.64 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:51 PM PDT 24
Peak memory 222288 kb
Host smart-9d27cd42-a894-4201-a7c2-c2fdc0fecb71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1333881150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1333881150
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2959682691
Short name T460
Test name
Test status
Simulation time 3588975012 ps
CPU time 26.42 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:01:06 PM PDT 24
Peak memory 216948 kb
Host smart-039dc4ab-8e55-41a2-9fb0-dfbaf8b5ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959682691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2959682691
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1934852160
Short name T324
Test name
Test status
Simulation time 888203727 ps
CPU time 4.32 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 216780 kb
Host smart-ec62de3b-d9f8-469d-9f79-157f6f4a16b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934852160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1934852160
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1827982074
Short name T307
Test name
Test status
Simulation time 113967665 ps
CPU time 1.02 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:00:41 PM PDT 24
Peak memory 207476 kb
Host smart-3f64ac97-3a88-49db-842a-f123aa6b2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827982074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1827982074
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1973405191
Short name T345
Test name
Test status
Simulation time 50535355 ps
CPU time 0.78 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:00:41 PM PDT 24
Peak memory 206340 kb
Host smart-2c8b28e9-c169-4750-9084-d54a60b3ad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973405191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1973405191
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2033160734
Short name T536
Test name
Test status
Simulation time 82826576 ps
CPU time 3.21 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 233220 kb
Host smart-d7b3974e-61c0-4330-b7bb-38041184f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033160734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2033160734
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3001614281
Short name T22
Test name
Test status
Simulation time 47160046 ps
CPU time 0.84 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:00:46 PM PDT 24
Peak memory 206068 kb
Host smart-0e5d7b07-47eb-4aed-bde0-71ad770d9758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001614281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
001614281
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.143517813
Short name T811
Test name
Test status
Simulation time 83534311 ps
CPU time 2.84 seconds
Started Jun 26 07:00:38 PM PDT 24
Finished Jun 26 07:00:42 PM PDT 24
Peak memory 233192 kb
Host smart-f01e0b55-90fa-4bf6-a131-e70cdc7f66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143517813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.143517813
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.165670110
Short name T53
Test name
Test status
Simulation time 16206169 ps
CPU time 0.77 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:42 PM PDT 24
Peak memory 205952 kb
Host smart-9379d700-187c-42b0-a3af-776426f018eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165670110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.165670110
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1764119973
Short name T738
Test name
Test status
Simulation time 50571334 ps
CPU time 0.89 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:42 PM PDT 24
Peak memory 216512 kb
Host smart-181b624a-62b5-4ba8-b5af-a15cc4bfa91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764119973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1764119973
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.189057591
Short name T499
Test name
Test status
Simulation time 8420058685 ps
CPU time 30.78 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:01:13 PM PDT 24
Peak memory 218140 kb
Host smart-e4315bb4-4d2e-42b8-a70f-13a8be9391c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189057591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.189057591
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2542895134
Short name T686
Test name
Test status
Simulation time 19798850 ps
CPU time 0.8 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:00:42 PM PDT 24
Peak memory 216308 kb
Host smart-ec4b2b80-a9c4-43a8-ac86-025cf70a1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542895134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2542895134
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1477191448
Short name T972
Test name
Test status
Simulation time 854679157 ps
CPU time 11.43 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:00:52 PM PDT 24
Peak memory 241136 kb
Host smart-277c5616-57da-45b6-823f-498af2d80c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477191448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1477191448
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3196276604
Short name T395
Test name
Test status
Simulation time 804733294 ps
CPU time 4.26 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 224940 kb
Host smart-54e04a7d-bf8f-4d6e-92a8-3e4cfc8f976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196276604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3196276604
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2477403003
Short name T942
Test name
Test status
Simulation time 1824797136 ps
CPU time 15.51 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:00:56 PM PDT 24
Peak memory 252552 kb
Host smart-3fe33f28-d2eb-4ab3-af6f-efa295139db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477403003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2477403003
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1391847977
Short name T798
Test name
Test status
Simulation time 63972527 ps
CPU time 1.15 seconds
Started Jun 26 07:00:34 PM PDT 24
Finished Jun 26 07:00:36 PM PDT 24
Peak memory 217184 kb
Host smart-0106cca0-a549-4fa9-8ba8-0bb1cfb12cf1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391847977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1391847977
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1965548507
Short name T628
Test name
Test status
Simulation time 5085091314 ps
CPU time 5.22 seconds
Started Jun 26 07:00:43 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 241220 kb
Host smart-5822951d-970c-4e18-91be-0ce5a0d3d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965548507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1965548507
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.82103612
Short name T442
Test name
Test status
Simulation time 313518128 ps
CPU time 4.14 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 233184 kb
Host smart-5e788f12-6952-4d75-a340-9d74256fc90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82103612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.82103612
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3497540413
Short name T79
Test name
Test status
Simulation time 245771419 ps
CPU time 5.76 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 222304 kb
Host smart-a255e2cf-7b02-4ee7-a786-99bf53911910
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3497540413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3497540413
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2729585244
Short name T206
Test name
Test status
Simulation time 22812204793 ps
CPU time 255.39 seconds
Started Jun 26 07:00:39 PM PDT 24
Finished Jun 26 07:04:56 PM PDT 24
Peak memory 256192 kb
Host smart-bf2764b9-c3e3-48f8-8a47-eb66fe0cf8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729585244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2729585244
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3090401959
Short name T759
Test name
Test status
Simulation time 6893303445 ps
CPU time 32.95 seconds
Started Jun 26 07:00:40 PM PDT 24
Finished Jun 26 07:01:15 PM PDT 24
Peak memory 216992 kb
Host smart-0b6a48f0-0b38-4bf0-a497-fe708f56ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090401959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3090401959
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.814559549
Short name T297
Test name
Test status
Simulation time 470138243 ps
CPU time 3.28 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 216804 kb
Host smart-2dcf2f51-8cfd-4ba3-8ce8-04a69c87b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814559549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.814559549
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3049490995
Short name T429
Test name
Test status
Simulation time 133763029 ps
CPU time 1.13 seconds
Started Jun 26 07:00:41 PM PDT 24
Finished Jun 26 07:00:44 PM PDT 24
Peak memory 207680 kb
Host smart-2ce5babe-012b-40aa-9f0f-a7142b66c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049490995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3049490995
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3943200537
Short name T644
Test name
Test status
Simulation time 168680939 ps
CPU time 0.82 seconds
Started Jun 26 07:00:43 PM PDT 24
Finished Jun 26 07:00:45 PM PDT 24
Peak memory 206380 kb
Host smart-b54cc56b-3d42-47f1-9ac0-c4eba5ccd95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943200537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3943200537
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2263127212
Short name T543
Test name
Test status
Simulation time 5520002526 ps
CPU time 7.69 seconds
Started Jun 26 07:00:42 PM PDT 24
Finished Jun 26 07:00:52 PM PDT 24
Peak memory 225036 kb
Host smart-80fd598d-e633-44e2-8516-e9bbd90b2276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263127212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2263127212
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.299877638
Short name T325
Test name
Test status
Simulation time 23740772 ps
CPU time 0.75 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 205828 kb
Host smart-5be1e698-f3af-4093-9269-4cb0c879b0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299877638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.299877638
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2700008064
Short name T77
Test name
Test status
Simulation time 1249070500 ps
CPU time 4.38 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 225012 kb
Host smart-3eca6db7-b249-49ce-a018-80c398f6108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700008064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2700008064
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1260467157
Short name T549
Test name
Test status
Simulation time 47093342 ps
CPU time 0.81 seconds
Started Jun 26 07:00:51 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 206984 kb
Host smart-2120abca-bd51-402f-bd0e-c10bbaaa71e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260467157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1260467157
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.176628370
Short name T779
Test name
Test status
Simulation time 25591283306 ps
CPU time 50.32 seconds
Started Jun 26 07:00:45 PM PDT 24
Finished Jun 26 07:01:38 PM PDT 24
Peak memory 249972 kb
Host smart-56b3dbd1-e62e-4d89-b884-8c77cca281d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176628370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.176628370
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3630047135
Short name T480
Test name
Test status
Simulation time 221701310004 ps
CPU time 322.04 seconds
Started Jun 26 07:00:44 PM PDT 24
Finished Jun 26 07:06:08 PM PDT 24
Peak memory 251504 kb
Host smart-a9b036ac-578a-47c5-8748-07d9afb15fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630047135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3630047135
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3749627889
Short name T197
Test name
Test status
Simulation time 7918942687 ps
CPU time 156.72 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:03:28 PM PDT 24
Peak memory 272884 kb
Host smart-15b0df08-0488-4bb4-8850-fe5304ca920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749627889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3749627889
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2318783581
Short name T124
Test name
Test status
Simulation time 9654488230 ps
CPU time 20.37 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:01:10 PM PDT 24
Peak memory 233316 kb
Host smart-ae5ed47f-a592-4a53-a738-d2e4a7bfa69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318783581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2318783581
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1746750438
Short name T960
Test name
Test status
Simulation time 662212643 ps
CPU time 7.97 seconds
Started Jun 26 07:00:47 PM PDT 24
Finished Jun 26 07:00:58 PM PDT 24
Peak memory 233220 kb
Host smart-5c2cec26-8fe3-4613-b446-b9dca527e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746750438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1746750438
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3508761151
Short name T435
Test name
Test status
Simulation time 112607529 ps
CPU time 5.38 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:00:57 PM PDT 24
Peak memory 233220 kb
Host smart-1d30c267-c8fe-4e27-827d-76e32638766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508761151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3508761151
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2921793681
Short name T490
Test name
Test status
Simulation time 18570703 ps
CPU time 1.07 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 217184 kb
Host smart-c2817be5-ddda-469d-bc46-d1839666342d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921793681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2921793681
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2888347594
Short name T35
Test name
Test status
Simulation time 64359631830 ps
CPU time 14.79 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:04 PM PDT 24
Peak memory 233248 kb
Host smart-85d4135f-b62b-406d-a703-c5f64ce21016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888347594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2888347594
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.345408335
Short name T217
Test name
Test status
Simulation time 1757936451 ps
CPU time 6.28 seconds
Started Jun 26 07:00:45 PM PDT 24
Finished Jun 26 07:00:52 PM PDT 24
Peak memory 225012 kb
Host smart-0502859a-b973-4015-9bea-c8256edcf7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345408335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.345408335
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1675167423
Short name T687
Test name
Test status
Simulation time 5367680341 ps
CPU time 16.9 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:05 PM PDT 24
Peak memory 222776 kb
Host smart-6f974f91-815f-4926-af00-7b574274b9da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1675167423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1675167423
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.656770416
Short name T423
Test name
Test status
Simulation time 1434313691 ps
CPU time 16.39 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:05 PM PDT 24
Peak memory 217016 kb
Host smart-b7de0430-a443-4d78-80a5-45af12224ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656770416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.656770416
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2014843369
Short name T512
Test name
Test status
Simulation time 364062146 ps
CPU time 2.1 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 216768 kb
Host smart-ba4251a8-f683-48f6-9241-d121bba93737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014843369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2014843369
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1434533384
Short name T841
Test name
Test status
Simulation time 138552707 ps
CPU time 1.74 seconds
Started Jun 26 07:00:48 PM PDT 24
Finished Jun 26 07:00:54 PM PDT 24
Peak memory 216468 kb
Host smart-71834ca1-6390-40fb-88c7-7e8f80bb6cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434533384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1434533384
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2117460481
Short name T372
Test name
Test status
Simulation time 129108015 ps
CPU time 0.83 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:00:50 PM PDT 24
Peak memory 206364 kb
Host smart-f98e1b53-83bc-4229-806a-d9b9a8db4644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117460481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2117460481
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2406062920
Short name T365
Test name
Test status
Simulation time 39326139785 ps
CPU time 23.31 seconds
Started Jun 26 07:00:46 PM PDT 24
Finished Jun 26 07:01:12 PM PDT 24
Peak memory 224996 kb
Host smart-5e4ff1aa-c82a-48a2-9e17-d6281a8fdde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406062920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2406062920
Directory /workspace/9.spi_device_upload/latest
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