Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3605744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4369667

1

T1

1360

T2

899

T3

5610

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4386756	1			T1	950		T2	58		T3	8817
values[0x0]	1793232	1			T1	452		T2	424		T3	2790
values[0x1]	1795423	1			T1	453		T2	454		T3	2904

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2566007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5409404

1

T1

1463

T2

903

T3

8228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31858	1			T1	2		T2	8		T3	82
valid_sources[0x01]	28117	1			T1	6		T2	4		T3	53
valid_sources[0x02]	30791	1			T1	3		T2	4		T3	71
valid_sources[0x03]	29846	1			T1	4		T2	6		T3	90
valid_sources[0x04]	30759	1			T1	7		T2	1		T3	106
valid_sources[0x05]	30029	1			T1	14		T2	5		T3	39
valid_sources[0x06]	28726	1			T1	14		T2	2		T3	73
valid_sources[0x07]	31928	1			T1	15		T2	2		T3	126
valid_sources[0x08]	29552	1			T1	9		T2	3		T3	20
valid_sources[0x09]	30546	1			T1	8		T2	5		T3	51
valid_sources[0x0a]	30872	1			T1	15		T2	3		T3	53
valid_sources[0x0b]	28561	1			T1	7		T2	3		T3	18
valid_sources[0x0c]	33030	1			T1	3		T2	1		T3	60
valid_sources[0x0d]	29250	1			T1	18		T2	6		T3	39
valid_sources[0x0e]	27859	1			T1	6		T2	4		T3	26
valid_sources[0x0f]	28686	1			T1	13		T2	2		T3	54
valid_sources[0x10]	28197	1			T2	6		T3	66		T4	11
valid_sources[0x11]	28208	1			T1	8		T2	4		T3	25
valid_sources[0x12]	31622	1			T1	21		T2	3		T3	57
valid_sources[0x13]	31747	1			T1	4		T2	4		T3	79
valid_sources[0x14]	36540	1			T1	1		T2	1		T3	59
valid_sources[0x15]	28913	1			T1	3		T2	2		T3	129
valid_sources[0x16]	30200	1			T2	3		T3	89		T4	12
valid_sources[0x17]	33309	1			T1	9		T2	7		T3	69
valid_sources[0x18]	30030	1			T1	1		T2	3		T3	61
valid_sources[0x19]	29387	1			T1	4		T2	1		T3	65
valid_sources[0x1a]	30655	1			T1	1		T3	40		T4	10
valid_sources[0x1b]	37161	1			T1	5		T2	3		T3	42
valid_sources[0x1c]	29390	1			T1	4		T2	2		T3	84
valid_sources[0x1d]	27410	1			T2	4		T3	62		T5	3
valid_sources[0x1e]	29467	1			T2	2		T3	17		T5	12
valid_sources[0x1f]	28322	1			T1	15		T2	5		T3	13
valid_sources[0x20]	30192	1			T1	7		T2	1		T3	35
valid_sources[0x21]	26934	1			T1	21		T2	2		T3	69
valid_sources[0x22]	29239	1			T1	5		T2	1		T3	53
valid_sources[0x23]	30430	1			T1	4		T2	7		T3	74
valid_sources[0x24]	29079	1			T1	4		T2	5		T3	52
valid_sources[0x25]	31845	1			T2	2		T3	47		T5	11
valid_sources[0x26]	31971	1			T1	12		T2	1		T3	68
valid_sources[0x27]	29940	1			T1	4		T2	2		T3	80
valid_sources[0x28]	32326	1			T1	1		T2	4		T3	110
valid_sources[0x29]	38867	1			T1	1		T3	49		T7	2
valid_sources[0x2a]	37188	1			T1	6		T2	9		T3	76
valid_sources[0x2b]	31151	1			T1	14		T2	3		T3	108
valid_sources[0x2c]	27747	1			T1	2		T2	5		T3	99
valid_sources[0x2d]	30986	1			T1	8		T2	2		T3	59
valid_sources[0x2e]	30431	1			T1	3		T2	9		T3	60
valid_sources[0x2f]	28165	1			T1	3		T2	4		T3	30
valid_sources[0x30]	31542	1			T1	3		T2	6		T3	27
valid_sources[0x31]	29981	1			T2	2		T3	23		T4	2
valid_sources[0x32]	29916	1			T1	8		T2	1		T3	43
valid_sources[0x33]	29386	1			T1	7		T2	3		T3	56
valid_sources[0x34]	80268	1			T1	4		T2	3		T3	24
valid_sources[0x35]	29085	1			T1	9		T2	3		T3	56
valid_sources[0x36]	34617	1			T1	11		T2	2		T3	68
valid_sources[0x37]	27698	1			T1	2		T2	3		T3	62
valid_sources[0x38]	30618	1			T1	1		T2	2		T3	61
valid_sources[0x39]	30248	1			T1	3		T2	3		T3	28
valid_sources[0x3a]	32178	1			T1	15		T2	4		T3	70
valid_sources[0x3b]	28295	1			T1	4		T2	2		T3	12
valid_sources[0x3c]	29261	1			T1	2		T2	2		T3	80
valid_sources[0x3d]	30828	1			T1	7		T2	1		T3	13
valid_sources[0x3e]	27887	1			T1	2		T2	6		T3	48
valid_sources[0x3f]	27231	1			T1	2		T2	2		T3	89
valid_sources[0x40]	30454	1			T1	14		T2	2		T3	53
valid_sources[0x41]	28937	1			T1	14		T2	3		T3	36
valid_sources[0x42]	34960	1			T1	2		T2	1		T3	110
valid_sources[0x43]	30331	1			T1	23		T2	4		T3	80
valid_sources[0x44]	38432	1			T1	14		T2	5		T3	40
valid_sources[0x45]	30470	1			T1	19		T2	3		T3	42
valid_sources[0x46]	31680	1			T1	8		T2	6		T3	51
valid_sources[0x47]	30072	1			T1	10		T2	8		T3	40
valid_sources[0x48]	28416	1			T1	8		T2	2		T3	87
valid_sources[0x49]	26551	1			T1	10		T2	1		T3	46
valid_sources[0x4a]	28080	1			T1	3		T2	5		T3	51
valid_sources[0x4b]	32102	1			T1	5		T2	1		T3	20
valid_sources[0x4c]	29091	1			T1	16		T2	7		T3	45
valid_sources[0x4d]	28829	1			T1	7		T2	3		T3	50
valid_sources[0x4e]	30570	1			T1	3		T2	2		T3	55
valid_sources[0x4f]	31077	1			T1	14		T2	5		T3	44
valid_sources[0x50]	31052	1			T1	15		T2	6		T3	73
valid_sources[0x51]	28115	1			T1	14		T2	6		T3	32
valid_sources[0x52]	28964	1			T1	1		T2	7		T3	33
valid_sources[0x53]	34327	1			T1	10		T2	4		T3	84
valid_sources[0x54]	28670	1			T1	15		T2	9		T3	61
valid_sources[0x55]	29192	1			T1	17		T2	2		T3	52
valid_sources[0x56]	35651	1			T2	2		T3	66		T5	2
valid_sources[0x57]	29325	1			T1	7		T2	1		T3	75
valid_sources[0x58]	28650	1			T1	3		T2	4		T3	86
valid_sources[0x59]	29516	1			T1	2		T2	3		T3	23
valid_sources[0x5a]	31802	1			T1	5		T2	3		T3	22
valid_sources[0x5b]	28412	1			T1	10		T2	3		T3	43
valid_sources[0x5c]	49390	1			T1	13		T2	3		T3	29
valid_sources[0x5d]	28118	1			T1	10		T2	2		T3	91
valid_sources[0x5e]	26962	1			T1	21		T2	6		T3	90
valid_sources[0x5f]	31758	1			T1	11		T2	3		T3	48
valid_sources[0x60]	38258	1			T1	12		T2	2		T3	65
valid_sources[0x61]	28724	1			T1	13		T2	1		T3	42
valid_sources[0x62]	28168	1			T1	16		T2	3		T3	63
valid_sources[0x63]	27609	1			T1	1		T2	3		T3	49
valid_sources[0x64]	31735	1			T1	8		T2	6		T3	85
valid_sources[0x65]	29254	1			T1	2		T2	9		T3	23
valid_sources[0x66]	29007	1			T1	18		T2	4		T3	54
valid_sources[0x67]	27628	1			T1	8		T2	3		T3	31
valid_sources[0x68]	30645	1			T1	5		T2	1		T3	119
valid_sources[0x69]	26866	1			T1	6		T2	8		T3	158
valid_sources[0x6a]	33194	1			T1	3		T2	1		T3	43
valid_sources[0x6b]	30195	1			T1	11		T2	1		T3	49
valid_sources[0x6c]	33434	1			T1	23		T2	3		T3	17
valid_sources[0x6d]	28931	1			T2	2		T3	43		T5	2
valid_sources[0x6e]	28609	1			T1	6		T2	2		T3	35
valid_sources[0x6f]	26491	1			T1	6		T2	4		T3	35
valid_sources[0x70]	29368	1			T1	14		T2	7		T3	78
valid_sources[0x71]	28083	1			T1	13		T2	1		T3	36
valid_sources[0x72]	29424	1			T1	24		T2	7		T3	40
valid_sources[0x73]	33365	1			T1	8		T2	5		T3	62
valid_sources[0x74]	32925	1			T1	21		T2	5		T3	78
valid_sources[0x75]	29868	1			T1	6		T2	3		T3	34
valid_sources[0x76]	28727	1			T1	7		T2	6		T3	55
valid_sources[0x77]	28209	1			T1	7		T2	2		T3	51
valid_sources[0x78]	32330	1			T1	13		T2	5		T3	71
valid_sources[0x79]	28123	1			T2	5		T3	49		T5	3
valid_sources[0x7a]	80608	1			T1	20		T2	3		T3	39
valid_sources[0x7b]	28201	1			T1	5		T2	8		T3	26
valid_sources[0x7c]	29776	1			T1	12		T2	1		T3	37
valid_sources[0x7d]	29449	1			T1	2		T2	6		T3	72
valid_sources[0x7e]	32457	1			T1	6		T2	5		T3	61
valid_sources[0x7f]	28238	1			T1	6		T2	4		T3	36
valid_sources[0x80]	29789	1			T2	5		T3	59		T4	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1111717

1

T1

464

T2

25

T3

1326

values[0x0]

all_enables

biggest_size

1640997

1

T1

451

T2

424

T3

2205

values[0x1]

all_enables

biggest_size

1616953

1

T1

445

T2

450

T3

2079