Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3626935

1

T1

495

T2

37

T3

8901

full_word

4368806

1

T1

1360

T2

899

T3

5610

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7995261	1			T1	1855		T2	936		T3	14511
auto[TlIntgErrCmd]	148	1			T94	7		T96	10		T97	6
auto[TlIntgErrData]	166	1			T94	5		T96	9		T97	5
auto[TlIntgErrBoth]	166	1			T94	8		T96	11		T97	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4388571

1

T1

950

T2

58

T3

8817

auto[1]

3607170

1

T1

905

T2

878

T3

5694

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3276505	1			T1	486		T2	33		T3	7491
auto[TlIntgErrNone]	partial	auto[1]	349980	1			T1	9		T2	4		T3	1410
auto[TlIntgErrNone]	full_word	auto[0]	1111841	1			T1	464		T2	25		T3	1326
auto[TlIntgErrNone]	full_word	auto[1]	3256935	1			T1	896		T2	874		T3	4284
auto[TlIntgErrCmd]	partial	auto[0]	75	1			T94	4		T96	2		T97	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T94	3		T96	8		T97	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T150	1		T166	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T167	2		T164	1		T168	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T94	2		T96	3		T97	2
auto[TlIntgErrData]	partial	auto[1]	91	1			T94	3		T96	5		T97	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T114	1		T167	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T96	1		T150	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	74	1			T94	5		T96	6		T97	5
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T94	3		T96	5		T97	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T113	1		T116	1		T165	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T97	2		T112	1		T113	1