Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	2999926	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	2999926	0	0
T1	40743	1663	0	0
T2	10838	832	0	0
T3	680768	832	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	0	0	0
T8	296186	832	0	0
T9	11961	0	0	0
T10	350593	9985	0	0
T11	0	1665	0	0
T12	0	832	0	0
T13	0	17464	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	3250597	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	3250597	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	2469	0	0
T4	3624	832	0	0
T5	9135	2634	0	0
T6	4596	0	0	0
T7	24726	0	0	0
T8	296186	832	0	0
T9	11961	0	0	0
T10	350593	17751	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	10816	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	191638	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	191638	0	0
T3	680768	979	0	0
T4	3624	0	0	0
T5	9135	0	0	0
T6	4596	0	0	0
T7	24726	38	0	0
T8	296186	0	0	0
T9	11961	63	0	0
T10	350593	1055	0	0
T11	26073	0	0	0
T13	0	723	0	0
T22	31110	53	0	0
T24	0	367	0	0
T36	0	306	0	0
T37	0	257	0	0
T38	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	428422	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	428422	0	0
T3	680768	3041	0	0
T4	3624	0	0	0
T5	9135	0	0	0
T6	4596	0	0	0
T7	24726	38	0	0
T8	296186	0	0	0
T9	11961	63	0	0
T10	350593	3067	0	0
T11	26073	0	0	0
T13	0	723	0	0
T22	31110	53	0	0
T24	0	1149	0	0
T36	0	1357	0	0
T37	0	257	0	0
T38	0	120	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	6257621	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	6257621	0	0
T1	40743	1023	0	0
T2	10838	105	0	0
T3	680768	13190	0	0
T4	3624	95	0	0
T5	9135	47	0	0
T6	4596	32	0	0
T7	24726	1528	0	0
T8	296186	68	0	0
T9	11961	482	0	0
T10	350593	9419	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446504798	12057406	0	0
DepthKnown_A	446504798	446368310	0	0
RvalidKnown_A	446504798	446368310	0	0
WreadyKnown_A	446504798	446368310	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	12057406	0	0
T1	40743	1023	0	0
T2	10838	104	0	0
T3	680768	39075	0	0
T4	3624	95	0	0
T5	9135	135	0	0
T6	4596	32	0	0
T7	24726	1528	0	0
T8	296186	68	0	0
T9	11961	482	0	0
T10	350593	26883	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446504798	446368310	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0