Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T9
1	0	Covered	T3,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T13,T36

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T13,T36
1	0	Covered	T10,T13,T36

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T13,T36

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	749486712	595309325	0	0
CheckNGreaterZero_A	2922	2922	0	0
GntImpliesReady_A	749486712	3806733	0	0
GntImpliesValid_A	749486712	3806733	0	0
GrantKnown_A	749486712	595309325	0	0
IdxKnown_A	749486712	595309325	0	0
IndexIsCorrect_A	749486712	3806733	0	0
LockArbDecision_A	749486712	0	0	0
NoReadyValidNoGrant_A	749486712	0	0	0
ReadyAndValidImplyGrant_A	749486712	3806733	0	0
ReqAndReadyImplyGrant_A	749486712	3806733	0	0
ReqImpliesValid_A	749486712	3806733	0	0
ReqStaysHighUntilGranted0_M	749486712	0	0	0
RoundRobin_A	749486712	4	0	974
ValidKnown_A	749486712	595309325	0	0
gen_data_port_assertion.DataFlow_A	749486712	3806733	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	595309325	0	0
T1	115303	115209	0	0
T2	20538	20454	0	0
T3	1004290	836772	0	0
T4	11848	7682	0	0
T5	9167	9096	0	0
T6	6966	5230	0	0
T7	32562	28110	0	0
T8	411522	353721	0	0
T9	73273	42531	0	0
T10	606957	1624039	0	0
T11	57817	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2922	2922	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	595309325	0	0
T1	115303	115209	0	0
T2	20538	20454	0	0
T3	1004290	836772	0	0
T4	11848	7682	0	0
T5	9167	9096	0	0
T6	6966	5230	0	0
T7	32562	28110	0	0
T8	411522	353721	0	0
T9	73273	42531	0	0
T10	606957	1624039	0	0
T11	57817	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	595309325	0	0
T1	115303	115209	0	0
T2	20538	20454	0	0
T3	1004290	836772	0	0
T4	11848	7682	0	0
T5	9167	9096	0	0
T6	6966	5230	0	0
T7	32562	28110	0	0
T8	411522	353721	0	0
T9	73273	42531	0	0
T10	606957	1624039	0	0
T11	57817	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	4	0	974
T53	108804	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	11305	0	0	1
T58	511689	0	0	1
T59	160636	0	0	1
T60	6490	0	0	1
T61	375493	0	0	1
T62	1015	0	0	1
T63	13888	0	0	1
T64	108799	0	0	1
T65	12608	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	595309325	0	0
T1	115303	115209	0	0
T2	20538	20454	0	0
T3	1004290	836772	0	0
T4	11848	7682	0	0
T5	9167	9096	0	0
T6	6966	5230	0	0
T7	32562	28110	0	0
T8	411522	353721	0	0
T9	73273	42531	0	0
T10	606957	1624039	0	0
T11	57817	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	749486712	3806733	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	842529	9167	0	0
T4	7736	832	0	0
T5	9151	832	0	0
T6	5781	0	0	0
T7	28644	297	0	0
T8	353854	832	0	0
T9	42617	629	0	0
T10	606957	17284	0	0
T11	115634	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	27566	522	0	0
T23	35598	0	0	0
T24	49110	2029	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T38	0	113	0	0
T42	0	2934	0	0
T43	0	5184	0	0
T44	0	13	0	0
T50	0	1319	0	0
T51	0	6	0	0
T52	0	271	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T9
1	0	Covered	T3,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152700103	29254636	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	152700103	633511	0	0
GntImpliesValid_A	152700103	633511	0	0
GrantKnown_A	152700103	29254636	0	0
IdxKnown_A	152700103	29254636	0	0
IndexIsCorrect_A	152700103	633511	0	0
LockArbDecision_A	152700103	0	0	0
NoReadyValidNoGrant_A	152700103	0	0	0
ReadyAndValidImplyGrant_A	152700103	633511	0	0
ReqAndReadyImplyGrant_A	152700103	633511	0	0
ReqImpliesValid_A	152700103	633511	0	0
ReqStaysHighUntilGranted0_M	152700103	0	0	0
RoundRobin_A	152700103	0	0	0
ValidKnown_A	152700103	29254636	0	0
gen_data_port_assertion.DataFlow_A	152700103	633511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	29254636	0	0
T3	161761	131792	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	720	0	0
T7	3918	3456	0	0
T8	57668	0	0	0
T9	30656	30656	0	0
T10	128182	439000	0	0
T11	57817	0	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	29254636	0	0
T3	161761	131792	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	720	0	0
T7	3918	3456	0	0
T8	57668	0	0	0
T9	30656	30656	0	0
T10	128182	439000	0	0
T11	57817	0	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	29254636	0	0
T3	161761	131792	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	720	0	0
T7	3918	3456	0	0
T8	57668	0	0	0
T9	30656	30656	0	0
T10	128182	439000	0	0
T11	57817	0	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	29254636	0	0
T3	161761	131792	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	720	0	0
T7	3918	3456	0	0
T8	57668	0	0	0
T9	30656	30656	0	0
T10	128182	439000	0	0
T11	57817	0	0	0
T22	13783	13336	0	0
T23	0	35216	0	0
T24	0	47128	0	0
T28	0	864	0	0
T29	0	11704	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	633511	0	0
T3	161761	5654	0	0
T4	4112	0	0	0
T5	16	0	0	0
T6	1185	0	0	0
T7	3918	205	0	0
T8	57668	0	0	0
T9	30656	409	0	0
T10	128182	4371	0	0
T11	57817	0	0	0
T22	13783	341	0	0
T24	0	2029	0	0
T38	0	113	0	0
T42	0	1831	0	0
T43	0	440	0	0
T50	0	1319	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T13,T36

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T13,T36
1	0	Covered	T10,T13,T36

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T10,T13,T36

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T13,T36
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T36
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152700103	122053521	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	152700103	836781	0	0
GntImpliesValid_A	152700103	836781	0	0
GrantKnown_A	152700103	122053521	0	0
IdxKnown_A	152700103	122053521	0	0
IndexIsCorrect_A	152700103	836781	0	0
LockArbDecision_A	152700103	0	0	0
NoReadyValidNoGrant_A	152700103	0	0	0
ReadyAndValidImplyGrant_A	152700103	836781	0	0
ReqAndReadyImplyGrant_A	152700103	836781	0	0
ReqImpliesValid_A	152700103	836781	0	0
ReqStaysHighUntilGranted0_M	152700103	0	0	0
RoundRobin_A	152700103	0	0	0
ValidKnown_A	152700103	122053521	0	0
gen_data_port_assertion.DataFlow_A	152700103	836781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	122053521	0	0
T1	74560	74560	0	0
T2	9700	9700	0	0
T3	161761	24300	0	0
T4	4112	4112	0	0
T5	16	16	0	0
T6	1185	0	0	0
T7	3918	0	0	0
T8	57668	57588	0	0
T9	30656	0	0	0
T10	128182	834687	0	0
T11	0	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	122053521	0	0
T1	74560	74560	0	0
T2	9700	9700	0	0
T3	161761	24300	0	0
T4	4112	4112	0	0
T5	16	16	0	0
T6	1185	0	0	0
T7	3918	0	0	0
T8	57668	57588	0	0
T9	30656	0	0	0
T10	128182	834687	0	0
T11	0	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	122053521	0	0
T1	74560	74560	0	0
T2	9700	9700	0	0
T3	161761	24300	0	0
T4	4112	4112	0	0
T5	16	16	0	0
T6	1185	0	0	0
T7	3918	0	0	0
T8	57668	57588	0	0
T9	30656	0	0	0
T10	128182	834687	0	0
T11	0	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	122053521	0	0
T1	74560	74560	0	0
T2	9700	9700	0	0
T3	161761	24300	0	0
T4	4112	4112	0	0
T5	16	16	0	0
T6	1185	0	0	0
T7	3918	0	0	0
T8	57668	57588	0	0
T9	30656	0	0	0
T10	128182	834687	0	0
T11	0	57038	0	0
T12	0	14856	0	0
T13	0	101468	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152700103	836781	0	0
T10	128182	3123	0	0
T11	57817	0	0	0
T12	14856	0	0	0
T13	101878	12378	0	0
T22	13783	0	0	0
T23	35598	0	0	0
T24	49110	0	0	0
T25	36151	0	0	0
T26	143190	0	0	0
T27	12085	0	0	0
T36	0	4566	0	0
T37	0	3588	0	0
T42	0	1103	0	0
T43	0	4744	0	0
T44	0	13	0	0
T51	0	6	0	0
T52	0	271	0	0
T66	0	630	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444086506	444001168	0	0
CheckNGreaterZero_A	974	974	0	0
GntImpliesReady_A	444086506	2336441	0	0
GntImpliesValid_A	444086506	2336441	0	0
GrantKnown_A	444086506	444001168	0	0
IdxKnown_A	444086506	444001168	0	0
IndexIsCorrect_A	444086506	2336441	0	0
LockArbDecision_A	444086506	0	0	0
NoReadyValidNoGrant_A	444086506	0	0	0
ReadyAndValidImplyGrant_A	444086506	2336441	0	0
ReqAndReadyImplyGrant_A	444086506	2336441	0	0
ReqImpliesValid_A	444086506	2336441	0	0
ReqStaysHighUntilGranted0_M	444086506	0	0	0
RoundRobin_A	444086506	4	0	974
ValidKnown_A	444086506	444001168	0	0
gen_data_port_assertion.DataFlow_A	444086506	2336441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	444001168	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974	974	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	444001168	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	444001168	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	4	0	974
T53	108804	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	11305	0	0	1
T58	511689	0	0	1
T59	160636	0	0	1
T60	6490	0	0	1
T61	375493	0	0	1
T62	1015	0	0	1
T63	13888	0	0	1
T64	108799	0	0	1
T65	12608	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	444001168	0	0
T1	40743	40649	0	0
T2	10838	10754	0	0
T3	680768	680680	0	0
T4	3624	3570	0	0
T5	9135	9080	0	0
T6	4596	4510	0	0
T7	24726	24654	0	0
T8	296186	296133	0	0
T9	11961	11875	0	0
T10	350593	350352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444086506	2336441	0	0
T1	40743	832	0	0
T2	10838	832	0	0
T3	680768	3513	0	0
T4	3624	832	0	0
T5	9135	832	0	0
T6	4596	0	0	0
T7	24726	92	0	0
T8	296186	832	0	0
T9	11961	220	0	0
T10	350593	9790	0	0
T22	0	181	0	0