Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3652405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4273490

1

T1

9676

T2

9776

T3

2998

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4344461	1			T1	1313		T2	4796		T3	2549
values[0x0]	1789530	1			T1	4681		T2	4496		T3	1405
values[0x1]	1791904	1			T1	4576		T2	4619		T3	1454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2585579	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5340316

1

T1

9929

T2

10943

T3

3697

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29128	1			T1	1		T3	21		T4	46
valid_sources[0x01]	29898	1			T2	22		T3	27		T4	32
valid_sources[0x02]	31341	1			T2	1		T3	12		T4	22
valid_sources[0x03]	30446	1			T2	314		T3	18		T4	26
valid_sources[0x04]	27640	1			T2	133		T3	10		T4	34
valid_sources[0x05]	33319	1			T2	2		T3	33		T4	26
valid_sources[0x06]	30614	1			T1	1		T2	18		T3	17
valid_sources[0x07]	30753	1			T2	113		T3	24		T4	22
valid_sources[0x08]	31949	1			T1	30		T2	4		T3	18
valid_sources[0x09]	32321	1			T2	35		T3	15		T4	37
valid_sources[0x0a]	28027	1			T1	416		T2	128		T3	22
valid_sources[0x0b]	33013	1			T2	87		T3	14		T4	38
valid_sources[0x0c]	31608	1			T1	44		T2	214		T3	31
valid_sources[0x0d]	27779	1			T3	21		T4	36		T7	72
valid_sources[0x0e]	34592	1			T3	13		T4	27		T7	46
valid_sources[0x0f]	45640	1			T2	234		T3	22		T4	34
valid_sources[0x10]	30918	1			T3	10		T4	30		T7	47
valid_sources[0x11]	32412	1			T2	71		T3	22		T4	21
valid_sources[0x12]	27992	1			T2	1		T3	21		T4	43
valid_sources[0x13]	29388	1			T2	1		T3	13		T4	36
valid_sources[0x14]	27537	1			T2	1		T3	25		T4	23
valid_sources[0x15]	29326	1			T3	18		T4	25		T7	98
valid_sources[0x16]	29842	1			T2	11		T3	9		T4	34
valid_sources[0x17]	30656	1			T2	1		T3	24		T4	26
valid_sources[0x18]	28748	1			T1	48		T2	1		T3	46
valid_sources[0x19]	35647	1			T2	87		T3	6		T4	39
valid_sources[0x1a]	35167	1			T1	1		T2	151		T3	20
valid_sources[0x1b]	28548	1			T2	56		T3	24		T4	30
valid_sources[0x1c]	30335	1			T2	2		T3	16		T4	28
valid_sources[0x1d]	29680	1			T2	147		T3	34		T4	22
valid_sources[0x1e]	34383	1			T2	10		T3	22		T4	43
valid_sources[0x1f]	27441	1			T3	19		T4	23		T7	59
valid_sources[0x20]	30319	1			T1	1		T2	15		T3	18
valid_sources[0x21]	31255	1			T2	98		T3	19		T4	29
valid_sources[0x22]	30151	1			T2	1		T3	7		T4	34
valid_sources[0x23]	31627	1			T1	970		T3	27		T4	24
valid_sources[0x24]	44983	1			T1	1		T2	4		T3	16
valid_sources[0x25]	27588	1			T2	2		T3	21		T4	34
valid_sources[0x26]	32326	1			T2	1		T3	17		T4	33
valid_sources[0x27]	29633	1			T2	12		T3	22		T4	34
valid_sources[0x28]	28931	1			T2	2		T3	13		T4	40
valid_sources[0x29]	31954	1			T2	358		T3	14		T4	40
valid_sources[0x2a]	29491	1			T3	25		T4	30		T7	73
valid_sources[0x2b]	29515	1			T1	1		T3	37		T4	26
valid_sources[0x2c]	31088	1			T2	1		T3	8		T4	23
valid_sources[0x2d]	30714	1			T2	52		T3	17		T4	19
valid_sources[0x2e]	28506	1			T2	25		T3	34		T4	39
valid_sources[0x2f]	33068	1			T1	1890		T2	21		T3	28
valid_sources[0x30]	29520	1			T2	5		T3	10		T4	25
valid_sources[0x31]	30930	1			T3	4		T4	28		T7	52
valid_sources[0x32]	27756	1			T2	74		T3	36		T4	35
valid_sources[0x33]	30266	1			T3	27		T4	42		T7	63
valid_sources[0x34]	29721	1			T2	3		T3	23		T4	35
valid_sources[0x35]	29263	1			T2	179		T3	12		T4	26
valid_sources[0x36]	35500	1			T1	1		T2	21		T3	33
valid_sources[0x37]	29593	1			T2	1		T3	32		T4	29
valid_sources[0x38]	32348	1			T1	1		T2	29		T3	8
valid_sources[0x39]	29134	1			T2	3		T3	9		T4	39
valid_sources[0x3a]	28997	1			T2	73		T3	20		T4	15
valid_sources[0x3b]	31720	1			T3	18		T4	32		T7	75
valid_sources[0x3c]	29884	1			T2	30		T3	23		T4	30
valid_sources[0x3d]	32101	1			T2	1		T3	15		T4	30
valid_sources[0x3e]	31482	1			T2	12		T3	29		T4	43
valid_sources[0x3f]	28399	1			T2	251		T3	9		T4	31
valid_sources[0x40]	31116	1			T2	9		T3	45		T4	25
valid_sources[0x41]	28917	1			T2	42		T3	21		T4	54
valid_sources[0x42]	32695	1			T1	582		T2	67		T3	17
valid_sources[0x43]	32629	1			T1	23		T2	1		T3	32
valid_sources[0x44]	28041	1			T3	17		T4	28		T7	60
valid_sources[0x45]	31565	1			T1	28		T2	472		T3	31
valid_sources[0x46]	29539	1			T1	416		T2	3		T3	16
valid_sources[0x47]	30541	1			T2	72		T3	23		T4	31
valid_sources[0x48]	30411	1			T2	1		T3	12		T4	31
valid_sources[0x49]	27365	1			T2	7		T3	2		T4	30
valid_sources[0x4a]	31193	1			T1	1		T2	42		T3	41
valid_sources[0x4b]	37217	1			T1	416		T2	6		T3	45
valid_sources[0x4c]	29499	1			T2	2		T3	21		T4	29
valid_sources[0x4d]	28752	1			T2	303		T3	33		T4	33
valid_sources[0x4e]	37144	1			T2	111		T3	37		T4	37
valid_sources[0x4f]	31158	1			T1	1		T2	94		T3	16
valid_sources[0x50]	30402	1			T1	59		T3	9		T4	30
valid_sources[0x51]	33661	1			T1	2		T2	36		T3	18
valid_sources[0x52]	32733	1			T2	27		T3	27		T4	21
valid_sources[0x53]	30749	1			T2	71		T3	9		T4	25
valid_sources[0x54]	28764	1			T2	209		T3	13		T4	43
valid_sources[0x55]	28358	1			T2	8		T3	18		T4	26
valid_sources[0x56]	28854	1			T3	7		T4	35		T7	79
valid_sources[0x57]	28775	1			T2	14		T3	18		T4	35
valid_sources[0x58]	32402	1			T2	41		T3	18		T4	47
valid_sources[0x59]	32689	1			T2	5		T3	22		T4	34
valid_sources[0x5a]	28507	1			T1	11		T2	59		T3	39
valid_sources[0x5b]	37477	1			T1	16		T2	42		T3	16
valid_sources[0x5c]	32520	1			T2	87		T3	25		T4	21
valid_sources[0x5d]	30075	1			T1	1		T3	26		T4	18
valid_sources[0x5e]	28368	1			T1	2		T2	21		T3	23
valid_sources[0x5f]	28178	1			T2	2		T3	22		T4	30
valid_sources[0x60]	30053	1			T2	12		T3	34		T4	34
valid_sources[0x61]	28204	1			T2	1		T3	49		T4	40
valid_sources[0x62]	28239	1			T2	5		T3	6		T4	32
valid_sources[0x63]	29312	1			T2	10		T3	17		T4	32
valid_sources[0x64]	30027	1			T1	1		T2	57		T3	32
valid_sources[0x65]	32575	1			T2	1		T3	24		T4	26
valid_sources[0x66]	29352	1			T1	463		T2	1		T3	22
valid_sources[0x67]	29002	1			T1	1		T2	2		T3	18
valid_sources[0x68]	29843	1			T2	57		T3	25		T4	28
valid_sources[0x69]	31795	1			T3	25		T4	36		T7	85
valid_sources[0x6a]	28286	1			T3	22		T4	37		T7	116
valid_sources[0x6b]	30489	1			T2	44		T3	17		T4	28
valid_sources[0x6c]	29232	1			T3	31		T4	34		T7	54
valid_sources[0x6d]	33538	1			T3	23		T4	38		T7	67
valid_sources[0x6e]	33586	1			T3	18		T4	42		T7	77
valid_sources[0x6f]	28243	1			T2	2		T3	30		T4	20
valid_sources[0x70]	39814	1			T3	10		T4	33		T7	59
valid_sources[0x71]	31743	1			T3	26		T4	19		T7	130
valid_sources[0x72]	33280	1			T2	78		T3	46		T4	48
valid_sources[0x73]	35969	1			T2	6		T3	10		T4	30
valid_sources[0x74]	36578	1			T2	126		T3	7		T4	33
valid_sources[0x75]	30149	1			T2	140		T3	24		T4	30
valid_sources[0x76]	29420	1			T2	1		T3	12		T4	30
valid_sources[0x77]	30191	1			T1	9		T2	2		T3	10
valid_sources[0x78]	32783	1			T3	33		T4	28		T7	62
valid_sources[0x79]	30337	1			T2	1		T3	36		T4	41
valid_sources[0x7a]	29131	1			T2	46		T3	31		T4	33
valid_sources[0x7b]	26759	1			T1	1		T2	2		T3	13
valid_sources[0x7c]	29138	1			T2	1		T3	10		T4	38
valid_sources[0x7d]	32643	1			T3	11		T4	38		T7	73
valid_sources[0x7e]	29003	1			T2	4		T3	17		T4	37
valid_sources[0x7f]	29147	1			T2	3		T3	18		T4	26
valid_sources[0x80]	29569	1			T1	832		T2	86		T3	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1033903

1

T1

551

T2

1675

T3

819

values[0x0]

all_enables

biggest_size

1631483

1

T1

4622

T2

4051

T3

1078

values[0x1]

all_enables

biggest_size

1608104

1

T1

4503

T2

4050

T3

1101