Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3671125

1

T1

894

T2

4135

T3

2410

full_word

4272461

1

T1

9676

T2

9776

T3

2998

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7943176	1			T1	10570		T2	13911		T3	5408
auto[TlIntgErrCmd]	137	1			T77	8		T78	9		T82	7
auto[TlIntgErrData]	146	1			T77	6		T78	12		T82	6
auto[TlIntgErrBoth]	127	1			T77	6		T78	9		T82	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4346119

1

T1

1313

T2

4796

T3

2549

auto[1]

3597467

1

T1

9257

T2

9115

T3

2859

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3311925	1			T1	762		T2	3121		T3	1730
auto[TlIntgErrNone]	partial	auto[1]	358829	1			T1	132		T2	1014		T3	680
auto[TlIntgErrNone]	full_word	auto[0]	1033979	1			T1	551		T2	1675		T3	819
auto[TlIntgErrNone]	full_word	auto[1]	3238443	1			T1	9125		T2	8101		T3	2179
auto[TlIntgErrCmd]	partial	auto[0]	66	1			T77	4		T78	5		T82	6
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T77	4		T78	3		T82	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T78	1		T133	1		T150	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T133	1		T151	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	77	1			T77	1		T78	6		T82	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T77	5		T78	5		T82	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T78	1		T149	2		T131	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T130	2		T149	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T77	2		T78	4		T82	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T77	3		T78	5		T82	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T130	1		T153	1		T154	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T77	1		T82	2		T149	2