Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	2902562	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	2902562	0	0
T1	250840	14995	0	0
T2	316743	4992	0	0
T3	123810	0	0	0
T4	504879	0	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	13307	0	0
T8	8204	832	0	0
T9	179236	4990	0	0
T10	101527	7484	0	0
T12	0	4997	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	3228403	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	3228403	0	0
T1	250840	14197	0	0
T2	316743	15490	0	0
T3	123810	0	0	0
T4	504879	0	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9152	0	0
T8	8204	832	0	0
T9	179236	3328	0	0
T10	101527	4160	0	0
T12	0	11094	0	0
T13	0	3583	0	0
T14	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	194964	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	194964	0	0
T1	250840	313	0	0
T2	316743	1291	0	0
T3	123810	636	0	0
T4	504879	400	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	704	0	0
T8	8204	0	0	0
T9	179236	192	0	0
T10	101527	302	0	0
T12	0	96	0	0
T24	0	687	0	0
T30	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	450908	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	450908	0	0
T1	250840	1376	0	0
T2	316743	3964	0	0
T3	123810	2732	0	0
T4	504879	1805	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	704	0	0
T8	8204	0	0	0
T9	179236	192	0	0
T10	101527	302	0	0
T12	0	344	0	0
T24	0	687	0	0
T30	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	6250893	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	6250893	0	0
T1	250840	2175	0	0
T2	316743	8179	0	0
T3	123810	5222	0	0
T4	504879	7942	0	0
T5	1092	13	0	0
T6	5603	26	0	0
T7	582194	8783	0	0
T8	8204	338	0	0
T9	179236	2818	0	0
T10	101527	6678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	441738623	12391795	0	0
DepthKnown_A	441738623	441601269	0	0
RvalidKnown_A	441738623	441601269	0	0
WreadyKnown_A	441738623	441601269	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	12391795	0	0
T1	250840	8476	0	0
T2	316743	23613	0	0
T3	123810	21170	0	0
T4	504879	34028	0	0
T5	1092	46	0	0
T6	5603	26	0	0
T7	582194	8782	0	0
T8	8204	338	0	0
T9	179236	2816	0	0
T10	101527	6639	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441738623	441601269	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0