Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	737978790	587086658	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	737978790	3871008	0	0
GntImpliesValid_A	737978790	3871008	0	0
GrantKnown_A	737978790	587086658	0	0
IdxKnown_A	737978790	587086658	0	0
IndexIsCorrect_A	737978790	3871008	0	0
LockArbDecision_A	737978790	0	0	0
NoReadyValidNoGrant_A	737978790	0	0	0
ReadyAndValidImplyGrant_A	737978790	3871008	0	0
ReqAndReadyImplyGrant_A	737978790	3871008	0	0
ReqImpliesValid_A	737978790	3871008	0	0
ReqStaysHighUntilGranted0_M	737978790	0	0	0
RoundRobin_A	737978790	4	0	976
ValidKnown_A	737978790	587086658	0	0
gen_data_port_assertion.DataFlow_A	737978790	3871008	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	587086658	0	0
T1	1014222	627819	0	0
T2	1453211	878605	0	0
T3	938074	526939	0	0
T4	633323	566533	0	0
T5	1092	992	0	0
T6	6755	6108	0	0
T7	2226702	1401001	0	0
T8	49992	29032	0	0
T9	685506	432036	0	0
T10	501167	300308	0	0
T11	1152	576	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	587086658	0	0
T1	1014222	627819	0	0
T2	1453211	878605	0	0
T3	938074	526939	0	0
T4	633323	566533	0	0
T5	1092	992	0	0
T6	6755	6108	0	0
T7	2226702	1401001	0	0
T8	49992	29032	0	0
T9	685506	432036	0	0
T10	501167	300308	0	0
T11	1152	576	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	587086658	0	0
T1	1014222	627819	0	0
T2	1453211	878605	0	0
T3	938074	526939	0	0
T4	633323	566533	0	0
T5	1092	992	0	0
T6	6755	6108	0	0
T7	2226702	1401001	0	0
T8	49992	29032	0	0
T9	685506	432036	0	0
T10	501167	300308	0	0
T11	1152	576	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	4	0	976
T2	316743	1	0	1
T3	123810	0	0	1
T4	504879	0	0	1
T5	1092	0	0	1
T6	5603	0	0	1
T7	582194	0	0	1
T8	8204	0	0	1
T9	179236	0	0	1
T10	101527	0	0	1
T11	2264	0	0	1
T24	0	1	0	0
T33	0	1	0	0
T45	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	587086658	0	0
T1	1014222	627819	0	0
T2	1453211	878605	0	0
T3	938074	526939	0	0
T4	633323	566533	0	0
T5	1092	992	0	0
T6	6755	6108	0	0
T7	2226702	1401001	0	0
T8	49992	29032	0	0
T9	685506	432036	0	0
T10	501167	300308	0	0
T11	1152	576	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737978790	3871008	0	0
T1	1014222	10584	0	0
T2	1453211	17741	0	0
T3	938074	6177	0	0
T4	633323	4018	0	0
T5	1092	0	0	0
T6	6755	0	0	0
T7	2226702	23308	0	0
T8	49992	832	0	0
T9	685506	4316	0	0
T10	501167	8916	0	0
T11	1152	0	0	0
T12	0	5200	0	0
T13	0	832	0	0
T24	0	3529	0	0
T37	0	5196	0	0
T41	0	11386	0	0
T42	0	4102	0	0
T43	0	157	0	0
T44	0	64	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149371259	28779366	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	149371259	654916	0	0
GntImpliesValid_A	149371259	654916	0	0
GrantKnown_A	149371259	28779366	0	0
IdxKnown_A	149371259	28779366	0	0
IndexIsCorrect_A	149371259	654916	0	0
LockArbDecision_A	149371259	0	0	0
NoReadyValidNoGrant_A	149371259	0	0	0
ReadyAndValidImplyGrant_A	149371259	654916	0	0
ReqAndReadyImplyGrant_A	149371259	654916	0	0
ReqImpliesValid_A	149371259	654916	0	0
ReqStaysHighUntilGranted0_M	149371259	0	0	0
RoundRobin_A	149371259	0	0	0
ValidKnown_A	149371259	28779366	0	0
gen_data_port_assertion.DataFlow_A	149371259	654916	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	28779366	0	0
T1	381691	36460	0	0
T2	568234	309448	0	0
T3	407132	403432	0	0
T4	64222	61720	0	0
T6	576	576	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	7336	0	0
T11	576	576	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	28779366	0	0
T1	381691	36460	0	0
T2	568234	309448	0	0
T3	407132	403432	0	0
T4	64222	61720	0	0
T6	576	576	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	7336	0	0
T11	576	576	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	28779366	0	0
T1	381691	36460	0	0
T2	568234	309448	0	0
T3	407132	403432	0	0
T4	64222	61720	0	0
T6	576	576	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	7336	0	0
T11	576	576	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	28779366	0	0
T1	381691	36460	0	0
T2	568234	309448	0	0
T3	407132	403432	0	0
T4	64222	61720	0	0
T6	576	576	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	7336	0	0
T11	576	576	0	0
T23	0	144	0	0
T24	0	49744	0	0
T25	0	792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	654916	0	0
T1	381691	352	0	0
T2	568234	5523	0	0
T3	407132	4070	0	0
T4	64222	2636	0	0
T6	576	0	0	0
T7	822254	0	0	0
T8	20894	0	0	0
T9	253135	0	0	0
T10	199820	301	0	0
T11	576	0	0	0
T24	0	2363	0	0
T37	0	662	0	0
T41	0	5059	0	0
T42	0	4102	0	0
T43	0	157	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149371259	119162475	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	149371259	929946	0	0
GntImpliesValid_A	149371259	929946	0	0
GrantKnown_A	149371259	119162475	0	0
IdxKnown_A	149371259	119162475	0	0
IndexIsCorrect_A	149371259	929946	0	0
LockArbDecision_A	149371259	0	0	0
NoReadyValidNoGrant_A	149371259	0	0	0
ReadyAndValidImplyGrant_A	149371259	929946	0	0
ReqAndReadyImplyGrant_A	149371259	929946	0	0
ReqImpliesValid_A	149371259	929946	0	0
ReqStaysHighUntilGranted0_M	149371259	0	0	0
RoundRobin_A	149371259	0	0	0
ValidKnown_A	149371259	119162475	0	0
gen_data_port_assertion.DataFlow_A	149371259	929946	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	119162475	0	0
T1	381691	340588	0	0
T2	568234	252699	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	818813	0	0
T8	20894	20894	0	0
T9	253135	252807	0	0
T10	199820	191452	0	0
T11	576	0	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	119162475	0	0
T1	381691	340588	0	0
T2	568234	252699	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	818813	0	0
T8	20894	20894	0	0
T9	253135	252807	0	0
T10	199820	191452	0	0
T11	576	0	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	119162475	0	0
T1	381691	340588	0	0
T2	568234	252699	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	818813	0	0
T8	20894	20894	0	0
T9	253135	252807	0	0
T10	199820	191452	0	0
T11	576	0	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	119162475	0	0
T1	381691	340588	0	0
T2	568234	252699	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	818813	0	0
T8	20894	20894	0	0
T9	253135	252807	0	0
T10	199820	191452	0	0
T11	576	0	0	0
T12	0	136938	0	0
T13	0	8358	0	0
T14	0	126508	0	0
T15	0	7792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149371259	929946	0	0
T1	381691	1394	0	0
T2	568234	4234	0	0
T3	407132	0	0	0
T4	64222	0	0	0
T6	576	0	0	0
T7	822254	13430	0	0
T8	20894	0	0	0
T9	253135	782	0	0
T10	199820	4027	0	0
T11	576	0	0	0
T12	0	937	0	0
T24	0	1166	0	0
T37	0	4534	0	0
T41	0	6327	0	0
T44	0	64	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439236272	439144817	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	439236272	2286146	0	0
GntImpliesValid_A	439236272	2286146	0	0
GrantKnown_A	439236272	439144817	0	0
IdxKnown_A	439236272	439144817	0	0
IndexIsCorrect_A	439236272	2286146	0	0
LockArbDecision_A	439236272	0	0	0
NoReadyValidNoGrant_A	439236272	0	0	0
ReadyAndValidImplyGrant_A	439236272	2286146	0	0
ReqAndReadyImplyGrant_A	439236272	2286146	0	0
ReqImpliesValid_A	439236272	2286146	0	0
ReqStaysHighUntilGranted0_M	439236272	0	0	0
RoundRobin_A	439236272	4	0	976
ValidKnown_A	439236272	439144817	0	0
gen_data_port_assertion.DataFlow_A	439236272	2286146	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	439144817	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	439144817	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	439144817	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	4	0	976
T2	316743	1	0	1
T3	123810	0	0	1
T4	504879	0	0	1
T5	1092	0	0	1
T6	5603	0	0	1
T7	582194	0	0	1
T8	8204	0	0	1
T9	179236	0	0	1
T10	101527	0	0	1
T11	2264	0	0	1
T24	0	1	0	0
T33	0	1	0	0
T45	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	439144817	0	0
T1	250840	250771	0	0
T2	316743	316458	0	0
T3	123810	123507	0	0
T4	504879	504813	0	0
T5	1092	992	0	0
T6	5603	5532	0	0
T7	582194	582188	0	0
T8	8204	8138	0	0
T9	179236	179229	0	0
T10	101527	101520	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439236272	2286146	0	0
T1	250840	8838	0	0
T2	316743	7984	0	0
T3	123810	2107	0	0
T4	504879	1382	0	0
T5	1092	0	0	0
T6	5603	0	0	0
T7	582194	9878	0	0
T8	8204	832	0	0
T9	179236	3534	0	0
T10	101527	4588	0	0
T12	0	4263	0	0
T13	0	832	0	0