Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
3639 |
0 |
0 |
T77 |
57424 |
4 |
0 |
0 |
T78 |
30162 |
3 |
0 |
0 |
T79 |
5017 |
2 |
0 |
0 |
T80 |
12680 |
9 |
0 |
0 |
T81 |
9332 |
174 |
0 |
0 |
T82 |
53664 |
4 |
0 |
0 |
T83 |
9535 |
73 |
0 |
0 |
T84 |
4926 |
68 |
0 |
0 |
T85 |
2660 |
91 |
0 |
0 |
T93 |
2852 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1500 |
0 |
0 |
T90 |
14641 |
30 |
0 |
0 |
T107 |
3551 |
10 |
0 |
0 |
T108 |
74518 |
577 |
0 |
0 |
T130 |
109490 |
131 |
0 |
0 |
T131 |
106133 |
107 |
0 |
0 |
T132 |
64391 |
82 |
0 |
0 |
T133 |
93678 |
59 |
0 |
0 |
T134 |
6996 |
8 |
0 |
0 |
T135 |
20360 |
57 |
0 |
0 |
T136 |
15455 |
27 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1510 |
0 |
0 |
T90 |
14641 |
22 |
0 |
0 |
T107 |
3551 |
2 |
0 |
0 |
T108 |
74518 |
550 |
0 |
0 |
T123 |
18418 |
57 |
0 |
0 |
T130 |
109490 |
90 |
0 |
0 |
T131 |
106133 |
116 |
0 |
0 |
T132 |
64391 |
78 |
0 |
0 |
T133 |
93678 |
73 |
0 |
0 |
T134 |
6996 |
13 |
0 |
0 |
T137 |
4086 |
9 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
2155 |
0 |
0 |
T90 |
14641 |
35 |
0 |
0 |
T107 |
3551 |
6 |
0 |
0 |
T108 |
74518 |
516 |
0 |
0 |
T123 |
18418 |
25 |
0 |
0 |
T130 |
109490 |
171 |
0 |
0 |
T131 |
106133 |
238 |
0 |
0 |
T132 |
64391 |
141 |
0 |
0 |
T133 |
93678 |
111 |
0 |
0 |
T134 |
6996 |
20 |
0 |
0 |
T137 |
4086 |
13 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
13661 |
0 |
0 |
T90 |
14641 |
152 |
0 |
0 |
T107 |
3551 |
8 |
0 |
0 |
T108 |
74518 |
524 |
0 |
0 |
T123 |
18418 |
38 |
0 |
0 |
T130 |
109490 |
2428 |
0 |
0 |
T131 |
106133 |
2201 |
0 |
0 |
T132 |
64391 |
1373 |
0 |
0 |
T133 |
93678 |
1143 |
0 |
0 |
T134 |
6996 |
221 |
0 |
0 |
T137 |
4086 |
117 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
11060 |
0 |
0 |
T90 |
14641 |
153 |
0 |
0 |
T108 |
74518 |
462 |
0 |
0 |
T123 |
18418 |
41 |
0 |
0 |
T130 |
109490 |
1478 |
0 |
0 |
T131 |
106133 |
1451 |
0 |
0 |
T132 |
64391 |
1238 |
0 |
0 |
T133 |
93678 |
1112 |
0 |
0 |
T134 |
6996 |
128 |
0 |
0 |
T135 |
20360 |
73 |
0 |
0 |
T136 |
15455 |
152 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
13355 |
0 |
0 |
T90 |
14641 |
379 |
0 |
0 |
T107 |
3551 |
102 |
0 |
0 |
T108 |
74518 |
530 |
0 |
0 |
T123 |
18418 |
44 |
0 |
0 |
T130 |
109490 |
2231 |
0 |
0 |
T131 |
106133 |
1903 |
0 |
0 |
T132 |
64391 |
1364 |
0 |
0 |
T133 |
93678 |
873 |
0 |
0 |
T134 |
6996 |
111 |
0 |
0 |
T137 |
4086 |
125 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
12422 |
0 |
0 |
T90 |
14641 |
161 |
0 |
0 |
T107 |
3551 |
3 |
0 |
0 |
T108 |
74518 |
472 |
0 |
0 |
T123 |
18418 |
35 |
0 |
0 |
T130 |
109490 |
1784 |
0 |
0 |
T131 |
106133 |
1795 |
0 |
0 |
T132 |
64391 |
1075 |
0 |
0 |
T133 |
93678 |
1143 |
0 |
0 |
T134 |
6996 |
8 |
0 |
0 |
T137 |
4086 |
8 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
12462 |
0 |
0 |
T90 |
14641 |
149 |
0 |
0 |
T107 |
3551 |
104 |
0 |
0 |
T108 |
74518 |
482 |
0 |
0 |
T123 |
18418 |
42 |
0 |
0 |
T130 |
109490 |
1547 |
0 |
0 |
T131 |
106133 |
1515 |
0 |
0 |
T132 |
64391 |
1431 |
0 |
0 |
T133 |
93678 |
1220 |
0 |
0 |
T134 |
6996 |
146 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
13181 |
0 |
0 |
T90 |
14641 |
17 |
0 |
0 |
T107 |
3551 |
8 |
0 |
0 |
T108 |
74518 |
517 |
0 |
0 |
T123 |
18418 |
60 |
0 |
0 |
T130 |
109490 |
2104 |
0 |
0 |
T131 |
106133 |
1913 |
0 |
0 |
T132 |
64391 |
1223 |
0 |
0 |
T133 |
93678 |
971 |
0 |
0 |
T134 |
6996 |
284 |
0 |
0 |
T137 |
4086 |
10 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
12499 |
0 |
0 |
T90 |
14641 |
235 |
0 |
0 |
T107 |
3551 |
1 |
0 |
0 |
T108 |
74518 |
463 |
0 |
0 |
T123 |
18418 |
16 |
0 |
0 |
T130 |
109490 |
2200 |
0 |
0 |
T131 |
106133 |
2479 |
0 |
0 |
T132 |
64391 |
1351 |
0 |
0 |
T133 |
93678 |
638 |
0 |
0 |
T134 |
6996 |
10 |
0 |
0 |
T137 |
4086 |
95 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
12446 |
0 |
0 |
T90 |
14641 |
122 |
0 |
0 |
T107 |
3551 |
105 |
0 |
0 |
T108 |
74518 |
459 |
0 |
0 |
T123 |
18418 |
20 |
0 |
0 |
T130 |
109490 |
2069 |
0 |
0 |
T131 |
106133 |
2422 |
0 |
0 |
T132 |
64391 |
1188 |
0 |
0 |
T133 |
93678 |
519 |
0 |
0 |
T134 |
6996 |
101 |
0 |
0 |
T137 |
4086 |
2 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
4837 |
0 |
0 |
T90 |
14641 |
61 |
0 |
0 |
T107 |
3551 |
2 |
0 |
0 |
T108 |
74518 |
526 |
0 |
0 |
T123 |
18418 |
32 |
0 |
0 |
T130 |
109490 |
463 |
0 |
0 |
T131 |
106133 |
797 |
0 |
0 |
T132 |
64391 |
453 |
0 |
0 |
T133 |
93678 |
507 |
0 |
0 |
T134 |
6996 |
79 |
0 |
0 |
T137 |
4086 |
2 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5438 |
0 |
0 |
T90 |
14641 |
123 |
0 |
0 |
T107 |
3551 |
3 |
0 |
0 |
T108 |
74518 |
469 |
0 |
0 |
T123 |
18418 |
8 |
0 |
0 |
T130 |
109490 |
822 |
0 |
0 |
T131 |
106133 |
729 |
0 |
0 |
T132 |
64391 |
443 |
0 |
0 |
T133 |
93678 |
394 |
0 |
0 |
T134 |
6996 |
99 |
0 |
0 |
T137 |
4086 |
60 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
6206 |
0 |
0 |
T83 |
9535 |
4 |
0 |
0 |
T90 |
14641 |
120 |
0 |
0 |
T107 |
3551 |
43 |
0 |
0 |
T108 |
74518 |
524 |
0 |
0 |
T123 |
18418 |
39 |
0 |
0 |
T130 |
109490 |
939 |
0 |
0 |
T131 |
106133 |
1045 |
0 |
0 |
T132 |
64391 |
451 |
0 |
0 |
T133 |
93678 |
564 |
0 |
0 |
T137 |
4086 |
47 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5638 |
0 |
0 |
T90 |
14641 |
31 |
0 |
0 |
T107 |
3551 |
3 |
0 |
0 |
T108 |
74518 |
499 |
0 |
0 |
T123 |
18418 |
27 |
0 |
0 |
T130 |
109490 |
901 |
0 |
0 |
T131 |
106133 |
766 |
0 |
0 |
T132 |
64391 |
620 |
0 |
0 |
T133 |
93678 |
385 |
0 |
0 |
T134 |
6996 |
63 |
0 |
0 |
T137 |
4086 |
8 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5143 |
0 |
0 |
T90 |
14641 |
94 |
0 |
0 |
T108 |
74518 |
503 |
0 |
0 |
T123 |
18418 |
24 |
0 |
0 |
T130 |
109490 |
637 |
0 |
0 |
T131 |
106133 |
598 |
0 |
0 |
T132 |
64391 |
306 |
0 |
0 |
T133 |
93678 |
429 |
0 |
0 |
T134 |
6996 |
11 |
0 |
0 |
T135 |
20360 |
56 |
0 |
0 |
T137 |
4086 |
1 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5400 |
0 |
0 |
T90 |
14641 |
77 |
0 |
0 |
T107 |
3551 |
4 |
0 |
0 |
T108 |
74518 |
465 |
0 |
0 |
T123 |
18418 |
36 |
0 |
0 |
T130 |
109490 |
657 |
0 |
0 |
T131 |
106133 |
751 |
0 |
0 |
T132 |
64391 |
489 |
0 |
0 |
T133 |
93678 |
389 |
0 |
0 |
T134 |
6996 |
11 |
0 |
0 |
T137 |
4086 |
58 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5159 |
0 |
0 |
T90 |
14641 |
85 |
0 |
0 |
T107 |
3551 |
8 |
0 |
0 |
T108 |
74518 |
508 |
0 |
0 |
T123 |
18418 |
5 |
0 |
0 |
T130 |
109490 |
801 |
0 |
0 |
T131 |
106133 |
563 |
0 |
0 |
T132 |
64391 |
432 |
0 |
0 |
T133 |
93678 |
364 |
0 |
0 |
T134 |
6996 |
42 |
0 |
0 |
T137 |
4086 |
7 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5485 |
0 |
0 |
T90 |
14641 |
74 |
0 |
0 |
T107 |
3551 |
40 |
0 |
0 |
T108 |
74518 |
519 |
0 |
0 |
T123 |
18418 |
54 |
0 |
0 |
T130 |
109490 |
648 |
0 |
0 |
T131 |
106133 |
687 |
0 |
0 |
T132 |
64391 |
428 |
0 |
0 |
T133 |
93678 |
463 |
0 |
0 |
T134 |
6996 |
45 |
0 |
0 |
T137 |
4086 |
51 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5583 |
0 |
0 |
T90 |
14641 |
56 |
0 |
0 |
T107 |
3551 |
5 |
0 |
0 |
T108 |
74518 |
505 |
0 |
0 |
T123 |
18418 |
39 |
0 |
0 |
T130 |
109490 |
790 |
0 |
0 |
T131 |
106133 |
684 |
0 |
0 |
T132 |
64391 |
334 |
0 |
0 |
T133 |
93678 |
403 |
0 |
0 |
T134 |
6996 |
54 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5284 |
0 |
0 |
T90 |
14641 |
153 |
0 |
0 |
T107 |
3551 |
44 |
0 |
0 |
T108 |
74518 |
473 |
0 |
0 |
T123 |
18418 |
40 |
0 |
0 |
T130 |
109490 |
814 |
0 |
0 |
T131 |
106133 |
629 |
0 |
0 |
T132 |
64391 |
407 |
0 |
0 |
T133 |
93678 |
301 |
0 |
0 |
T134 |
6996 |
45 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5292 |
0 |
0 |
T90 |
14641 |
79 |
0 |
0 |
T107 |
3551 |
5 |
0 |
0 |
T108 |
74518 |
487 |
0 |
0 |
T123 |
18418 |
16 |
0 |
0 |
T130 |
109490 |
632 |
0 |
0 |
T131 |
106133 |
746 |
0 |
0 |
T132 |
64391 |
547 |
0 |
0 |
T133 |
93678 |
430 |
0 |
0 |
T134 |
6996 |
42 |
0 |
0 |
T137 |
4086 |
59 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5146 |
0 |
0 |
T83 |
9535 |
1 |
0 |
0 |
T90 |
14641 |
69 |
0 |
0 |
T107 |
3551 |
5 |
0 |
0 |
T108 |
74518 |
506 |
0 |
0 |
T123 |
18418 |
16 |
0 |
0 |
T130 |
109490 |
856 |
0 |
0 |
T131 |
106133 |
757 |
0 |
0 |
T132 |
64391 |
392 |
0 |
0 |
T133 |
93678 |
372 |
0 |
0 |
T137 |
4086 |
8 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5940 |
0 |
0 |
T90 |
14641 |
92 |
0 |
0 |
T108 |
74518 |
473 |
0 |
0 |
T123 |
18418 |
22 |
0 |
0 |
T130 |
109490 |
935 |
0 |
0 |
T131 |
106133 |
845 |
0 |
0 |
T132 |
64391 |
754 |
0 |
0 |
T133 |
93678 |
423 |
0 |
0 |
T134 |
6996 |
10 |
0 |
0 |
T135 |
20360 |
50 |
0 |
0 |
T136 |
15455 |
149 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5227 |
0 |
0 |
T90 |
14641 |
92 |
0 |
0 |
T107 |
3551 |
40 |
0 |
0 |
T108 |
74518 |
522 |
0 |
0 |
T123 |
18418 |
26 |
0 |
0 |
T130 |
109490 |
753 |
0 |
0 |
T131 |
106133 |
780 |
0 |
0 |
T132 |
64391 |
370 |
0 |
0 |
T133 |
93678 |
338 |
0 |
0 |
T134 |
6996 |
42 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5528 |
0 |
0 |
T90 |
14641 |
15 |
0 |
0 |
T107 |
3551 |
6 |
0 |
0 |
T108 |
74518 |
471 |
0 |
0 |
T123 |
18418 |
39 |
0 |
0 |
T130 |
109490 |
860 |
0 |
0 |
T131 |
106133 |
833 |
0 |
0 |
T132 |
64391 |
558 |
0 |
0 |
T133 |
93678 |
337 |
0 |
0 |
T134 |
6996 |
50 |
0 |
0 |
T137 |
4086 |
6 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5802 |
0 |
0 |
T90 |
14641 |
125 |
0 |
0 |
T107 |
3551 |
37 |
0 |
0 |
T108 |
74518 |
538 |
0 |
0 |
T123 |
18418 |
25 |
0 |
0 |
T130 |
109490 |
878 |
0 |
0 |
T131 |
106133 |
847 |
0 |
0 |
T132 |
64391 |
712 |
0 |
0 |
T133 |
93678 |
236 |
0 |
0 |
T134 |
6996 |
93 |
0 |
0 |
T137 |
4086 |
61 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5832 |
0 |
0 |
T90 |
14641 |
133 |
0 |
0 |
T107 |
3551 |
1 |
0 |
0 |
T108 |
74518 |
517 |
0 |
0 |
T123 |
18418 |
82 |
0 |
0 |
T130 |
109490 |
798 |
0 |
0 |
T131 |
106133 |
699 |
0 |
0 |
T132 |
64391 |
632 |
0 |
0 |
T133 |
93678 |
495 |
0 |
0 |
T134 |
6996 |
9 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5485 |
0 |
0 |
T90 |
14641 |
172 |
0 |
0 |
T92 |
20578 |
1 |
0 |
0 |
T107 |
3551 |
2 |
0 |
0 |
T108 |
74518 |
506 |
0 |
0 |
T123 |
18418 |
40 |
0 |
0 |
T130 |
109490 |
847 |
0 |
0 |
T131 |
106133 |
787 |
0 |
0 |
T132 |
64391 |
403 |
0 |
0 |
T133 |
93678 |
351 |
0 |
0 |
T137 |
4086 |
52 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5363 |
0 |
0 |
T90 |
14641 |
65 |
0 |
0 |
T107 |
3551 |
57 |
0 |
0 |
T108 |
74518 |
471 |
0 |
0 |
T123 |
18418 |
62 |
0 |
0 |
T130 |
109490 |
826 |
0 |
0 |
T131 |
106133 |
689 |
0 |
0 |
T132 |
64391 |
456 |
0 |
0 |
T133 |
93678 |
491 |
0 |
0 |
T134 |
6996 |
106 |
0 |
0 |
T137 |
4086 |
49 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5880 |
0 |
0 |
T90 |
14641 |
139 |
0 |
0 |
T107 |
3551 |
48 |
0 |
0 |
T108 |
74518 |
491 |
0 |
0 |
T123 |
18418 |
17 |
0 |
0 |
T130 |
109490 |
873 |
0 |
0 |
T131 |
106133 |
704 |
0 |
0 |
T132 |
64391 |
340 |
0 |
0 |
T133 |
93678 |
599 |
0 |
0 |
T134 |
6996 |
50 |
0 |
0 |
T135 |
20360 |
23 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5856 |
0 |
0 |
T90 |
14641 |
53 |
0 |
0 |
T107 |
3551 |
1 |
0 |
0 |
T108 |
74518 |
491 |
0 |
0 |
T123 |
18418 |
20 |
0 |
0 |
T130 |
109490 |
899 |
0 |
0 |
T131 |
106133 |
779 |
0 |
0 |
T132 |
64391 |
475 |
0 |
0 |
T133 |
93678 |
556 |
0 |
0 |
T134 |
6996 |
97 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5666 |
0 |
0 |
T90 |
14641 |
52 |
0 |
0 |
T107 |
3551 |
37 |
0 |
0 |
T108 |
74518 |
517 |
0 |
0 |
T123 |
18418 |
16 |
0 |
0 |
T130 |
109490 |
1081 |
0 |
0 |
T131 |
106133 |
716 |
0 |
0 |
T132 |
64391 |
573 |
0 |
0 |
T133 |
93678 |
510 |
0 |
0 |
T134 |
6996 |
6 |
0 |
0 |
T137 |
4086 |
61 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5914 |
0 |
0 |
T90 |
14641 |
115 |
0 |
0 |
T107 |
3551 |
43 |
0 |
0 |
T108 |
74518 |
488 |
0 |
0 |
T123 |
18418 |
34 |
0 |
0 |
T130 |
109490 |
943 |
0 |
0 |
T131 |
106133 |
813 |
0 |
0 |
T132 |
64391 |
543 |
0 |
0 |
T133 |
93678 |
332 |
0 |
0 |
T134 |
6996 |
104 |
0 |
0 |
T137 |
4086 |
61 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
5437 |
0 |
0 |
T90 |
14641 |
116 |
0 |
0 |
T107 |
3551 |
50 |
0 |
0 |
T108 |
74518 |
520 |
0 |
0 |
T123 |
18418 |
12 |
0 |
0 |
T130 |
109490 |
803 |
0 |
0 |
T131 |
106133 |
832 |
0 |
0 |
T132 |
64391 |
565 |
0 |
0 |
T133 |
93678 |
275 |
0 |
0 |
T134 |
6996 |
8 |
0 |
0 |
T137 |
4086 |
6 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1758 |
0 |
0 |
T90 |
14641 |
34 |
0 |
0 |
T107 |
3551 |
7 |
0 |
0 |
T108 |
74518 |
468 |
0 |
0 |
T123 |
18418 |
48 |
0 |
0 |
T130 |
109490 |
221 |
0 |
0 |
T131 |
106133 |
162 |
0 |
0 |
T132 |
64391 |
93 |
0 |
0 |
T133 |
93678 |
106 |
0 |
0 |
T134 |
6996 |
3 |
0 |
0 |
T137 |
4086 |
1 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1651 |
0 |
0 |
T90 |
14641 |
35 |
0 |
0 |
T107 |
3551 |
2 |
0 |
0 |
T108 |
74518 |
485 |
0 |
0 |
T123 |
18418 |
13 |
0 |
0 |
T130 |
109490 |
114 |
0 |
0 |
T131 |
106133 |
130 |
0 |
0 |
T132 |
64391 |
122 |
0 |
0 |
T133 |
93678 |
52 |
0 |
0 |
T134 |
6996 |
21 |
0 |
0 |
T137 |
4086 |
8 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1884 |
0 |
0 |
T90 |
14641 |
32 |
0 |
0 |
T107 |
3551 |
7 |
0 |
0 |
T108 |
74518 |
547 |
0 |
0 |
T123 |
18418 |
25 |
0 |
0 |
T130 |
109490 |
173 |
0 |
0 |
T131 |
106133 |
154 |
0 |
0 |
T132 |
64391 |
115 |
0 |
0 |
T133 |
93678 |
92 |
0 |
0 |
T134 |
6996 |
10 |
0 |
0 |
T137 |
4086 |
10 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1672 |
0 |
0 |
T90 |
14641 |
22 |
0 |
0 |
T107 |
3551 |
4 |
0 |
0 |
T108 |
74518 |
486 |
0 |
0 |
T123 |
18418 |
14 |
0 |
0 |
T130 |
109490 |
175 |
0 |
0 |
T131 |
106133 |
181 |
0 |
0 |
T132 |
64391 |
109 |
0 |
0 |
T133 |
93678 |
73 |
0 |
0 |
T134 |
6996 |
7 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
2379 |
0 |
0 |
T90 |
14641 |
52 |
0 |
0 |
T108 |
74518 |
471 |
0 |
0 |
T123 |
18418 |
30 |
0 |
0 |
T130 |
109490 |
198 |
0 |
0 |
T131 |
106133 |
321 |
0 |
0 |
T132 |
64391 |
215 |
0 |
0 |
T133 |
93678 |
135 |
0 |
0 |
T134 |
6996 |
7 |
0 |
0 |
T135 |
20360 |
20 |
0 |
0 |
T137 |
4086 |
6 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
4927 |
0 |
0 |
T2 |
316743 |
12 |
0 |
0 |
T3 |
123810 |
38 |
0 |
0 |
T4 |
504879 |
0 |
0 |
0 |
T5 |
1092 |
0 |
0 |
0 |
T6 |
5603 |
0 |
0 |
0 |
T7 |
582194 |
0 |
0 |
0 |
T8 |
8204 |
0 |
0 |
0 |
T9 |
179236 |
0 |
0 |
0 |
T10 |
101527 |
0 |
0 |
0 |
T11 |
2264 |
0 |
0 |
0 |
T16 |
0 |
49 |
0 |
0 |
T138 |
0 |
40 |
0 |
0 |
T139 |
0 |
40 |
0 |
0 |
T140 |
0 |
23 |
0 |
0 |
T141 |
0 |
8 |
0 |
0 |
T142 |
0 |
65 |
0 |
0 |
T143 |
0 |
16 |
0 |
0 |
T144 |
0 |
8 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1564 |
0 |
0 |
T83 |
9535 |
6 |
0 |
0 |
T90 |
14641 |
34 |
0 |
0 |
T108 |
74518 |
440 |
0 |
0 |
T123 |
18418 |
15 |
0 |
0 |
T130 |
109490 |
174 |
0 |
0 |
T131 |
106133 |
133 |
0 |
0 |
T132 |
64391 |
114 |
0 |
0 |
T133 |
93678 |
69 |
0 |
0 |
T134 |
6996 |
34 |
0 |
0 |
T137 |
4086 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1779 |
0 |
0 |
T90 |
14641 |
14 |
0 |
0 |
T107 |
3551 |
9 |
0 |
0 |
T108 |
74518 |
505 |
0 |
0 |
T123 |
18418 |
55 |
0 |
0 |
T130 |
109490 |
166 |
0 |
0 |
T131 |
106133 |
153 |
0 |
0 |
T132 |
64391 |
100 |
0 |
0 |
T133 |
93678 |
83 |
0 |
0 |
T134 |
6996 |
12 |
0 |
0 |
T137 |
4086 |
7 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1430 |
0 |
0 |
T90 |
14641 |
23 |
0 |
0 |
T107 |
3551 |
3 |
0 |
0 |
T108 |
74518 |
549 |
0 |
0 |
T123 |
18418 |
40 |
0 |
0 |
T130 |
109490 |
110 |
0 |
0 |
T131 |
106133 |
99 |
0 |
0 |
T132 |
64391 |
85 |
0 |
0 |
T133 |
93678 |
56 |
0 |
0 |
T134 |
6996 |
15 |
0 |
0 |
T135 |
20360 |
11 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1489 |
0 |
0 |
T90 |
14641 |
28 |
0 |
0 |
T107 |
3551 |
6 |
0 |
0 |
T108 |
74518 |
489 |
0 |
0 |
T123 |
18418 |
18 |
0 |
0 |
T130 |
109490 |
104 |
0 |
0 |
T131 |
106133 |
147 |
0 |
0 |
T132 |
64391 |
86 |
0 |
0 |
T133 |
93678 |
45 |
0 |
0 |
T134 |
6996 |
11 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1404 |
0 |
0 |
T90 |
14641 |
18 |
0 |
0 |
T107 |
3551 |
1 |
0 |
0 |
T108 |
74518 |
504 |
0 |
0 |
T123 |
18418 |
54 |
0 |
0 |
T130 |
109490 |
98 |
0 |
0 |
T131 |
106133 |
98 |
0 |
0 |
T132 |
64391 |
73 |
0 |
0 |
T133 |
93678 |
57 |
0 |
0 |
T134 |
6996 |
7 |
0 |
0 |
T137 |
4086 |
3 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1408 |
0 |
0 |
T90 |
14641 |
14 |
0 |
0 |
T107 |
3551 |
7 |
0 |
0 |
T108 |
74518 |
462 |
0 |
0 |
T123 |
18418 |
39 |
0 |
0 |
T130 |
109490 |
101 |
0 |
0 |
T131 |
106133 |
131 |
0 |
0 |
T132 |
64391 |
75 |
0 |
0 |
T133 |
93678 |
55 |
0 |
0 |
T134 |
6996 |
6 |
0 |
0 |
T137 |
4086 |
5 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
2394 |
0 |
0 |
T90 |
14641 |
17 |
0 |
0 |
T107 |
3551 |
12 |
0 |
0 |
T108 |
74518 |
480 |
0 |
0 |
T123 |
18418 |
37 |
0 |
0 |
T130 |
109490 |
292 |
0 |
0 |
T131 |
106133 |
216 |
0 |
0 |
T132 |
64391 |
197 |
0 |
0 |
T133 |
93678 |
161 |
0 |
0 |
T134 |
6996 |
23 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1401 |
0 |
0 |
T90 |
14641 |
14 |
0 |
0 |
T107 |
3551 |
2 |
0 |
0 |
T108 |
74518 |
505 |
0 |
0 |
T123 |
18418 |
30 |
0 |
0 |
T130 |
109490 |
115 |
0 |
0 |
T131 |
106133 |
108 |
0 |
0 |
T132 |
64391 |
77 |
0 |
0 |
T133 |
93678 |
87 |
0 |
0 |
T134 |
6996 |
8 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
2921 |
0 |
0 |
T90 |
14641 |
73 |
0 |
0 |
T107 |
3551 |
18 |
0 |
0 |
T108 |
74518 |
466 |
0 |
0 |
T123 |
18418 |
36 |
0 |
0 |
T130 |
109490 |
371 |
0 |
0 |
T131 |
106133 |
387 |
0 |
0 |
T132 |
64391 |
183 |
0 |
0 |
T133 |
93678 |
238 |
0 |
0 |
T134 |
6996 |
18 |
0 |
0 |
T137 |
4086 |
11 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1752 |
0 |
0 |
T90 |
14641 |
21 |
0 |
0 |
T107 |
3551 |
7 |
0 |
0 |
T108 |
74518 |
477 |
0 |
0 |
T123 |
18418 |
44 |
0 |
0 |
T130 |
109490 |
173 |
0 |
0 |
T131 |
106133 |
170 |
0 |
0 |
T132 |
64391 |
97 |
0 |
0 |
T133 |
93678 |
98 |
0 |
0 |
T134 |
6996 |
12 |
0 |
0 |
T137 |
4086 |
12 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1447 |
0 |
0 |
T90 |
14641 |
27 |
0 |
0 |
T107 |
3551 |
3 |
0 |
0 |
T108 |
74518 |
488 |
0 |
0 |
T123 |
18418 |
35 |
0 |
0 |
T130 |
109490 |
111 |
0 |
0 |
T131 |
106133 |
139 |
0 |
0 |
T132 |
64391 |
93 |
0 |
0 |
T133 |
93678 |
58 |
0 |
0 |
T134 |
6996 |
8 |
0 |
0 |
T135 |
20360 |
28 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1495 |
0 |
0 |
T90 |
14641 |
19 |
0 |
0 |
T108 |
74518 |
475 |
0 |
0 |
T123 |
18418 |
44 |
0 |
0 |
T130 |
109490 |
103 |
0 |
0 |
T131 |
106133 |
96 |
0 |
0 |
T132 |
64391 |
81 |
0 |
0 |
T133 |
93678 |
56 |
0 |
0 |
T134 |
6996 |
11 |
0 |
0 |
T135 |
20360 |
111 |
0 |
0 |
T137 |
4086 |
1 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1497 |
0 |
0 |
T90 |
14641 |
30 |
0 |
0 |
T107 |
3551 |
4 |
0 |
0 |
T108 |
74518 |
494 |
0 |
0 |
T123 |
18418 |
30 |
0 |
0 |
T130 |
109490 |
119 |
0 |
0 |
T131 |
106133 |
115 |
0 |
0 |
T132 |
64391 |
83 |
0 |
0 |
T133 |
93678 |
78 |
0 |
0 |
T134 |
6996 |
19 |
0 |
0 |
T137 |
4086 |
1 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1486 |
0 |
0 |
T90 |
14641 |
28 |
0 |
0 |
T107 |
3551 |
7 |
0 |
0 |
T108 |
74518 |
526 |
0 |
0 |
T123 |
18418 |
28 |
0 |
0 |
T130 |
109490 |
111 |
0 |
0 |
T131 |
106133 |
101 |
0 |
0 |
T132 |
64391 |
64 |
0 |
0 |
T133 |
93678 |
65 |
0 |
0 |
T134 |
6996 |
7 |
0 |
0 |
T137 |
4086 |
5 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1435 |
0 |
0 |
T90 |
14641 |
30 |
0 |
0 |
T107 |
3551 |
4 |
0 |
0 |
T108 |
74518 |
509 |
0 |
0 |
T123 |
18418 |
27 |
0 |
0 |
T130 |
109490 |
131 |
0 |
0 |
T131 |
106133 |
121 |
0 |
0 |
T132 |
64391 |
57 |
0 |
0 |
T133 |
93678 |
45 |
0 |
0 |
T134 |
6996 |
9 |
0 |
0 |
T137 |
4086 |
2 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441738623 |
1487 |
0 |
0 |
T90 |
14641 |
20 |
0 |
0 |
T92 |
20578 |
5 |
0 |
0 |
T107 |
3551 |
1 |
0 |
0 |
T108 |
74518 |
544 |
0 |
0 |
T123 |
18418 |
41 |
0 |
0 |
T130 |
109490 |
94 |
0 |
0 |
T131 |
106133 |
136 |
0 |
0 |
T132 |
64391 |
89 |
0 |
0 |
T133 |
93678 |
58 |
0 |
0 |
T137 |
4086 |
4 |
0 |
0 |