Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3646187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4374265

1

T1

33170

T2

873

T3

897

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4284452	1			T1	26855		T2	2		T3	5
values[0x0]	1865601	1			T1	16211		T2	436		T3	452
values[0x1]	1870399	1			T1	16467		T2	439		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2574249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5446203

1

T1

41384

T2

873

T3

900

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32390	1			T1	228		T2	4		T4	40
valid_sources[0x01]	72358	1			T1	233		T2	3		T4	29
valid_sources[0x02]	30693	1			T1	231		T2	2		T4	26
valid_sources[0x03]	29707	1			T1	255		T2	5		T4	35
valid_sources[0x04]	30118	1			T1	238		T2	1		T4	38
valid_sources[0x05]	29186	1			T1	237		T2	2		T4	30
valid_sources[0x06]	31749	1			T1	228		T2	2		T4	35
valid_sources[0x07]	29703	1			T1	197		T2	1		T4	29
valid_sources[0x08]	30724	1			T1	243		T2	3		T4	44
valid_sources[0x09]	31925	1			T1	199		T2	6		T4	27
valid_sources[0x0a]	28969	1			T1	227		T2	2		T4	33
valid_sources[0x0b]	30425	1			T1	229		T2	4		T4	29
valid_sources[0x0c]	34743	1			T1	234		T2	5		T4	36
valid_sources[0x0d]	30544	1			T1	213		T2	3		T4	44
valid_sources[0x0e]	31560	1			T1	224		T2	2		T4	28
valid_sources[0x0f]	32187	1			T1	247		T2	1		T4	26
valid_sources[0x10]	32588	1			T1	198		T2	2		T4	35
valid_sources[0x11]	31708	1			T1	278		T2	2		T4	27
valid_sources[0x12]	29041	1			T1	201		T2	3		T4	31
valid_sources[0x13]	30856	1			T1	250		T2	4		T4	19
valid_sources[0x14]	30173	1			T1	245		T2	3		T4	27
valid_sources[0x15]	32085	1			T1	188		T2	2		T4	28
valid_sources[0x16]	31137	1			T1	249		T2	4		T4	29
valid_sources[0x17]	31959	1			T1	229		T2	2		T4	38
valid_sources[0x18]	31223	1			T1	221		T2	9		T4	36
valid_sources[0x19]	33265	1			T1	225		T2	4		T4	46
valid_sources[0x1a]	33079	1			T1	254		T2	1		T4	40
valid_sources[0x1b]	30697	1			T1	235		T2	5		T4	35
valid_sources[0x1c]	41808	1			T1	262		T2	4		T4	31
valid_sources[0x1d]	27951	1			T1	226		T2	3		T4	38
valid_sources[0x1e]	29531	1			T1	258		T2	3		T4	26
valid_sources[0x1f]	30943	1			T1	228		T2	6		T4	24
valid_sources[0x20]	28325	1			T1	236		T2	3		T4	41
valid_sources[0x21]	34059	1			T1	214		T2	8		T4	31
valid_sources[0x22]	29091	1			T1	231		T2	8		T4	20
valid_sources[0x23]	30686	1			T1	242		T2	6		T4	34
valid_sources[0x24]	28672	1			T1	216		T2	6		T4	34
valid_sources[0x25]	33762	1			T1	236		T2	6		T4	30
valid_sources[0x26]	31386	1			T1	214		T2	3		T3	452
valid_sources[0x27]	29414	1			T1	250		T2	5		T4	34
valid_sources[0x28]	29867	1			T1	235		T2	3		T4	33
valid_sources[0x29]	28460	1			T1	229		T2	2		T4	38
valid_sources[0x2a]	32123	1			T1	220		T2	2		T4	33
valid_sources[0x2b]	30524	1			T1	230		T2	3		T4	33
valid_sources[0x2c]	34455	1			T1	236		T2	2		T4	24
valid_sources[0x2d]	30035	1			T1	232		T2	5		T4	38
valid_sources[0x2e]	35053	1			T1	214		T2	5		T4	26
valid_sources[0x2f]	29710	1			T1	217		T2	5		T4	29
valid_sources[0x30]	30416	1			T1	185		T2	3		T4	35
valid_sources[0x31]	31029	1			T1	230		T2	4		T4	38
valid_sources[0x32]	31890	1			T1	217		T2	2		T4	38
valid_sources[0x33]	35504	1			T1	261		T2	3		T4	33
valid_sources[0x34]	29617	1			T1	252		T2	3		T4	35
valid_sources[0x35]	28386	1			T1	248		T2	1		T4	31
valid_sources[0x36]	30760	1			T1	234		T2	4		T4	23
valid_sources[0x37]	33639	1			T1	212		T2	3		T4	36
valid_sources[0x38]	44622	1			T1	272		T2	6		T4	40
valid_sources[0x39]	30812	1			T1	234		T2	3		T4	41
valid_sources[0x3a]	28316	1			T1	249		T2	2		T4	28
valid_sources[0x3b]	35270	1			T1	270		T2	6		T4	37
valid_sources[0x3c]	32150	1			T1	249		T2	3		T4	43
valid_sources[0x3d]	28924	1			T1	223		T2	6		T4	25
valid_sources[0x3e]	29768	1			T1	217		T2	7		T4	38
valid_sources[0x3f]	33135	1			T1	249		T2	3		T4	30
valid_sources[0x40]	34733	1			T1	221		T2	2		T4	33
valid_sources[0x41]	28124	1			T1	206		T4	34		T5	2
valid_sources[0x42]	31184	1			T1	294		T2	2		T4	38
valid_sources[0x43]	30249	1			T1	199		T2	3		T4	36
valid_sources[0x44]	33724	1			T1	234		T2	2		T4	23
valid_sources[0x45]	34773	1			T1	229		T2	4		T4	34
valid_sources[0x46]	30056	1			T1	220		T2	2		T4	35
valid_sources[0x47]	30682	1			T1	220		T2	6		T4	32
valid_sources[0x48]	32050	1			T1	219		T2	6		T4	27
valid_sources[0x49]	30504	1			T1	224		T2	4		T4	40
valid_sources[0x4a]	30512	1			T1	243		T2	5		T4	38
valid_sources[0x4b]	27450	1			T1	235		T2	6		T4	36
valid_sources[0x4c]	33065	1			T1	248		T2	2		T4	36
valid_sources[0x4d]	35016	1			T1	219		T2	7		T4	33
valid_sources[0x4e]	27900	1			T1	212		T2	2		T4	29
valid_sources[0x4f]	29706	1			T1	209		T2	7		T3	450
valid_sources[0x50]	34901	1			T1	238		T2	4		T4	21
valid_sources[0x51]	31253	1			T1	289		T4	39		T8	133
valid_sources[0x52]	31639	1			T1	242		T2	4		T4	31
valid_sources[0x53]	28659	1			T1	254		T2	3		T4	35
valid_sources[0x54]	28238	1			T1	223		T2	2		T4	31
valid_sources[0x55]	30380	1			T1	229		T2	4		T4	30
valid_sources[0x56]	29862	1			T1	222		T2	2		T4	37
valid_sources[0x57]	28061	1			T1	197		T2	5		T4	27
valid_sources[0x58]	32991	1			T1	240		T2	4		T4	24
valid_sources[0x59]	27549	1			T1	237		T2	3		T4	23
valid_sources[0x5a]	31157	1			T1	255		T2	1		T4	38
valid_sources[0x5b]	29633	1			T1	223		T2	5		T4	40
valid_sources[0x5c]	31889	1			T1	191		T2	1		T4	33
valid_sources[0x5d]	31516	1			T1	235		T2	3		T4	34
valid_sources[0x5e]	31120	1			T1	228		T2	8		T4	34
valid_sources[0x5f]	27583	1			T1	204		T2	4		T4	21
valid_sources[0x60]	33330	1			T1	229		T2	5		T4	28
valid_sources[0x61]	31047	1			T1	224		T2	5		T4	39
valid_sources[0x62]	30390	1			T1	234		T2	2		T4	39
valid_sources[0x63]	30873	1			T1	243		T2	4		T4	26
valid_sources[0x64]	29709	1			T1	203		T2	1		T4	24
valid_sources[0x65]	27759	1			T1	207		T2	3		T4	27
valid_sources[0x66]	27254	1			T1	214		T2	3		T4	38
valid_sources[0x67]	29632	1			T1	234		T2	4		T4	37
valid_sources[0x68]	37293	1			T1	219		T2	3		T4	38
valid_sources[0x69]	26881	1			T1	225		T2	2		T4	39
valid_sources[0x6a]	30221	1			T1	218		T2	6		T4	18
valid_sources[0x6b]	31785	1			T1	223		T2	7		T4	34
valid_sources[0x6c]	32835	1			T1	238		T2	1		T4	25
valid_sources[0x6d]	28366	1			T1	220		T2	7		T4	30
valid_sources[0x6e]	28105	1			T1	258		T2	4		T4	30
valid_sources[0x6f]	28190	1			T1	242		T4	32		T5	4
valid_sources[0x70]	31074	1			T1	265		T2	4		T4	25
valid_sources[0x71]	28890	1			T1	230		T2	2		T4	35
valid_sources[0x72]	29767	1			T1	252		T2	1		T4	40
valid_sources[0x73]	30332	1			T1	236		T2	4		T4	42
valid_sources[0x74]	29403	1			T1	202		T2	9		T4	31
valid_sources[0x75]	30075	1			T1	212		T2	4		T4	35
valid_sources[0x76]	28779	1			T1	257		T2	4		T4	36
valid_sources[0x77]	31771	1			T1	222		T2	3		T4	29
valid_sources[0x78]	31018	1			T1	261		T2	5		T4	26
valid_sources[0x79]	31212	1			T1	218		T2	4		T4	42
valid_sources[0x7a]	29074	1			T1	206		T2	3		T4	37
valid_sources[0x7b]	27810	1			T1	285		T2	3		T4	38
valid_sources[0x7c]	27609	1			T1	234		T2	3		T4	39
valid_sources[0x7d]	33478	1			T1	220		T2	3		T4	25
valid_sources[0x7e]	31484	1			T1	261		T2	5		T4	26
valid_sources[0x7f]	27378	1			T1	234		T2	5		T4	39
valid_sources[0x80]	30701	1			T1	258		T2	3		T4	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

978290

1

T1

3651

T2

1

T3

2

values[0x0]

all_enables

biggest_size

1708060

1

T1

14771

T2

434

T3

451

values[0x1]

all_enables

biggest_size

1687915

1

T1

14748

T2

438

T3

444