SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[spi_device_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 5811401 | 1 | T1 | 40489 | T2 | 45 | T3 | 70 | ||||
auto[1] | 2228153 | 1 | T1 | 19044 | T2 | 832 | T3 | 832 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 8039289 | 1 | T1 | 59533 | T2 | 877 | T3 | 902 | ||||
values[1] | 26 | 1 | T98 | 1 | T99 | 4 | T154 | 1 | ||||
values[2] | 5 | 1 | T173 | 2 | T174 | 1 | T175 | 1 | ||||
values[3] | 134 | 1 | T97 | 3 | T98 | 4 | T99 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 8039321 | 1 | T1 | 59533 | T2 | 877 | T3 | 902 | ||||
values[1] | 25 | 1 | T99 | 3 | T153 | 2 | T173 | 1 | ||||
values[2] | 5 | 1 | T173 | 1 | T176 | 1 | T177 | 1 | ||||
values[3] | 115 | 1 | T97 | 4 | T98 | 2 | T99 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 8039194 | 1 | T1 | 59533 | T2 | 877 | T3 | 902 | ||||
auto[TlIntgErrCmd] | 127 | 1 | T97 | 3 | T98 | 7 | T99 | 15 | ||||
auto[TlIntgErrData] | 95 | 1 | T97 | 5 | T98 | 1 | T99 | 4 | ||||
auto[TlIntgErrBoth] | 138 | 1 | T97 | 2 | T98 | 2 | T99 | 11 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |