Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3666229

1

T1

26363

T2

4

T3

5

full_word

4373325

1

T1

33170

T2

873

T3

897

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8039194	1			T1	59533		T2	877		T3	902
auto[TlIntgErrCmd]	127	1			T97	3		T98	7		T99	15
auto[TlIntgErrData]	95	1			T97	5		T98	1		T99	4
auto[TlIntgErrBoth]	138	1			T97	2		T98	2		T99	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4286124

1

T1

26855

T2

2

T3

5

auto[1]

3753430

1

T1

32678

T2

875

T3

897

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3307625	1			T1	23204		T2	1		T3	3
auto[TlIntgErrNone]	partial	auto[1]	358283	1			T1	3159		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	978340	1			T1	3651		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	3394946	1			T1	29519		T2	872		T3	895
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T97	1		T98	1		T99	8
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T97	1		T98	4		T99	7
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T154	1		T157	2		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T97	1		T98	2		T174	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T97	3		T99	1		T153	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T97	2		T98	1		T99	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T99	1		T155	1		T157	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T99	1		T178	1		T157	3
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T97	1		T98	2		T99	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T97	1		T99	5		T153	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T99	2		T173	1		T154	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T176	1		T177	4		T179	1