Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	3116054	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	3116054	0	0
T1	251416	29106	0	0
T2	3319	1667	0	0
T3	124381	1663	0	0
T4	113057	9152	0	0
T5	64540	0	0	0
T6	9426	0	0	0
T7	18136	1663	0	0
T8	354421	7498	0	0
T9	3444	0	0	0
T10	333892	0	0	0
T11	0	832	0	0
T12	0	1663	0	0
T13	0	832	0	0
T15	0	11647	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	3446837	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	3446837	0	0
T1	251416	17472	0	0
T2	3319	836	0	0
T3	124381	832	0	0
T4	113057	7654	0	0
T5	64540	0	0	0
T6	9426	0	0	0
T7	18136	832	0	0
T8	354421	13977	0	0
T9	3444	0	0	0
T10	333892	0	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	3690	0	0
T15	0	25840	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	187343	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	187343	0	0
T1	251416	1572	0	0
T2	3319	0	0	0
T3	124381	0	0	0
T4	113057	352	0	0
T5	64540	0	0	0
T6	9426	0	0	0
T7	18136	0	0	0
T8	354421	487	0	0
T9	3444	35	0	0
T10	333892	603	0	0
T13	0	128	0	0
T15	0	224	0	0
T24	0	752	0	0
T25	0	149	0	0
T34	0	674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	392918	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	392918	0	0
T1	251416	1572	0	0
T2	3319	0	0	0
T3	124381	0	0	0
T4	113057	850	0	0
T5	64540	0	0	0
T6	9426	0	0	0
T7	18136	0	0	0
T8	354421	2214	0	0
T9	3444	159	0	0
T10	333892	603	0	0
T13	0	621	0	0
T15	0	1068	0	0
T24	0	752	0	0
T25	0	149	0	0
T34	0	1864	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	6197641	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	6197641	0	0
T1	251416	40781	0	0
T2	3319	45	0	0
T3	124381	70	0	0
T4	113057	2055	0	0
T5	64540	446	0	0
T6	9426	41	0	0
T7	18136	46	0	0
T8	354421	38429	0	0
T9	3444	160	0	0
T10	333892	6555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460293511	12300920	0	0
DepthKnown_A	460293511	460164997	0	0
RvalidKnown_A	460293511	460164997	0	0
WreadyKnown_A	460293511	460164997	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	12300920	0	0
T1	251416	40489	0	0
T2	3319	221	0	0
T3	124381	201	0	0
T4	113057	5074	0	0
T5	64540	446	0	0
T6	9426	41	0	0
T7	18136	46	0	0
T8	354421	154248	0	0
T9	3444	680	0	0
T10	333892	6517	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460293511	460164997	0	0
T1	251416	251383	0	0
T2	3319	3246	0	0
T3	124381	124376	0	0
T4	113057	113048	0	0
T5	64540	64441	0	0
T6	9426	9329	0	0
T7	18136	18086	0	0
T8	354421	354415	0	0
T9	3444	3373	0	0
T10	333892	333814	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0