Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
3699 |
0 |
0 |
T95 |
2484 |
1 |
0 |
0 |
T96 |
2367 |
44 |
0 |
0 |
T98 |
28529 |
1 |
0 |
0 |
T99 |
29517 |
5 |
0 |
0 |
T100 |
4834 |
2 |
0 |
0 |
T101 |
7454 |
96 |
0 |
0 |
T102 |
5231 |
89 |
0 |
0 |
T104 |
4317 |
86 |
0 |
0 |
T111 |
14008 |
3 |
0 |
0 |
T112 |
2553 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1975 |
0 |
0 |
T111 |
14008 |
37 |
0 |
0 |
T113 |
10179 |
17 |
0 |
0 |
T120 |
36314 |
246 |
0 |
0 |
T121 |
9630 |
14 |
0 |
0 |
T122 |
7952 |
10 |
0 |
0 |
T143 |
4031 |
2 |
0 |
0 |
T153 |
33541 |
23 |
0 |
0 |
T154 |
70046 |
72 |
0 |
0 |
T155 |
36786 |
35 |
0 |
0 |
T156 |
61442 |
43 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1868 |
0 |
0 |
T111 |
14008 |
13 |
0 |
0 |
T113 |
10179 |
22 |
0 |
0 |
T120 |
36314 |
244 |
0 |
0 |
T121 |
9630 |
14 |
0 |
0 |
T122 |
7952 |
12 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T143 |
4031 |
3 |
0 |
0 |
T153 |
33541 |
18 |
0 |
0 |
T154 |
70046 |
68 |
0 |
0 |
T155 |
36786 |
21 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2469 |
0 |
0 |
T111 |
14008 |
34 |
0 |
0 |
T113 |
10179 |
15 |
0 |
0 |
T120 |
36314 |
224 |
0 |
0 |
T121 |
9630 |
36 |
0 |
0 |
T122 |
7952 |
9 |
0 |
0 |
T124 |
3805 |
19 |
0 |
0 |
T143 |
4031 |
13 |
0 |
0 |
T153 |
33541 |
44 |
0 |
0 |
T154 |
70046 |
159 |
0 |
0 |
T155 |
36786 |
80 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
8809 |
0 |
0 |
T111 |
14008 |
267 |
0 |
0 |
T113 |
10179 |
244 |
0 |
0 |
T120 |
36314 |
240 |
0 |
0 |
T121 |
9630 |
230 |
0 |
0 |
T122 |
7952 |
126 |
0 |
0 |
T140 |
3618 |
59 |
0 |
0 |
T143 |
4031 |
119 |
0 |
0 |
T153 |
33541 |
421 |
0 |
0 |
T154 |
70046 |
1159 |
0 |
0 |
T155 |
36786 |
553 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
9753 |
0 |
0 |
T111 |
14008 |
307 |
0 |
0 |
T113 |
10179 |
137 |
0 |
0 |
T120 |
36314 |
200 |
0 |
0 |
T121 |
9630 |
130 |
0 |
0 |
T122 |
7952 |
110 |
0 |
0 |
T124 |
3805 |
75 |
0 |
0 |
T143 |
4031 |
7 |
0 |
0 |
T153 |
33541 |
328 |
0 |
0 |
T154 |
70046 |
1339 |
0 |
0 |
T155 |
36786 |
550 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
9248 |
0 |
0 |
T111 |
14008 |
13 |
0 |
0 |
T113 |
10179 |
112 |
0 |
0 |
T120 |
36314 |
200 |
0 |
0 |
T121 |
9630 |
327 |
0 |
0 |
T122 |
7952 |
111 |
0 |
0 |
T124 |
3805 |
2 |
0 |
0 |
T140 |
3618 |
66 |
0 |
0 |
T143 |
4031 |
120 |
0 |
0 |
T153 |
33541 |
470 |
0 |
0 |
T154 |
70046 |
1299 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
8120 |
0 |
0 |
T111 |
14008 |
157 |
0 |
0 |
T113 |
10179 |
22 |
0 |
0 |
T120 |
36314 |
260 |
0 |
0 |
T121 |
9630 |
127 |
0 |
0 |
T122 |
7952 |
138 |
0 |
0 |
T124 |
3805 |
9 |
0 |
0 |
T143 |
4031 |
116 |
0 |
0 |
T153 |
33541 |
218 |
0 |
0 |
T154 |
70046 |
733 |
0 |
0 |
T155 |
36786 |
438 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
9726 |
0 |
0 |
T111 |
14008 |
241 |
0 |
0 |
T113 |
10179 |
133 |
0 |
0 |
T120 |
36314 |
240 |
0 |
0 |
T121 |
9630 |
106 |
0 |
0 |
T122 |
7952 |
98 |
0 |
0 |
T124 |
3805 |
3 |
0 |
0 |
T140 |
3618 |
70 |
0 |
0 |
T143 |
4031 |
140 |
0 |
0 |
T153 |
33541 |
425 |
0 |
0 |
T154 |
70046 |
1070 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
10379 |
0 |
0 |
T101 |
7454 |
2 |
0 |
0 |
T111 |
14008 |
277 |
0 |
0 |
T113 |
10179 |
152 |
0 |
0 |
T120 |
36314 |
215 |
0 |
0 |
T121 |
9630 |
236 |
0 |
0 |
T122 |
7952 |
233 |
0 |
0 |
T124 |
3805 |
110 |
0 |
0 |
T140 |
3618 |
66 |
0 |
0 |
T153 |
33541 |
412 |
0 |
0 |
T154 |
70046 |
1458 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
9394 |
0 |
0 |
T111 |
14008 |
302 |
0 |
0 |
T113 |
10179 |
148 |
0 |
0 |
T120 |
36314 |
230 |
0 |
0 |
T121 |
9630 |
101 |
0 |
0 |
T122 |
7952 |
97 |
0 |
0 |
T124 |
3805 |
83 |
0 |
0 |
T143 |
4031 |
3 |
0 |
0 |
T153 |
33541 |
246 |
0 |
0 |
T154 |
70046 |
1189 |
0 |
0 |
T155 |
36786 |
735 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
9311 |
0 |
0 |
T111 |
14008 |
109 |
0 |
0 |
T113 |
10179 |
127 |
0 |
0 |
T120 |
36314 |
193 |
0 |
0 |
T121 |
9630 |
144 |
0 |
0 |
T122 |
7952 |
228 |
0 |
0 |
T124 |
3805 |
89 |
0 |
0 |
T140 |
3618 |
67 |
0 |
0 |
T143 |
4031 |
5 |
0 |
0 |
T153 |
33541 |
463 |
0 |
0 |
T154 |
70046 |
1323 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4771 |
0 |
0 |
T111 |
14008 |
27 |
0 |
0 |
T113 |
10179 |
12 |
0 |
0 |
T120 |
36314 |
243 |
0 |
0 |
T121 |
9630 |
44 |
0 |
0 |
T122 |
7952 |
66 |
0 |
0 |
T124 |
3805 |
45 |
0 |
0 |
T140 |
3618 |
31 |
0 |
0 |
T143 |
4031 |
49 |
0 |
0 |
T153 |
33541 |
209 |
0 |
0 |
T154 |
70046 |
591 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4928 |
0 |
0 |
T111 |
14008 |
115 |
0 |
0 |
T113 |
10179 |
45 |
0 |
0 |
T120 |
36314 |
241 |
0 |
0 |
T121 |
9630 |
48 |
0 |
0 |
T122 |
7952 |
6 |
0 |
0 |
T124 |
3805 |
2 |
0 |
0 |
T143 |
4031 |
66 |
0 |
0 |
T153 |
33541 |
136 |
0 |
0 |
T154 |
70046 |
456 |
0 |
0 |
T155 |
36786 |
381 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5087 |
0 |
0 |
T111 |
14008 |
88 |
0 |
0 |
T113 |
10179 |
111 |
0 |
0 |
T120 |
36314 |
221 |
0 |
0 |
T121 |
9630 |
80 |
0 |
0 |
T122 |
7952 |
29 |
0 |
0 |
T124 |
3805 |
59 |
0 |
0 |
T140 |
3618 |
52 |
0 |
0 |
T143 |
4031 |
3 |
0 |
0 |
T153 |
33541 |
178 |
0 |
0 |
T154 |
70046 |
662 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5028 |
0 |
0 |
T111 |
14008 |
23 |
0 |
0 |
T113 |
10179 |
8 |
0 |
0 |
T120 |
36314 |
231 |
0 |
0 |
T121 |
9630 |
105 |
0 |
0 |
T122 |
7952 |
90 |
0 |
0 |
T124 |
3805 |
8 |
0 |
0 |
T140 |
3618 |
24 |
0 |
0 |
T143 |
4031 |
51 |
0 |
0 |
T153 |
33541 |
171 |
0 |
0 |
T154 |
70046 |
612 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4696 |
0 |
0 |
T111 |
14008 |
47 |
0 |
0 |
T113 |
10179 |
66 |
0 |
0 |
T120 |
36314 |
247 |
0 |
0 |
T121 |
9630 |
68 |
0 |
0 |
T122 |
7952 |
104 |
0 |
0 |
T140 |
3618 |
8 |
0 |
0 |
T143 |
4031 |
3 |
0 |
0 |
T153 |
33541 |
164 |
0 |
0 |
T154 |
70046 |
468 |
0 |
0 |
T155 |
36786 |
307 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4561 |
0 |
0 |
T111 |
14008 |
157 |
0 |
0 |
T113 |
10179 |
11 |
0 |
0 |
T120 |
36314 |
209 |
0 |
0 |
T121 |
9630 |
17 |
0 |
0 |
T122 |
7952 |
56 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T140 |
3618 |
18 |
0 |
0 |
T143 |
4031 |
4 |
0 |
0 |
T153 |
33541 |
213 |
0 |
0 |
T154 |
70046 |
522 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4846 |
0 |
0 |
T111 |
14008 |
68 |
0 |
0 |
T113 |
10179 |
129 |
0 |
0 |
T120 |
36314 |
211 |
0 |
0 |
T121 |
9630 |
113 |
0 |
0 |
T122 |
7952 |
64 |
0 |
0 |
T124 |
3805 |
25 |
0 |
0 |
T140 |
3618 |
10 |
0 |
0 |
T143 |
4031 |
24 |
0 |
0 |
T153 |
33541 |
90 |
0 |
0 |
T154 |
70046 |
622 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4932 |
0 |
0 |
T111 |
14008 |
22 |
0 |
0 |
T113 |
10179 |
49 |
0 |
0 |
T120 |
36314 |
230 |
0 |
0 |
T121 |
9630 |
81 |
0 |
0 |
T122 |
7952 |
62 |
0 |
0 |
T140 |
3618 |
6 |
0 |
0 |
T143 |
4031 |
56 |
0 |
0 |
T153 |
33541 |
75 |
0 |
0 |
T154 |
70046 |
670 |
0 |
0 |
T155 |
36786 |
242 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5005 |
0 |
0 |
T111 |
14008 |
22 |
0 |
0 |
T113 |
10179 |
85 |
0 |
0 |
T120 |
36314 |
216 |
0 |
0 |
T121 |
9630 |
49 |
0 |
0 |
T122 |
7952 |
72 |
0 |
0 |
T124 |
3805 |
44 |
0 |
0 |
T140 |
3618 |
9 |
0 |
0 |
T143 |
4031 |
4 |
0 |
0 |
T153 |
33541 |
172 |
0 |
0 |
T154 |
70046 |
593 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5319 |
0 |
0 |
T106 |
8000 |
1 |
0 |
0 |
T111 |
14008 |
109 |
0 |
0 |
T113 |
10179 |
56 |
0 |
0 |
T120 |
36314 |
153 |
0 |
0 |
T121 |
9630 |
9 |
0 |
0 |
T124 |
3805 |
8 |
0 |
0 |
T140 |
3618 |
31 |
0 |
0 |
T143 |
4031 |
56 |
0 |
0 |
T153 |
33541 |
218 |
0 |
0 |
T154 |
70046 |
577 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4928 |
0 |
0 |
T111 |
14008 |
102 |
0 |
0 |
T113 |
10179 |
57 |
0 |
0 |
T120 |
36314 |
240 |
0 |
0 |
T121 |
9630 |
16 |
0 |
0 |
T122 |
7952 |
83 |
0 |
0 |
T124 |
3805 |
2 |
0 |
0 |
T140 |
3618 |
3 |
0 |
0 |
T143 |
4031 |
9 |
0 |
0 |
T153 |
33541 |
105 |
0 |
0 |
T154 |
70046 |
463 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5065 |
0 |
0 |
T111 |
14008 |
28 |
0 |
0 |
T113 |
10179 |
85 |
0 |
0 |
T120 |
36314 |
190 |
0 |
0 |
T121 |
9630 |
91 |
0 |
0 |
T122 |
7952 |
59 |
0 |
0 |
T124 |
3805 |
5 |
0 |
0 |
T143 |
4031 |
63 |
0 |
0 |
T153 |
33541 |
218 |
0 |
0 |
T154 |
70046 |
400 |
0 |
0 |
T155 |
36786 |
303 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4889 |
0 |
0 |
T111 |
14008 |
64 |
0 |
0 |
T113 |
10179 |
23 |
0 |
0 |
T120 |
36314 |
226 |
0 |
0 |
T121 |
9630 |
74 |
0 |
0 |
T122 |
7952 |
74 |
0 |
0 |
T124 |
3805 |
44 |
0 |
0 |
T140 |
3618 |
27 |
0 |
0 |
T143 |
4031 |
31 |
0 |
0 |
T153 |
33541 |
189 |
0 |
0 |
T154 |
70046 |
490 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4773 |
0 |
0 |
T111 |
14008 |
61 |
0 |
0 |
T113 |
10179 |
19 |
0 |
0 |
T120 |
36314 |
255 |
0 |
0 |
T121 |
9630 |
41 |
0 |
0 |
T122 |
7952 |
7 |
0 |
0 |
T153 |
33541 |
120 |
0 |
0 |
T154 |
70046 |
565 |
0 |
0 |
T155 |
36786 |
276 |
0 |
0 |
T156 |
61442 |
224 |
0 |
0 |
T157 |
100353 |
886 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4840 |
0 |
0 |
T111 |
14008 |
23 |
0 |
0 |
T113 |
10179 |
56 |
0 |
0 |
T120 |
36314 |
227 |
0 |
0 |
T121 |
9630 |
36 |
0 |
0 |
T122 |
7952 |
64 |
0 |
0 |
T124 |
3805 |
58 |
0 |
0 |
T143 |
4031 |
60 |
0 |
0 |
T153 |
33541 |
86 |
0 |
0 |
T154 |
70046 |
382 |
0 |
0 |
T155 |
36786 |
405 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4775 |
0 |
0 |
T111 |
14008 |
75 |
0 |
0 |
T113 |
10179 |
11 |
0 |
0 |
T120 |
36314 |
228 |
0 |
0 |
T121 |
9630 |
7 |
0 |
0 |
T122 |
7952 |
12 |
0 |
0 |
T124 |
3805 |
41 |
0 |
0 |
T140 |
3618 |
39 |
0 |
0 |
T143 |
4031 |
2 |
0 |
0 |
T153 |
33541 |
200 |
0 |
0 |
T154 |
70046 |
347 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5287 |
0 |
0 |
T111 |
14008 |
71 |
0 |
0 |
T113 |
10179 |
77 |
0 |
0 |
T120 |
36314 |
206 |
0 |
0 |
T121 |
9630 |
56 |
0 |
0 |
T122 |
7952 |
49 |
0 |
0 |
T140 |
3618 |
1 |
0 |
0 |
T143 |
4031 |
10 |
0 |
0 |
T153 |
33541 |
255 |
0 |
0 |
T154 |
70046 |
576 |
0 |
0 |
T155 |
36786 |
363 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5093 |
0 |
0 |
T111 |
14008 |
78 |
0 |
0 |
T113 |
10179 |
9 |
0 |
0 |
T120 |
36314 |
249 |
0 |
0 |
T121 |
9630 |
87 |
0 |
0 |
T122 |
7952 |
81 |
0 |
0 |
T124 |
3805 |
5 |
0 |
0 |
T140 |
3618 |
17 |
0 |
0 |
T143 |
4031 |
61 |
0 |
0 |
T153 |
33541 |
108 |
0 |
0 |
T154 |
70046 |
699 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4414 |
0 |
0 |
T111 |
14008 |
191 |
0 |
0 |
T113 |
10179 |
66 |
0 |
0 |
T120 |
36314 |
236 |
0 |
0 |
T121 |
9630 |
70 |
0 |
0 |
T122 |
7952 |
56 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T153 |
33541 |
208 |
0 |
0 |
T154 |
70046 |
259 |
0 |
0 |
T155 |
36786 |
241 |
0 |
0 |
T156 |
61442 |
390 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4632 |
0 |
0 |
T111 |
14008 |
111 |
0 |
0 |
T113 |
10179 |
103 |
0 |
0 |
T120 |
36314 |
250 |
0 |
0 |
T121 |
9630 |
104 |
0 |
0 |
T122 |
7952 |
76 |
0 |
0 |
T124 |
3805 |
26 |
0 |
0 |
T140 |
3618 |
5 |
0 |
0 |
T143 |
4031 |
1 |
0 |
0 |
T153 |
33541 |
94 |
0 |
0 |
T154 |
70046 |
440 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4977 |
0 |
0 |
T111 |
14008 |
111 |
0 |
0 |
T113 |
10179 |
102 |
0 |
0 |
T120 |
36314 |
234 |
0 |
0 |
T121 |
9630 |
50 |
0 |
0 |
T122 |
7952 |
12 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T140 |
3618 |
3 |
0 |
0 |
T143 |
4031 |
41 |
0 |
0 |
T153 |
33541 |
107 |
0 |
0 |
T154 |
70046 |
636 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
5325 |
0 |
0 |
T111 |
14008 |
113 |
0 |
0 |
T113 |
10179 |
13 |
0 |
0 |
T120 |
36314 |
253 |
0 |
0 |
T121 |
9630 |
50 |
0 |
0 |
T122 |
7952 |
38 |
0 |
0 |
T124 |
3805 |
53 |
0 |
0 |
T143 |
4031 |
46 |
0 |
0 |
T153 |
33541 |
121 |
0 |
0 |
T154 |
70046 |
608 |
0 |
0 |
T155 |
36786 |
312 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4721 |
0 |
0 |
T111 |
14008 |
68 |
0 |
0 |
T113 |
10179 |
58 |
0 |
0 |
T120 |
36314 |
226 |
0 |
0 |
T121 |
9630 |
57 |
0 |
0 |
T122 |
7952 |
5 |
0 |
0 |
T124 |
3805 |
7 |
0 |
0 |
T140 |
3618 |
23 |
0 |
0 |
T143 |
4031 |
9 |
0 |
0 |
T153 |
33541 |
199 |
0 |
0 |
T154 |
70046 |
470 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4544 |
0 |
0 |
T111 |
14008 |
36 |
0 |
0 |
T113 |
10179 |
78 |
0 |
0 |
T120 |
36314 |
278 |
0 |
0 |
T121 |
9630 |
70 |
0 |
0 |
T122 |
7952 |
105 |
0 |
0 |
T124 |
3805 |
39 |
0 |
0 |
T143 |
4031 |
56 |
0 |
0 |
T153 |
33541 |
88 |
0 |
0 |
T154 |
70046 |
316 |
0 |
0 |
T155 |
36786 |
366 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2226 |
0 |
0 |
T111 |
14008 |
25 |
0 |
0 |
T113 |
10179 |
26 |
0 |
0 |
T120 |
36314 |
240 |
0 |
0 |
T121 |
9630 |
19 |
0 |
0 |
T122 |
7952 |
20 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T140 |
3618 |
4 |
0 |
0 |
T143 |
4031 |
8 |
0 |
0 |
T153 |
33541 |
24 |
0 |
0 |
T154 |
70046 |
121 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2119 |
0 |
0 |
T111 |
14008 |
39 |
0 |
0 |
T113 |
10179 |
31 |
0 |
0 |
T120 |
36314 |
183 |
0 |
0 |
T121 |
9630 |
11 |
0 |
0 |
T122 |
7952 |
10 |
0 |
0 |
T124 |
3805 |
12 |
0 |
0 |
T143 |
4031 |
5 |
0 |
0 |
T153 |
33541 |
31 |
0 |
0 |
T154 |
70046 |
126 |
0 |
0 |
T155 |
36786 |
74 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2264 |
0 |
0 |
T106 |
8000 |
1 |
0 |
0 |
T111 |
14008 |
31 |
0 |
0 |
T113 |
10179 |
10 |
0 |
0 |
T120 |
36314 |
216 |
0 |
0 |
T121 |
9630 |
16 |
0 |
0 |
T122 |
7952 |
14 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T140 |
3618 |
5 |
0 |
0 |
T153 |
33541 |
42 |
0 |
0 |
T154 |
70046 |
82 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2239 |
0 |
0 |
T106 |
8000 |
1 |
0 |
0 |
T111 |
14008 |
26 |
0 |
0 |
T113 |
10179 |
31 |
0 |
0 |
T120 |
36314 |
234 |
0 |
0 |
T121 |
9630 |
12 |
0 |
0 |
T122 |
7952 |
15 |
0 |
0 |
T124 |
3805 |
5 |
0 |
0 |
T140 |
3618 |
5 |
0 |
0 |
T143 |
4031 |
4 |
0 |
0 |
T153 |
33541 |
30 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2393 |
0 |
0 |
T111 |
14008 |
52 |
0 |
0 |
T113 |
10179 |
41 |
0 |
0 |
T120 |
36314 |
206 |
0 |
0 |
T121 |
9630 |
20 |
0 |
0 |
T122 |
7952 |
15 |
0 |
0 |
T140 |
3618 |
10 |
0 |
0 |
T143 |
4031 |
2 |
0 |
0 |
T153 |
33541 |
27 |
0 |
0 |
T154 |
70046 |
200 |
0 |
0 |
T155 |
36786 |
87 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
4131 |
0 |
0 |
T52 |
0 |
31 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
T128 |
668566 |
0 |
0 |
0 |
T129 |
250803 |
0 |
0 |
0 |
T130 |
655720 |
0 |
0 |
0 |
T131 |
188694 |
0 |
0 |
0 |
T158 |
575392 |
22 |
0 |
0 |
T159 |
0 |
10 |
0 |
0 |
T160 |
0 |
26 |
0 |
0 |
T161 |
0 |
51 |
0 |
0 |
T162 |
0 |
45 |
0 |
0 |
T163 |
0 |
56 |
0 |
0 |
T164 |
0 |
34 |
0 |
0 |
T165 |
0 |
22 |
0 |
0 |
T166 |
1241 |
0 |
0 |
0 |
T167 |
565808 |
0 |
0 |
0 |
T168 |
1151 |
0 |
0 |
0 |
T169 |
1458 |
0 |
0 |
0 |
T170 |
243957 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2150 |
0 |
0 |
T106 |
8000 |
10 |
0 |
0 |
T111 |
14008 |
42 |
0 |
0 |
T113 |
10179 |
13 |
0 |
0 |
T120 |
36314 |
169 |
0 |
0 |
T121 |
9630 |
7 |
0 |
0 |
T122 |
7952 |
4 |
0 |
0 |
T124 |
3805 |
4 |
0 |
0 |
T140 |
3618 |
5 |
0 |
0 |
T143 |
4031 |
8 |
0 |
0 |
T153 |
33541 |
24 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2017 |
0 |
0 |
T111 |
14008 |
16 |
0 |
0 |
T113 |
10179 |
17 |
0 |
0 |
T120 |
36314 |
215 |
0 |
0 |
T121 |
9630 |
20 |
0 |
0 |
T122 |
7952 |
6 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T140 |
3618 |
6 |
0 |
0 |
T143 |
4031 |
5 |
0 |
0 |
T153 |
33541 |
30 |
0 |
0 |
T154 |
70046 |
98 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1875 |
0 |
0 |
T111 |
14008 |
21 |
0 |
0 |
T113 |
10179 |
18 |
0 |
0 |
T120 |
36314 |
212 |
0 |
0 |
T121 |
9630 |
11 |
0 |
0 |
T122 |
7952 |
12 |
0 |
0 |
T124 |
3805 |
4 |
0 |
0 |
T143 |
4031 |
4 |
0 |
0 |
T153 |
33541 |
13 |
0 |
0 |
T154 |
70046 |
84 |
0 |
0 |
T155 |
36786 |
38 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1776 |
0 |
0 |
T111 |
14008 |
31 |
0 |
0 |
T113 |
10179 |
22 |
0 |
0 |
T120 |
36314 |
210 |
0 |
0 |
T121 |
9630 |
7 |
0 |
0 |
T122 |
7952 |
11 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T143 |
4031 |
1 |
0 |
0 |
T153 |
33541 |
29 |
0 |
0 |
T154 |
70046 |
80 |
0 |
0 |
T155 |
36786 |
30 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1938 |
0 |
0 |
T111 |
14008 |
20 |
0 |
0 |
T113 |
10179 |
15 |
0 |
0 |
T120 |
36314 |
230 |
0 |
0 |
T121 |
9630 |
8 |
0 |
0 |
T122 |
7952 |
4 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T143 |
4031 |
9 |
0 |
0 |
T153 |
33541 |
20 |
0 |
0 |
T154 |
70046 |
58 |
0 |
0 |
T155 |
36786 |
27 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1779 |
0 |
0 |
T111 |
14008 |
35 |
0 |
0 |
T113 |
10179 |
21 |
0 |
0 |
T120 |
36314 |
218 |
0 |
0 |
T121 |
9630 |
3 |
0 |
0 |
T122 |
7952 |
7 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T140 |
3618 |
8 |
0 |
0 |
T143 |
4031 |
1 |
0 |
0 |
T153 |
33541 |
34 |
0 |
0 |
T154 |
70046 |
80 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2499 |
0 |
0 |
T111 |
14008 |
52 |
0 |
0 |
T113 |
10179 |
12 |
0 |
0 |
T120 |
36314 |
192 |
0 |
0 |
T121 |
9630 |
12 |
0 |
0 |
T122 |
7952 |
25 |
0 |
0 |
T124 |
3805 |
14 |
0 |
0 |
T140 |
3618 |
2 |
0 |
0 |
T143 |
4031 |
28 |
0 |
0 |
T153 |
33541 |
67 |
0 |
0 |
T154 |
70046 |
147 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1910 |
0 |
0 |
T111 |
14008 |
24 |
0 |
0 |
T113 |
10179 |
28 |
0 |
0 |
T120 |
36314 |
235 |
0 |
0 |
T121 |
9630 |
9 |
0 |
0 |
T122 |
7952 |
5 |
0 |
0 |
T143 |
4031 |
3 |
0 |
0 |
T153 |
33541 |
16 |
0 |
0 |
T154 |
70046 |
69 |
0 |
0 |
T155 |
36786 |
44 |
0 |
0 |
T156 |
61442 |
19 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2924 |
0 |
0 |
T111 |
14008 |
60 |
0 |
0 |
T113 |
10179 |
33 |
0 |
0 |
T120 |
36314 |
248 |
0 |
0 |
T121 |
9630 |
18 |
0 |
0 |
T122 |
7952 |
5 |
0 |
0 |
T124 |
3805 |
13 |
0 |
0 |
T140 |
3618 |
11 |
0 |
0 |
T143 |
4031 |
26 |
0 |
0 |
T153 |
33541 |
43 |
0 |
0 |
T154 |
70046 |
247 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
2145 |
0 |
0 |
T111 |
14008 |
34 |
0 |
0 |
T113 |
10179 |
22 |
0 |
0 |
T120 |
36314 |
239 |
0 |
0 |
T121 |
9630 |
24 |
0 |
0 |
T122 |
7952 |
5 |
0 |
0 |
T124 |
3805 |
3 |
0 |
0 |
T140 |
3618 |
6 |
0 |
0 |
T143 |
4031 |
5 |
0 |
0 |
T153 |
33541 |
36 |
0 |
0 |
T154 |
70046 |
117 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1914 |
0 |
0 |
T111 |
14008 |
24 |
0 |
0 |
T113 |
10179 |
18 |
0 |
0 |
T120 |
36314 |
222 |
0 |
0 |
T121 |
9630 |
12 |
0 |
0 |
T122 |
7952 |
2 |
0 |
0 |
T124 |
3805 |
2 |
0 |
0 |
T143 |
4031 |
4 |
0 |
0 |
T153 |
33541 |
36 |
0 |
0 |
T154 |
70046 |
71 |
0 |
0 |
T155 |
36786 |
44 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1835 |
0 |
0 |
T111 |
14008 |
11 |
0 |
0 |
T113 |
10179 |
17 |
0 |
0 |
T120 |
36314 |
230 |
0 |
0 |
T121 |
9630 |
18 |
0 |
0 |
T122 |
7952 |
4 |
0 |
0 |
T124 |
3805 |
2 |
0 |
0 |
T143 |
4031 |
9 |
0 |
0 |
T153 |
33541 |
14 |
0 |
0 |
T154 |
70046 |
85 |
0 |
0 |
T155 |
36786 |
38 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1644 |
0 |
0 |
T111 |
14008 |
22 |
0 |
0 |
T113 |
10179 |
18 |
0 |
0 |
T120 |
36314 |
178 |
0 |
0 |
T121 |
9630 |
12 |
0 |
0 |
T122 |
7952 |
6 |
0 |
0 |
T124 |
3805 |
1 |
0 |
0 |
T143 |
4031 |
8 |
0 |
0 |
T153 |
33541 |
24 |
0 |
0 |
T154 |
70046 |
96 |
0 |
0 |
T155 |
36786 |
36 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1600 |
0 |
0 |
T111 |
14008 |
20 |
0 |
0 |
T113 |
10179 |
17 |
0 |
0 |
T120 |
36314 |
211 |
0 |
0 |
T121 |
9630 |
7 |
0 |
0 |
T122 |
7952 |
3 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T143 |
4031 |
2 |
0 |
0 |
T153 |
33541 |
20 |
0 |
0 |
T154 |
70046 |
53 |
0 |
0 |
T155 |
36786 |
41 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1828 |
0 |
0 |
T111 |
14008 |
19 |
0 |
0 |
T113 |
10179 |
13 |
0 |
0 |
T120 |
36314 |
209 |
0 |
0 |
T121 |
9630 |
20 |
0 |
0 |
T122 |
7952 |
3 |
0 |
0 |
T124 |
3805 |
6 |
0 |
0 |
T140 |
3618 |
7 |
0 |
0 |
T143 |
4031 |
5 |
0 |
0 |
T153 |
33541 |
7 |
0 |
0 |
T154 |
70046 |
80 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460293511 |
1923 |
0 |
0 |
T111 |
14008 |
34 |
0 |
0 |
T113 |
10179 |
14 |
0 |
0 |
T120 |
36314 |
232 |
0 |
0 |
T121 |
9630 |
6 |
0 |
0 |
T122 |
7952 |
9 |
0 |
0 |
T124 |
3805 |
4 |
0 |
0 |
T140 |
3618 |
1 |
0 |
0 |
T153 |
33541 |
17 |
0 |
0 |
T154 |
70046 |
67 |
0 |
0 |
T155 |
36786 |
48 |
0 |
0 |