Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3441339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4254358

1

T1

13

T2

905

T3

418

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4216221	1			T1	1		T2	45		T3	441
values[0x0]	1738191	1			T1	14		T2	470		T3	217
values[0x1]	1741285	1			T1	5		T2	416		T3	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2450440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5245257

1

T1

13

T2

910

T3

549

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27598	1			T2	4		T3	2		T6	6
valid_sources[0x01]	26954	1			T2	5		T3	1		T4	2
valid_sources[0x02]	27814	1			T2	5		T3	3		T6	4
valid_sources[0x03]	26894	1			T2	3		T3	5		T6	7
valid_sources[0x04]	29007	1			T2	6		T3	7		T4	3
valid_sources[0x05]	29063	1			T3	8		T4	26		T6	8
valid_sources[0x06]	29341	1			T2	4		T3	4		T4	11
valid_sources[0x07]	30255	1			T2	5		T3	2		T6	8
valid_sources[0x08]	27457	1			T2	1		T3	4		T4	19
valid_sources[0x09]	29696	1			T2	2		T4	3		T6	7
valid_sources[0x0a]	31649	1			T2	5		T3	1		T6	5
valid_sources[0x0b]	29561	1			T2	2		T3	4		T4	4
valid_sources[0x0c]	29975	1			T2	2		T3	3		T4	2
valid_sources[0x0d]	28494	1			T2	8		T3	2		T4	11
valid_sources[0x0e]	27254	1			T2	2		T3	6		T6	6
valid_sources[0x0f]	27442	1			T2	8		T3	3		T6	4
valid_sources[0x10]	30379	1			T2	4		T3	4		T6	6
valid_sources[0x11]	31188	1			T2	1		T3	1		T4	3
valid_sources[0x12]	30253	1			T2	5		T3	3		T6	7
valid_sources[0x13]	28268	1			T2	1		T3	3		T4	46
valid_sources[0x14]	27792	1			T2	4		T3	5		T6	4
valid_sources[0x15]	31223	1			T2	4		T3	2		T6	12
valid_sources[0x16]	28526	1			T2	8		T3	3		T6	3
valid_sources[0x17]	30197	1			T2	8		T3	4		T6	8
valid_sources[0x18]	31773	1			T2	8		T3	5		T4	11
valid_sources[0x19]	28272	1			T2	8		T3	2		T6	9
valid_sources[0x1a]	34271	1			T2	2		T3	1		T4	33
valid_sources[0x1b]	28232	1			T2	5		T3	1		T6	6
valid_sources[0x1c]	31749	1			T2	2		T3	3		T6	5
valid_sources[0x1d]	26406	1			T2	7		T3	7		T6	2
valid_sources[0x1e]	30442	1			T2	4		T3	2		T6	8
valid_sources[0x1f]	28330	1			T2	3		T3	5		T4	24
valid_sources[0x20]	28033	1			T2	3		T3	5		T4	6
valid_sources[0x21]	58915	1			T2	7		T3	3		T4	2
valid_sources[0x22]	29710	1			T2	3		T3	8		T4	13
valid_sources[0x23]	32119	1			T2	2		T3	2		T4	12
valid_sources[0x24]	30963	1			T2	9		T3	3		T6	7
valid_sources[0x25]	26846	1			T2	5		T3	3		T6	3
valid_sources[0x26]	32320	1			T2	4		T3	6		T4	59
valid_sources[0x27]	33016	1			T2	1		T3	3		T4	2
valid_sources[0x28]	28300	1			T2	5		T3	1		T6	1
valid_sources[0x29]	32492	1			T2	5		T3	1		T6	7
valid_sources[0x2a]	27490	1			T2	2		T3	1		T6	8
valid_sources[0x2b]	30333	1			T2	4		T3	1		T4	2
valid_sources[0x2c]	29238	1			T2	7		T3	3		T4	21
valid_sources[0x2d]	31275	1			T2	4		T3	2		T4	6
valid_sources[0x2e]	52065	1			T2	2		T3	5		T6	7
valid_sources[0x2f]	32969	1			T2	4		T3	8		T6	4
valid_sources[0x30]	30022	1			T2	3		T3	4		T6	5
valid_sources[0x31]	27984	1			T2	5		T3	4		T6	2
valid_sources[0x32]	36745	1			T2	2		T3	6		T4	9
valid_sources[0x33]	30587	1			T2	1		T3	1		T4	2
valid_sources[0x34]	27495	1			T2	6		T3	7		T4	5
valid_sources[0x35]	29724	1			T2	6		T3	3		T4	1
valid_sources[0x36]	27863	1			T2	3		T3	4		T6	10
valid_sources[0x37]	31235	1			T2	1		T3	3		T6	3
valid_sources[0x38]	30587	1			T2	6		T3	1		T6	6
valid_sources[0x39]	27940	1			T2	2		T3	8		T4	14
valid_sources[0x3a]	29833	1			T2	1		T4	20		T6	9
valid_sources[0x3b]	29722	1			T2	7		T3	7		T4	25
valid_sources[0x3c]	29636	1			T2	5		T3	1		T6	5
valid_sources[0x3d]	27544	1			T2	2		T3	4		T4	1
valid_sources[0x3e]	28798	1			T2	4		T3	4		T6	5
valid_sources[0x3f]	27836	1			T2	4		T3	2		T4	31
valid_sources[0x40]	28845	1			T2	2		T3	4		T6	7
valid_sources[0x41]	31502	1			T2	2		T3	2		T6	6
valid_sources[0x42]	29302	1			T2	4		T3	3		T6	2
valid_sources[0x43]	30197	1			T2	3		T3	3		T6	10
valid_sources[0x44]	34208	1			T2	1		T3	6		T4	1
valid_sources[0x45]	31415	1			T2	3		T3	4		T6	6
valid_sources[0x46]	31553	1			T2	1		T3	1		T4	3
valid_sources[0x47]	28814	1			T2	2		T3	3		T6	1
valid_sources[0x48]	28151	1			T2	8		T3	1		T6	2
valid_sources[0x49]	28909	1			T2	2		T3	1		T6	6
valid_sources[0x4a]	29971	1			T2	7		T3	3		T6	4
valid_sources[0x4b]	27370	1			T2	2		T3	5		T6	5
valid_sources[0x4c]	30033	1			T2	1		T3	3		T6	3
valid_sources[0x4d]	28663	1			T2	1		T3	4		T6	3
valid_sources[0x4e]	27237	1			T2	2		T3	5		T4	4
valid_sources[0x4f]	31631	1			T2	4		T3	3		T4	1
valid_sources[0x50]	32315	1			T2	3		T3	5		T6	9
valid_sources[0x51]	30843	1			T2	4		T3	1		T9	77
valid_sources[0x52]	31225	1			T2	3		T3	1		T6	6
valid_sources[0x53]	29735	1			T3	4		T6	6		T9	78
valid_sources[0x54]	26029	1			T2	4		T3	3		T4	15
valid_sources[0x55]	26325	1			T2	3		T3	4		T6	2
valid_sources[0x56]	29121	1			T2	3		T3	3		T6	7
valid_sources[0x57]	25612	1			T2	3		T3	1		T6	6
valid_sources[0x58]	30217	1			T2	5		T3	5		T6	3
valid_sources[0x59]	29676	1			T2	5		T3	5		T4	2
valid_sources[0x5a]	29029	1			T2	6		T3	5		T6	9
valid_sources[0x5b]	33287	1			T2	1		T3	2		T4	8
valid_sources[0x5c]	29614	1			T2	2		T3	3		T6	8
valid_sources[0x5d]	27579	1			T2	6		T3	3		T6	4
valid_sources[0x5e]	31728	1			T2	4		T3	2		T4	7
valid_sources[0x5f]	27431	1			T2	2		T3	1		T4	2
valid_sources[0x60]	28784	1			T2	3		T3	6		T6	4
valid_sources[0x61]	28886	1			T2	2		T3	4		T6	4
valid_sources[0x62]	29725	1			T2	4		T3	5		T6	4
valid_sources[0x63]	35835	1			T2	2		T3	4		T6	3
valid_sources[0x64]	29818	1			T2	2		T3	2		T6	7
valid_sources[0x65]	29474	1			T2	5		T4	5		T6	6
valid_sources[0x66]	28080	1			T2	2		T3	5		T4	4
valid_sources[0x67]	37658	1			T2	7		T3	1		T4	14
valid_sources[0x68]	30514	1			T2	2		T3	4		T6	2
valid_sources[0x69]	30813	1			T2	4		T4	11		T6	6
valid_sources[0x6a]	28973	1			T2	5		T3	2		T6	6
valid_sources[0x6b]	37616	1			T2	3		T3	2		T6	7
valid_sources[0x6c]	25757	1			T2	5		T3	1		T4	11
valid_sources[0x6d]	29008	1			T2	1		T3	3		T6	5
valid_sources[0x6e]	27579	1			T2	3		T3	3		T6	9
valid_sources[0x6f]	31713	1			T2	3		T3	5		T6	12
valid_sources[0x70]	28545	1			T2	5		T3	3		T6	11
valid_sources[0x71]	28428	1			T2	6		T3	5		T4	24
valid_sources[0x72]	33732	1			T2	2		T3	4		T6	4
valid_sources[0x73]	30322	1			T2	6		T3	7		T4	17
valid_sources[0x74]	28303	1			T2	1		T3	3		T6	2
valid_sources[0x75]	29246	1			T2	3		T3	5		T6	8
valid_sources[0x76]	29238	1			T3	1		T4	8		T6	6
valid_sources[0x77]	27749	1			T2	7		T3	4		T4	3
valid_sources[0x78]	29179	1			T2	3		T3	4		T6	9
valid_sources[0x79]	29720	1			T2	3		T6	4		T9	81
valid_sources[0x7a]	26971	1			T2	3		T3	6		T4	3
valid_sources[0x7b]	27886	1			T2	4		T3	1		T4	13
valid_sources[0x7c]	26986	1			T2	7		T3	5		T6	4
valid_sources[0x7d]	34641	1			T2	2		T3	4		T4	6
valid_sources[0x7e]	27828	1			T2	7		T3	1		T6	6
valid_sources[0x7f]	27062	1			T2	8		T3	2		T6	2
valid_sources[0x80]	31198	1			T2	3		T6	2		T9	76

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1094236

1

T2

22

T3

106

T4

127

values[0x0]

all_enables

biggest_size

1591547

1

T1

10

T2

467

T3

168

values[0x1]

all_enables

biggest_size

1568575

1

T1

3

T2

416

T3

144