Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3464047

1

T1

7

T2

26

T3

433

full_word

4253534

1

T1

13

T2

905

T3

418

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7717141	1			T1	20		T2	931		T3	851
auto[TlIntgErrCmd]	158	1			T101	7		T102	9		T114	9
auto[TlIntgErrData]	142	1			T100	6		T101	13		T102	6
auto[TlIntgErrBoth]	140	1			T100	4		T101	10		T102	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4218124

1

T1

1

T2

45

T3

441

auto[1]

3499457

1

T1

19

T2

886

T3

410

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3123586	1			T1	1		T2	23		T3	335
auto[TlIntgErrNone]	partial	auto[1]	340061	1			T1	6		T2	3		T3	98
auto[TlIntgErrNone]	full_word	auto[0]	1094332	1			T2	22		T3	106		T4	127
auto[TlIntgErrNone]	full_word	auto[1]	3159162	1			T1	13		T2	883		T3	312
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T101	2		T102	4		T114	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T101	5		T102	4		T114	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T102	1		T174	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T116	1		T115	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T100	1		T101	3		T102	2
auto[TlIntgErrData]	partial	auto[1]	65	1			T100	3		T101	8		T102	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T100	2		T114	1		T174	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T101	2		T102	1		T114	2
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T100	1		T101	4		T102	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T100	2		T101	5		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T100	1		T174	1		T176	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T101	1		T115	1		T175	1