Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	2885853	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	2885853	0	0
T2	37724	832	0	0
T3	27645	0	0	0
T4	54209	1663	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	0	0	0
T9	434100	14149	0	0
T10	12286	1665	0	0
T11	557878	13329	0	0
T12	0	1668	0	0
T13	0	12475	0	0
T14	0	18304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	3247744	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	3247744	0	0
T2	37724	832	0	0
T3	27645	0	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	0	0	0
T9	434100	17971	0	0
T10	12286	834	0	0
T11	557878	20683	0	0
T12	0	837	0	0
T13	0	8320	0	0
T14	0	17608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	200539	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	200539	0	0
T3	27645	85	0	0
T4	54209	0	0	0
T5	198336	0	0	0
T6	18861	0	0	0
T7	33783	0	0	0
T8	11473	2	0	0
T9	434100	913	0	0
T10	12286	0	0	0
T11	557878	248	0	0
T12	12063	0	0	0
T13	0	1052	0	0
T14	0	1110	0	0
T15	0	625	0	0
T22	0	33	0	0
T26	0	100	0	0
T31	0	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	484998	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	484998	0	0
T3	27645	85	0	0
T4	54209	0	0	0
T5	198336	0	0	0
T6	18861	0	0	0
T7	33783	0	0	0
T8	11473	14	0	0
T9	434100	2724	0	0
T10	12286	0	0	0
T11	557878	802	0	0
T12	12063	0	0	0
T13	0	1052	0	0
T14	0	3359	0	0
T15	0	625	0	0
T22	0	98	0	0
T26	0	100	0	0
T31	0	228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	6042097	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	6042097	0	0
T1	2317	20	0	0
T2	37724	99	0	0
T3	27645	769	0	0
T4	54209	317	0	0
T5	198336	6094	0	0
T6	18861	702	0	0
T7	33783	207	0	0
T8	11473	134	0	0
T9	434100	9549	0	0
T10	12286	509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428618852	13166172	0	0
DepthKnown_A	428618852	428482184	0	0
RvalidKnown_A	428618852	428482184	0	0
WreadyKnown_A	428618852	428482184	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	13166172	0	0
T1	2317	94	0	0
T2	37724	99	0	0
T3	27645	766	0	0
T4	54209	317	0	0
T5	198336	6094	0	0
T6	18861	702	0	0
T7	33783	207	0	0
T8	11473	575	0	0
T9	434100	27556	0	0
T10	12286	2299	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428618852	428482184	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0