Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T3,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Unreachable
1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T13
1	0	Covered	T9,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T9,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	742721836	583059955	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	742721836	3856211	0	0
GntImpliesValid_A	742721836	3856211	0	0
GrantKnown_A	742721836	583059955	0	0
IdxKnown_A	742721836	583059955	0	0
IndexIsCorrect_A	742721836	3856211	0	0
LockArbDecision_A	742721836	0	0	0
NoReadyValidNoGrant_A	742721836	0	0	0
ReadyAndValidImplyGrant_A	742721836	3856211	0	0
ReqAndReadyImplyGrant_A	742721836	3856211	0	0
ReqImpliesValid_A	742721836	3856211	0	0
ReqStaysHighUntilGranted0_M	742721836	0	0	0
RoundRobin_A	742721836	3	0	976
ValidKnown_A	742721836	583059955	0	0
gen_data_port_assertion.DataFlow_A	742721836	3856211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	583059955	0	0
T1	2749	2683	0	0
T2	218296	127919	0	0
T3	76637	51638	0	0
T4	105315	79678	0	0
T5	579968	389102	0	0
T6	25393	21736	0	0
T7	86797	57742	0	0
T8	15979	13161	0	0
T9	671436	1608530	0	0
T10	63830	37993	0	0
T11	692494	689313	0	0
T12	0	128	0	0
T13	0	671825	0	0
T14	0	841910	0	0
T15	0	59848	0	0
T28	0	93824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	583059955	0	0
T1	2749	2683	0	0
T2	218296	127919	0	0
T3	76637	51638	0	0
T4	105315	79678	0	0
T5	579968	389102	0	0
T6	25393	21736	0	0
T7	86797	57742	0	0
T8	15979	13161	0	0
T9	671436	1608530	0	0
T10	63830	37993	0	0
T11	692494	689313	0	0
T12	0	128	0	0
T13	0	671825	0	0
T14	0	841910	0	0
T15	0	59848	0	0
T28	0	93824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	583059955	0	0
T1	2749	2683	0	0
T2	218296	127919	0	0
T3	76637	51638	0	0
T4	105315	79678	0	0
T5	579968	389102	0	0
T6	25393	21736	0	0
T7	86797	57742	0	0
T8	15979	13161	0	0
T9	671436	1608530	0	0
T10	63830	37993	0	0
T11	692494	689313	0	0
T12	0	128	0	0
T13	0	671825	0	0
T14	0	841910	0	0
T15	0	59848	0	0
T28	0	93824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3	0	976
T46	580371	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	118435	0	0	1
T50	64456	0	0	1
T51	117248	0	0	1
T52	72538	0	0	1
T53	55718	0	0	1
T54	2274	0	0	1
T55	214982	0	0	1
T56	77197	0	0	1
T57	245981	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	583059955	0	0
T1	2749	2683	0	0
T2	218296	127919	0	0
T3	76637	51638	0	0
T4	105315	79678	0	0
T5	579968	389102	0	0
T6	25393	21736	0	0
T7	86797	57742	0	0
T8	15979	13161	0	0
T9	671436	1608530	0	0
T10	63830	37993	0	0
T11	692494	689313	0	0
T12	0	128	0	0
T13	0	671825	0	0
T14	0	841910	0	0
T15	0	59848	0	0
T28	0	93824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742721836	3856211	0	0
T2	37724	832	0	0
T3	52141	805	0	0
T4	79762	832	0	0
T5	389152	832	0	0
T6	22127	832	0	0
T7	60290	0	0	0
T8	13726	90	0	0
T9	671436	17433	0	0
T10	63830	832	0	0
T11	1942866	12884	0	0
T12	2222	832	0	0
T13	678294	5649	0	0
T14	846535	6327	0	0
T15	520285	3294	0	0
T16	0	1128	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	7439	0	0
T31	0	3085	0	0
T37	0	875	0	0
T44	0	4147	0	0
T45	0	8	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T3,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Unreachable
1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	158171753	30117848	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	158171753	668351	0	0
GntImpliesValid_A	158171753	668351	0	0
GrantKnown_A	158171753	30117848	0	0
IdxKnown_A	158171753	30117848	0	0
IndexIsCorrect_A	158171753	668351	0	0
LockArbDecision_A	158171753	0	0	0
NoReadyValidNoGrant_A	158171753	0	0	0
ReadyAndValidImplyGrant_A	158171753	668351	0	0
ReqAndReadyImplyGrant_A	158171753	668351	0	0
ReqImpliesValid_A	158171753	668351	0	0
ReqStaysHighUntilGranted0_M	158171753	0	0	0
RoundRobin_A	158171753	0	0	0
ValidKnown_A	158171753	30117848	0	0
gen_data_port_assertion.DataFlow_A	158171753	668351	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	30117848	0	0
T1	432	432	0	0
T2	90286	0	0	0
T3	24496	24056	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	24048	0	0
T8	2253	1768	0	0
T9	118668	306144	0	0
T10	25772	0	0	0
T11	0	13096	0	0
T13	0	403728	0	0
T14	0	353488	0	0
T15	0	59848	0	0
T28	0	93824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	30117848	0	0
T1	432	432	0	0
T2	90286	0	0	0
T3	24496	24056	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	24048	0	0
T8	2253	1768	0	0
T9	118668	306144	0	0
T10	25772	0	0	0
T11	0	13096	0	0
T13	0	403728	0	0
T14	0	353488	0	0
T15	0	59848	0	0
T28	0	93824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	30117848	0	0
T1	432	432	0	0
T2	90286	0	0	0
T3	24496	24056	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	24048	0	0
T8	2253	1768	0	0
T9	118668	306144	0	0
T10	25772	0	0	0
T11	0	13096	0	0
T13	0	403728	0	0
T14	0	353488	0	0
T15	0	59848	0	0
T28	0	93824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	30117848	0	0
T1	432	432	0	0
T2	90286	0	0	0
T3	24496	24056	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	24048	0	0
T8	2253	1768	0	0
T9	118668	306144	0	0
T10	25772	0	0	0
T11	0	13096	0	0
T13	0	403728	0	0
T14	0	353488	0	0
T15	0	59848	0	0
T28	0	93824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	668351	0	0
T3	24496	531	0	0
T4	25553	0	0	0
T5	190816	0	0	0
T6	3266	0	0	0
T7	26507	0	0	0
T8	2253	46	0	0
T9	118668	3654	0	0
T10	25772	0	0	0
T11	692494	635	0	0
T12	1111	0	0	0
T13	0	4337	0	0
T14	0	3445	0	0
T15	0	2702	0	0
T16	0	1128	0	0
T28	0	3963	0	0
T44	0	4147	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T13
1	0	Covered	T9,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T9,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T11,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	158171753	126652781	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	158171753	879976	0	0
GntImpliesValid_A	158171753	879976	0	0
GrantKnown_A	158171753	126652781	0	0
IdxKnown_A	158171753	126652781	0	0
IndexIsCorrect_A	158171753	879976	0	0
LockArbDecision_A	158171753	0	0	0
NoReadyValidNoGrant_A	158171753	0	0	0
ReadyAndValidImplyGrant_A	158171753	879976	0	0
ReqAndReadyImplyGrant_A	158171753	879976	0	0
ReqImpliesValid_A	158171753	879976	0	0
ReqStaysHighUntilGranted0_M	158171753	0	0	0
RoundRobin_A	158171753	0	0	0
ValidKnown_A	158171753	126652781	0	0
gen_data_port_assertion.DataFlow_A	158171753	879976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	126652781	0	0
T2	90286	90286	0	0
T3	24496	0	0	0
T4	25553	25553	0	0
T5	190816	190816	0	0
T6	3266	2960	0	0
T7	26507	0	0	0
T8	2253	0	0	0
T9	118668	868383	0	0
T10	25772	25772	0	0
T11	692494	676217	0	0
T12	0	128	0	0
T13	0	268097	0	0
T14	0	488422	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	126652781	0	0
T2	90286	90286	0	0
T3	24496	0	0	0
T4	25553	25553	0	0
T5	190816	190816	0	0
T6	3266	2960	0	0
T7	26507	0	0	0
T8	2253	0	0	0
T9	118668	868383	0	0
T10	25772	25772	0	0
T11	692494	676217	0	0
T12	0	128	0	0
T13	0	268097	0	0
T14	0	488422	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	126652781	0	0
T2	90286	90286	0	0
T3	24496	0	0	0
T4	25553	25553	0	0
T5	190816	190816	0	0
T6	3266	2960	0	0
T7	26507	0	0	0
T8	2253	0	0	0
T9	118668	868383	0	0
T10	25772	25772	0	0
T11	692494	676217	0	0
T12	0	128	0	0
T13	0	268097	0	0
T14	0	488422	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	126652781	0	0
T2	90286	90286	0	0
T3	24496	0	0	0
T4	25553	25553	0	0
T5	190816	190816	0	0
T6	3266	2960	0	0
T7	26507	0	0	0
T8	2253	0	0	0
T9	118668	868383	0	0
T10	25772	25772	0	0
T11	692494	676217	0	0
T12	0	128	0	0
T13	0	268097	0	0
T14	0	488422	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158171753	879976	0	0
T9	118668	2630	0	0
T10	25772	0	0	0
T11	692494	2677	0	0
T12	1111	0	0	0
T13	678294	1312	0	0
T14	846535	2882	0	0
T15	520285	592	0	0
T22	134942	137	0	0
T23	5966	0	0	0
T24	100657	0	0	0
T28	0	3476	0	0
T31	0	3085	0	0
T37	0	875	0	0
T45	0	8	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	426378330	426289326	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	426378330	2307884	0	0
GntImpliesValid_A	426378330	2307884	0	0
GrantKnown_A	426378330	426289326	0	0
IdxKnown_A	426378330	426289326	0	0
IndexIsCorrect_A	426378330	2307884	0	0
LockArbDecision_A	426378330	0	0	0
NoReadyValidNoGrant_A	426378330	0	0	0
ReadyAndValidImplyGrant_A	426378330	2307884	0	0
ReqAndReadyImplyGrant_A	426378330	2307884	0	0
ReqImpliesValid_A	426378330	2307884	0	0
ReqStaysHighUntilGranted0_M	426378330	0	0	0
RoundRobin_A	426378330	3	0	976
ValidKnown_A	426378330	426289326	0	0
gen_data_port_assertion.DataFlow_A	426378330	2307884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	426289326	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	426289326	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	426289326	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	3	0	976
T46	580371	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	118435	0	0	1
T50	64456	0	0	1
T51	117248	0	0	1
T52	72538	0	0	1
T53	55718	0	0	1
T54	2274	0	0	1
T55	214982	0	0	1
T56	77197	0	0	1
T57	245981	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	426289326	0	0
T1	2317	2251	0	0
T2	37724	37633	0	0
T3	27645	27582	0	0
T4	54209	54125	0	0
T5	198336	198286	0	0
T6	18861	18776	0	0
T7	33783	33694	0	0
T8	11473	11393	0	0
T9	434100	434003	0	0
T10	12286	12221	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426378330	2307884	0	0
T2	37724	832	0	0
T3	27645	274	0	0
T4	54209	832	0	0
T5	198336	832	0	0
T6	18861	832	0	0
T7	33783	0	0	0
T8	11473	44	0	0
T9	434100	11149	0	0
T10	12286	832	0	0
T11	557878	9572	0	0
T12	0	832	0	0