Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4179 |
0 |
0 |
T97 |
11980 |
191 |
0 |
0 |
T98 |
6428 |
257 |
0 |
0 |
T99 |
3635 |
9 |
0 |
0 |
T100 |
10345 |
2 |
0 |
0 |
T101 |
29923 |
1 |
0 |
0 |
T102 |
70122 |
5 |
0 |
0 |
T103 |
16553 |
248 |
0 |
0 |
T112 |
9083 |
3 |
0 |
0 |
T113 |
5139 |
2 |
0 |
0 |
T114 |
29662 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1334 |
0 |
0 |
T97 |
11980 |
3 |
0 |
0 |
T102 |
70122 |
81 |
0 |
0 |
T111 |
10096 |
14 |
0 |
0 |
T147 |
11687 |
28 |
0 |
0 |
T148 |
7341 |
19 |
0 |
0 |
T155 |
4859 |
7 |
0 |
0 |
T156 |
6551 |
12 |
0 |
0 |
T157 |
12038 |
7 |
0 |
0 |
T158 |
12737 |
49 |
0 |
0 |
T159 |
91046 |
213 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1276 |
0 |
0 |
T102 |
70122 |
73 |
0 |
0 |
T111 |
10096 |
13 |
0 |
0 |
T147 |
11687 |
11 |
0 |
0 |
T148 |
7341 |
38 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
34 |
0 |
0 |
T157 |
12038 |
7 |
0 |
0 |
T158 |
12737 |
29 |
0 |
0 |
T159 |
91046 |
223 |
0 |
0 |
T160 |
15451 |
18 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1743 |
0 |
0 |
T102 |
70122 |
134 |
0 |
0 |
T111 |
10096 |
33 |
0 |
0 |
T147 |
11687 |
12 |
0 |
0 |
T148 |
7341 |
9 |
0 |
0 |
T155 |
4859 |
11 |
0 |
0 |
T156 |
6551 |
13 |
0 |
0 |
T157 |
12038 |
10 |
0 |
0 |
T158 |
12737 |
44 |
0 |
0 |
T159 |
91046 |
266 |
0 |
0 |
T160 |
15451 |
31 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
7405 |
0 |
0 |
T102 |
70122 |
1156 |
0 |
0 |
T111 |
10096 |
20 |
0 |
0 |
T128 |
4528 |
138 |
0 |
0 |
T147 |
11687 |
12 |
0 |
0 |
T148 |
7341 |
49 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
18 |
0 |
0 |
T157 |
12038 |
272 |
0 |
0 |
T158 |
12737 |
78 |
0 |
0 |
T159 |
91046 |
274 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
9559 |
0 |
0 |
T102 |
70122 |
1497 |
0 |
0 |
T111 |
10096 |
128 |
0 |
0 |
T128 |
4528 |
126 |
0 |
0 |
T147 |
11687 |
52 |
0 |
0 |
T148 |
7341 |
20 |
0 |
0 |
T155 |
4859 |
3 |
0 |
0 |
T156 |
6551 |
7 |
0 |
0 |
T157 |
12038 |
260 |
0 |
0 |
T158 |
12737 |
57 |
0 |
0 |
T159 |
91046 |
221 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
9130 |
0 |
0 |
T102 |
70122 |
1490 |
0 |
0 |
T111 |
10096 |
119 |
0 |
0 |
T128 |
4528 |
114 |
0 |
0 |
T147 |
11687 |
12 |
0 |
0 |
T148 |
7341 |
8 |
0 |
0 |
T155 |
4859 |
148 |
0 |
0 |
T156 |
6551 |
31 |
0 |
0 |
T157 |
12038 |
150 |
0 |
0 |
T158 |
12737 |
8 |
0 |
0 |
T159 |
91046 |
215 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
8852 |
0 |
0 |
T102 |
70122 |
1649 |
0 |
0 |
T111 |
10096 |
131 |
0 |
0 |
T128 |
4528 |
112 |
0 |
0 |
T147 |
11687 |
19 |
0 |
0 |
T148 |
7341 |
12 |
0 |
0 |
T155 |
4859 |
147 |
0 |
0 |
T156 |
6551 |
16 |
0 |
0 |
T157 |
12038 |
253 |
0 |
0 |
T158 |
12737 |
35 |
0 |
0 |
T159 |
91046 |
189 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
8899 |
0 |
0 |
T102 |
70122 |
1106 |
0 |
0 |
T111 |
10096 |
131 |
0 |
0 |
T128 |
4528 |
88 |
0 |
0 |
T147 |
11687 |
22 |
0 |
0 |
T148 |
7341 |
25 |
0 |
0 |
T155 |
4859 |
136 |
0 |
0 |
T156 |
6551 |
10 |
0 |
0 |
T157 |
12038 |
10 |
0 |
0 |
T158 |
12737 |
14 |
0 |
0 |
T159 |
91046 |
243 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
7894 |
0 |
0 |
T97 |
11980 |
5 |
0 |
0 |
T102 |
70122 |
1181 |
0 |
0 |
T111 |
10096 |
15 |
0 |
0 |
T147 |
11687 |
42 |
0 |
0 |
T148 |
7341 |
5 |
0 |
0 |
T155 |
4859 |
1 |
0 |
0 |
T156 |
6551 |
15 |
0 |
0 |
T157 |
12038 |
255 |
0 |
0 |
T158 |
12737 |
116 |
0 |
0 |
T159 |
91046 |
236 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
8088 |
0 |
0 |
T102 |
70122 |
1453 |
0 |
0 |
T111 |
10096 |
111 |
0 |
0 |
T128 |
4528 |
5 |
0 |
0 |
T147 |
11687 |
36 |
0 |
0 |
T148 |
7341 |
27 |
0 |
0 |
T155 |
4859 |
143 |
0 |
0 |
T156 |
6551 |
5 |
0 |
0 |
T157 |
12038 |
128 |
0 |
0 |
T158 |
12737 |
22 |
0 |
0 |
T159 |
91046 |
228 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
7942 |
0 |
0 |
T102 |
70122 |
974 |
0 |
0 |
T111 |
10096 |
137 |
0 |
0 |
T128 |
4528 |
6 |
0 |
0 |
T129 |
4166 |
2 |
0 |
0 |
T147 |
11687 |
19 |
0 |
0 |
T155 |
4859 |
101 |
0 |
0 |
T157 |
12038 |
12 |
0 |
0 |
T158 |
12737 |
68 |
0 |
0 |
T159 |
91046 |
245 |
0 |
0 |
T160 |
15451 |
153 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4158 |
0 |
0 |
T102 |
70122 |
537 |
0 |
0 |
T111 |
10096 |
39 |
0 |
0 |
T128 |
4528 |
49 |
0 |
0 |
T147 |
11687 |
39 |
0 |
0 |
T148 |
7341 |
71 |
0 |
0 |
T155 |
4859 |
7 |
0 |
0 |
T156 |
6551 |
6 |
0 |
0 |
T157 |
12038 |
107 |
0 |
0 |
T158 |
12737 |
8 |
0 |
0 |
T159 |
91046 |
201 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3749 |
0 |
0 |
T102 |
70122 |
276 |
0 |
0 |
T111 |
10096 |
49 |
0 |
0 |
T147 |
11687 |
17 |
0 |
0 |
T148 |
7341 |
9 |
0 |
0 |
T155 |
4859 |
58 |
0 |
0 |
T156 |
6551 |
8 |
0 |
0 |
T157 |
12038 |
104 |
0 |
0 |
T158 |
12737 |
17 |
0 |
0 |
T159 |
91046 |
212 |
0 |
0 |
T161 |
15805 |
8 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3867 |
0 |
0 |
T102 |
70122 |
390 |
0 |
0 |
T111 |
10096 |
109 |
0 |
0 |
T128 |
4528 |
57 |
0 |
0 |
T147 |
11687 |
25 |
0 |
0 |
T148 |
7341 |
14 |
0 |
0 |
T155 |
4859 |
7 |
0 |
0 |
T156 |
6551 |
12 |
0 |
0 |
T157 |
12038 |
92 |
0 |
0 |
T158 |
12737 |
47 |
0 |
0 |
T159 |
91046 |
209 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4093 |
0 |
0 |
T102 |
70122 |
697 |
0 |
0 |
T111 |
10096 |
78 |
0 |
0 |
T128 |
4528 |
53 |
0 |
0 |
T147 |
11687 |
9 |
0 |
0 |
T148 |
7341 |
51 |
0 |
0 |
T155 |
4859 |
7 |
0 |
0 |
T156 |
6551 |
23 |
0 |
0 |
T157 |
12038 |
24 |
0 |
0 |
T158 |
12737 |
83 |
0 |
0 |
T159 |
91046 |
241 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4265 |
0 |
0 |
T97 |
11980 |
9 |
0 |
0 |
T102 |
70122 |
538 |
0 |
0 |
T111 |
10096 |
109 |
0 |
0 |
T147 |
11687 |
7 |
0 |
0 |
T148 |
7341 |
27 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
1 |
0 |
0 |
T157 |
12038 |
109 |
0 |
0 |
T158 |
12737 |
20 |
0 |
0 |
T159 |
91046 |
235 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4460 |
0 |
0 |
T102 |
70122 |
557 |
0 |
0 |
T111 |
10096 |
98 |
0 |
0 |
T128 |
4528 |
45 |
0 |
0 |
T147 |
11687 |
31 |
0 |
0 |
T148 |
7341 |
58 |
0 |
0 |
T155 |
4859 |
8 |
0 |
0 |
T156 |
6551 |
16 |
0 |
0 |
T157 |
12038 |
12 |
0 |
0 |
T158 |
12737 |
62 |
0 |
0 |
T159 |
91046 |
220 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3901 |
0 |
0 |
T102 |
70122 |
450 |
0 |
0 |
T111 |
10096 |
17 |
0 |
0 |
T128 |
4528 |
43 |
0 |
0 |
T147 |
11687 |
12 |
0 |
0 |
T148 |
7341 |
36 |
0 |
0 |
T155 |
4859 |
55 |
0 |
0 |
T156 |
6551 |
12 |
0 |
0 |
T157 |
12038 |
106 |
0 |
0 |
T158 |
12737 |
3 |
0 |
0 |
T159 |
91046 |
240 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3980 |
0 |
0 |
T102 |
70122 |
414 |
0 |
0 |
T103 |
16553 |
2 |
0 |
0 |
T111 |
10096 |
14 |
0 |
0 |
T147 |
11687 |
5 |
0 |
0 |
T148 |
7341 |
24 |
0 |
0 |
T155 |
4859 |
6 |
0 |
0 |
T156 |
6551 |
17 |
0 |
0 |
T157 |
12038 |
70 |
0 |
0 |
T158 |
12737 |
59 |
0 |
0 |
T159 |
91046 |
207 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3999 |
0 |
0 |
T102 |
70122 |
412 |
0 |
0 |
T111 |
10096 |
23 |
0 |
0 |
T147 |
11687 |
22 |
0 |
0 |
T148 |
7341 |
25 |
0 |
0 |
T155 |
4859 |
53 |
0 |
0 |
T157 |
12038 |
74 |
0 |
0 |
T158 |
12737 |
42 |
0 |
0 |
T159 |
91046 |
197 |
0 |
0 |
T160 |
15451 |
112 |
0 |
0 |
T162 |
103009 |
770 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3524 |
0 |
0 |
T102 |
70122 |
580 |
0 |
0 |
T111 |
10096 |
68 |
0 |
0 |
T128 |
4528 |
2 |
0 |
0 |
T147 |
11687 |
23 |
0 |
0 |
T148 |
7341 |
38 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
20 |
0 |
0 |
T157 |
12038 |
7 |
0 |
0 |
T158 |
12737 |
23 |
0 |
0 |
T159 |
91046 |
250 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4158 |
0 |
0 |
T102 |
70122 |
603 |
0 |
0 |
T111 |
10096 |
62 |
0 |
0 |
T128 |
4528 |
48 |
0 |
0 |
T147 |
11687 |
13 |
0 |
0 |
T148 |
7341 |
4 |
0 |
0 |
T155 |
4859 |
56 |
0 |
0 |
T157 |
12038 |
74 |
0 |
0 |
T158 |
12737 |
20 |
0 |
0 |
T159 |
91046 |
229 |
0 |
0 |
T160 |
15451 |
90 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3615 |
0 |
0 |
T102 |
70122 |
301 |
0 |
0 |
T111 |
10096 |
11 |
0 |
0 |
T147 |
11687 |
22 |
0 |
0 |
T148 |
7341 |
8 |
0 |
0 |
T155 |
4859 |
54 |
0 |
0 |
T156 |
6551 |
9 |
0 |
0 |
T157 |
12038 |
41 |
0 |
0 |
T158 |
12737 |
57 |
0 |
0 |
T159 |
91046 |
203 |
0 |
0 |
T160 |
15451 |
65 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4010 |
0 |
0 |
T102 |
70122 |
505 |
0 |
0 |
T103 |
16553 |
1 |
0 |
0 |
T111 |
10096 |
78 |
0 |
0 |
T128 |
4528 |
44 |
0 |
0 |
T148 |
7341 |
22 |
0 |
0 |
T155 |
4859 |
33 |
0 |
0 |
T156 |
6551 |
3 |
0 |
0 |
T157 |
12038 |
98 |
0 |
0 |
T158 |
12737 |
19 |
0 |
0 |
T159 |
91046 |
246 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4143 |
0 |
0 |
T102 |
70122 |
575 |
0 |
0 |
T111 |
10096 |
36 |
0 |
0 |
T128 |
4528 |
9 |
0 |
0 |
T147 |
11687 |
41 |
0 |
0 |
T148 |
7341 |
39 |
0 |
0 |
T155 |
4859 |
46 |
0 |
0 |
T156 |
6551 |
7 |
0 |
0 |
T157 |
12038 |
77 |
0 |
0 |
T158 |
12737 |
57 |
0 |
0 |
T159 |
91046 |
224 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4011 |
0 |
0 |
T102 |
70122 |
445 |
0 |
0 |
T103 |
16553 |
9 |
0 |
0 |
T111 |
10096 |
8 |
0 |
0 |
T147 |
11687 |
25 |
0 |
0 |
T148 |
7341 |
40 |
0 |
0 |
T155 |
4859 |
47 |
0 |
0 |
T156 |
6551 |
5 |
0 |
0 |
T157 |
12038 |
95 |
0 |
0 |
T158 |
12737 |
66 |
0 |
0 |
T159 |
91046 |
188 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3437 |
0 |
0 |
T102 |
70122 |
446 |
0 |
0 |
T111 |
10096 |
65 |
0 |
0 |
T128 |
4528 |
4 |
0 |
0 |
T147 |
11687 |
1 |
0 |
0 |
T148 |
7341 |
29 |
0 |
0 |
T155 |
4859 |
47 |
0 |
0 |
T156 |
6551 |
10 |
0 |
0 |
T157 |
12038 |
64 |
0 |
0 |
T158 |
12737 |
28 |
0 |
0 |
T159 |
91046 |
207 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3785 |
0 |
0 |
T97 |
11980 |
8 |
0 |
0 |
T102 |
70122 |
576 |
0 |
0 |
T111 |
10096 |
57 |
0 |
0 |
T128 |
4528 |
4 |
0 |
0 |
T147 |
11687 |
33 |
0 |
0 |
T148 |
7341 |
3 |
0 |
0 |
T155 |
4859 |
34 |
0 |
0 |
T157 |
12038 |
64 |
0 |
0 |
T158 |
12737 |
14 |
0 |
0 |
T159 |
91046 |
253 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4018 |
0 |
0 |
T102 |
70122 |
438 |
0 |
0 |
T111 |
10096 |
86 |
0 |
0 |
T128 |
4528 |
29 |
0 |
0 |
T147 |
11687 |
26 |
0 |
0 |
T148 |
7341 |
3 |
0 |
0 |
T155 |
4859 |
69 |
0 |
0 |
T156 |
6551 |
9 |
0 |
0 |
T157 |
12038 |
101 |
0 |
0 |
T158 |
12737 |
23 |
0 |
0 |
T159 |
91046 |
240 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3549 |
0 |
0 |
T102 |
70122 |
560 |
0 |
0 |
T111 |
10096 |
70 |
0 |
0 |
T147 |
11687 |
26 |
0 |
0 |
T148 |
7341 |
11 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
9 |
0 |
0 |
T157 |
12038 |
15 |
0 |
0 |
T158 |
12737 |
70 |
0 |
0 |
T159 |
91046 |
249 |
0 |
0 |
T160 |
15451 |
92 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4217 |
0 |
0 |
T97 |
11980 |
15 |
0 |
0 |
T102 |
70122 |
534 |
0 |
0 |
T111 |
10096 |
57 |
0 |
0 |
T147 |
11687 |
1 |
0 |
0 |
T148 |
7341 |
21 |
0 |
0 |
T155 |
4859 |
40 |
0 |
0 |
T156 |
6551 |
3 |
0 |
0 |
T157 |
12038 |
101 |
0 |
0 |
T158 |
12737 |
51 |
0 |
0 |
T159 |
91046 |
209 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
4202 |
0 |
0 |
T102 |
70122 |
423 |
0 |
0 |
T111 |
10096 |
53 |
0 |
0 |
T128 |
4528 |
1 |
0 |
0 |
T147 |
11687 |
18 |
0 |
0 |
T148 |
7341 |
29 |
0 |
0 |
T156 |
6551 |
5 |
0 |
0 |
T157 |
12038 |
66 |
0 |
0 |
T158 |
12737 |
19 |
0 |
0 |
T159 |
91046 |
218 |
0 |
0 |
T160 |
15451 |
143 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3821 |
0 |
0 |
T102 |
70122 |
436 |
0 |
0 |
T111 |
10096 |
46 |
0 |
0 |
T128 |
4528 |
31 |
0 |
0 |
T147 |
11687 |
12 |
0 |
0 |
T148 |
7341 |
18 |
0 |
0 |
T155 |
4859 |
10 |
0 |
0 |
T156 |
6551 |
17 |
0 |
0 |
T157 |
12038 |
13 |
0 |
0 |
T158 |
12737 |
38 |
0 |
0 |
T159 |
91046 |
198 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3867 |
0 |
0 |
T102 |
70122 |
502 |
0 |
0 |
T111 |
10096 |
62 |
0 |
0 |
T128 |
4528 |
33 |
0 |
0 |
T147 |
11687 |
17 |
0 |
0 |
T148 |
7341 |
10 |
0 |
0 |
T155 |
4859 |
4 |
0 |
0 |
T157 |
12038 |
48 |
0 |
0 |
T158 |
12737 |
70 |
0 |
0 |
T159 |
91046 |
228 |
0 |
0 |
T160 |
15451 |
82 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3881 |
0 |
0 |
T102 |
70122 |
599 |
0 |
0 |
T111 |
10096 |
66 |
0 |
0 |
T128 |
4528 |
2 |
0 |
0 |
T147 |
11687 |
11 |
0 |
0 |
T148 |
7341 |
3 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
2 |
0 |
0 |
T157 |
12038 |
56 |
0 |
0 |
T158 |
12737 |
18 |
0 |
0 |
T159 |
91046 |
243 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1430 |
0 |
0 |
T102 |
70122 |
101 |
0 |
0 |
T111 |
10096 |
16 |
0 |
0 |
T128 |
4528 |
7 |
0 |
0 |
T147 |
11687 |
19 |
0 |
0 |
T148 |
7341 |
9 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
1 |
0 |
0 |
T157 |
12038 |
23 |
0 |
0 |
T158 |
12737 |
37 |
0 |
0 |
T159 |
91046 |
232 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1617 |
0 |
0 |
T102 |
70122 |
129 |
0 |
0 |
T105 |
10994 |
1 |
0 |
0 |
T111 |
10096 |
7 |
0 |
0 |
T147 |
11687 |
50 |
0 |
0 |
T148 |
7341 |
42 |
0 |
0 |
T155 |
4859 |
1 |
0 |
0 |
T156 |
6551 |
11 |
0 |
0 |
T157 |
12038 |
21 |
0 |
0 |
T158 |
12737 |
44 |
0 |
0 |
T159 |
91046 |
222 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1489 |
0 |
0 |
T102 |
70122 |
133 |
0 |
0 |
T111 |
10096 |
27 |
0 |
0 |
T147 |
11687 |
25 |
0 |
0 |
T148 |
7341 |
12 |
0 |
0 |
T155 |
4859 |
8 |
0 |
0 |
T156 |
6551 |
28 |
0 |
0 |
T157 |
12038 |
24 |
0 |
0 |
T158 |
12737 |
51 |
0 |
0 |
T159 |
91046 |
178 |
0 |
0 |
T160 |
15451 |
19 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1346 |
0 |
0 |
T102 |
70122 |
103 |
0 |
0 |
T111 |
10096 |
17 |
0 |
0 |
T128 |
4528 |
7 |
0 |
0 |
T147 |
11687 |
26 |
0 |
0 |
T148 |
7341 |
10 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T156 |
6551 |
11 |
0 |
0 |
T157 |
12038 |
19 |
0 |
0 |
T158 |
12737 |
65 |
0 |
0 |
T159 |
91046 |
166 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1959 |
0 |
0 |
T102 |
70122 |
123 |
0 |
0 |
T111 |
10096 |
35 |
0 |
0 |
T128 |
4528 |
8 |
0 |
0 |
T147 |
11687 |
22 |
0 |
0 |
T148 |
7341 |
11 |
0 |
0 |
T155 |
4859 |
1 |
0 |
0 |
T156 |
6551 |
6 |
0 |
0 |
T157 |
12038 |
22 |
0 |
0 |
T158 |
12737 |
16 |
0 |
0 |
T159 |
91046 |
247 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
3901 |
0 |
0 |
T17 |
483709 |
22 |
0 |
0 |
T18 |
0 |
39 |
0 |
0 |
T29 |
0 |
33 |
0 |
0 |
T40 |
408742 |
0 |
0 |
0 |
T58 |
1552 |
0 |
0 |
0 |
T62 |
419871 |
0 |
0 |
0 |
T81 |
0 |
16 |
0 |
0 |
T90 |
1328 |
0 |
0 |
0 |
T96 |
40079 |
0 |
0 |
0 |
T104 |
382313 |
0 |
0 |
0 |
T117 |
185016 |
0 |
0 |
0 |
T163 |
0 |
6 |
0 |
0 |
T164 |
0 |
43 |
0 |
0 |
T165 |
0 |
21 |
0 |
0 |
T166 |
0 |
32 |
0 |
0 |
T167 |
0 |
15 |
0 |
0 |
T168 |
0 |
42 |
0 |
0 |
T169 |
73045 |
0 |
0 |
0 |
T170 |
1930 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1471 |
0 |
0 |
T102 |
70122 |
110 |
0 |
0 |
T111 |
10096 |
20 |
0 |
0 |
T128 |
4528 |
5 |
0 |
0 |
T147 |
11687 |
11 |
0 |
0 |
T148 |
7341 |
29 |
0 |
0 |
T155 |
4859 |
4 |
0 |
0 |
T156 |
6551 |
16 |
0 |
0 |
T157 |
12038 |
13 |
0 |
0 |
T158 |
12737 |
55 |
0 |
0 |
T159 |
91046 |
221 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1580 |
0 |
0 |
T102 |
70122 |
100 |
0 |
0 |
T111 |
10096 |
20 |
0 |
0 |
T128 |
4528 |
9 |
0 |
0 |
T147 |
11687 |
37 |
0 |
0 |
T148 |
7341 |
1 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
32 |
0 |
0 |
T157 |
12038 |
21 |
0 |
0 |
T158 |
12737 |
34 |
0 |
0 |
T159 |
91046 |
228 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1241 |
0 |
0 |
T102 |
70122 |
63 |
0 |
0 |
T111 |
10096 |
10 |
0 |
0 |
T128 |
4528 |
8 |
0 |
0 |
T147 |
11687 |
32 |
0 |
0 |
T148 |
7341 |
18 |
0 |
0 |
T155 |
4859 |
2 |
0 |
0 |
T156 |
6551 |
4 |
0 |
0 |
T157 |
12038 |
15 |
0 |
0 |
T158 |
12737 |
61 |
0 |
0 |
T159 |
91046 |
191 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1157 |
0 |
0 |
T102 |
70122 |
73 |
0 |
0 |
T103 |
16553 |
4 |
0 |
0 |
T111 |
10096 |
14 |
0 |
0 |
T147 |
11687 |
28 |
0 |
0 |
T148 |
7341 |
22 |
0 |
0 |
T155 |
4859 |
1 |
0 |
0 |
T157 |
12038 |
10 |
0 |
0 |
T158 |
12737 |
25 |
0 |
0 |
T159 |
91046 |
235 |
0 |
0 |
T160 |
15451 |
20 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1308 |
0 |
0 |
T102 |
70122 |
57 |
0 |
0 |
T111 |
10096 |
12 |
0 |
0 |
T128 |
4528 |
7 |
0 |
0 |
T147 |
11687 |
27 |
0 |
0 |
T148 |
7341 |
20 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T157 |
12038 |
11 |
0 |
0 |
T158 |
12737 |
30 |
0 |
0 |
T159 |
91046 |
218 |
0 |
0 |
T160 |
15451 |
24 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1278 |
0 |
0 |
T102 |
70122 |
69 |
0 |
0 |
T105 |
10994 |
6 |
0 |
0 |
T111 |
10096 |
24 |
0 |
0 |
T147 |
11687 |
32 |
0 |
0 |
T148 |
7341 |
42 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T156 |
6551 |
11 |
0 |
0 |
T157 |
12038 |
12 |
0 |
0 |
T158 |
12737 |
5 |
0 |
0 |
T159 |
91046 |
195 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
2144 |
0 |
0 |
T102 |
70122 |
261 |
0 |
0 |
T111 |
10096 |
39 |
0 |
0 |
T128 |
4528 |
12 |
0 |
0 |
T147 |
11687 |
39 |
0 |
0 |
T148 |
7341 |
11 |
0 |
0 |
T155 |
4859 |
12 |
0 |
0 |
T156 |
6551 |
10 |
0 |
0 |
T157 |
12038 |
22 |
0 |
0 |
T158 |
12737 |
22 |
0 |
0 |
T159 |
91046 |
228 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1334 |
0 |
0 |
T102 |
70122 |
90 |
0 |
0 |
T103 |
16553 |
7 |
0 |
0 |
T111 |
10096 |
19 |
0 |
0 |
T128 |
4528 |
7 |
0 |
0 |
T147 |
11687 |
25 |
0 |
0 |
T148 |
7341 |
16 |
0 |
0 |
T155 |
4859 |
6 |
0 |
0 |
T157 |
12038 |
29 |
0 |
0 |
T158 |
12737 |
33 |
0 |
0 |
T159 |
91046 |
220 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
2413 |
0 |
0 |
T102 |
70122 |
283 |
0 |
0 |
T111 |
10096 |
53 |
0 |
0 |
T128 |
4528 |
15 |
0 |
0 |
T147 |
11687 |
34 |
0 |
0 |
T148 |
7341 |
11 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T156 |
6551 |
2 |
0 |
0 |
T157 |
12038 |
31 |
0 |
0 |
T158 |
12737 |
36 |
0 |
0 |
T159 |
91046 |
203 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1676 |
0 |
0 |
T102 |
70122 |
97 |
0 |
0 |
T111 |
10096 |
11 |
0 |
0 |
T147 |
11687 |
9 |
0 |
0 |
T148 |
7341 |
19 |
0 |
0 |
T155 |
4859 |
9 |
0 |
0 |
T156 |
6551 |
21 |
0 |
0 |
T157 |
12038 |
20 |
0 |
0 |
T158 |
12737 |
20 |
0 |
0 |
T159 |
91046 |
220 |
0 |
0 |
T161 |
15805 |
5 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1403 |
0 |
0 |
T102 |
70122 |
70 |
0 |
0 |
T111 |
10096 |
7 |
0 |
0 |
T128 |
4528 |
4 |
0 |
0 |
T147 |
11687 |
18 |
0 |
0 |
T148 |
7341 |
11 |
0 |
0 |
T155 |
4859 |
3 |
0 |
0 |
T156 |
6551 |
12 |
0 |
0 |
T157 |
12038 |
20 |
0 |
0 |
T158 |
12737 |
83 |
0 |
0 |
T159 |
91046 |
256 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1323 |
0 |
0 |
T102 |
70122 |
65 |
0 |
0 |
T111 |
10096 |
13 |
0 |
0 |
T128 |
4528 |
1 |
0 |
0 |
T147 |
11687 |
25 |
0 |
0 |
T148 |
7341 |
42 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T156 |
6551 |
5 |
0 |
0 |
T157 |
12038 |
16 |
0 |
0 |
T158 |
12737 |
4 |
0 |
0 |
T159 |
91046 |
239 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1263 |
0 |
0 |
T102 |
70122 |
81 |
0 |
0 |
T111 |
10096 |
14 |
0 |
0 |
T128 |
4528 |
2 |
0 |
0 |
T147 |
11687 |
48 |
0 |
0 |
T148 |
7341 |
22 |
0 |
0 |
T155 |
4859 |
6 |
0 |
0 |
T157 |
12038 |
19 |
0 |
0 |
T158 |
12737 |
44 |
0 |
0 |
T159 |
91046 |
238 |
0 |
0 |
T160 |
15451 |
23 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1307 |
0 |
0 |
T102 |
70122 |
65 |
0 |
0 |
T111 |
10096 |
18 |
0 |
0 |
T128 |
4528 |
7 |
0 |
0 |
T147 |
11687 |
7 |
0 |
0 |
T148 |
7341 |
5 |
0 |
0 |
T155 |
4859 |
1 |
0 |
0 |
T156 |
6551 |
11 |
0 |
0 |
T157 |
12038 |
16 |
0 |
0 |
T158 |
12737 |
80 |
0 |
0 |
T159 |
91046 |
218 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1313 |
0 |
0 |
T97 |
11980 |
1 |
0 |
0 |
T102 |
70122 |
57 |
0 |
0 |
T111 |
10096 |
11 |
0 |
0 |
T147 |
11687 |
21 |
0 |
0 |
T148 |
7341 |
33 |
0 |
0 |
T155 |
4859 |
5 |
0 |
0 |
T156 |
6551 |
3 |
0 |
0 |
T157 |
12038 |
17 |
0 |
0 |
T158 |
12737 |
43 |
0 |
0 |
T159 |
91046 |
234 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
428618852 |
1330 |
0 |
0 |
T102 |
70122 |
65 |
0 |
0 |
T111 |
10096 |
9 |
0 |
0 |
T128 |
4528 |
3 |
0 |
0 |
T147 |
11687 |
33 |
0 |
0 |
T148 |
7341 |
25 |
0 |
0 |
T155 |
4859 |
4 |
0 |
0 |
T156 |
6551 |
8 |
0 |
0 |
T157 |
12038 |
7 |
0 |
0 |
T158 |
12737 |
16 |
0 |
0 |
T159 |
91046 |
234 |
0 |
0 |