Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3175201	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4028207

1

T1

1263

T2

1

T3

1308

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3818092	1			T1	738		T2	1		T3	872
values[0x0]	1692482	1			T1	465		T2	8		T3	434
values[0x1]	1692834	1			T1	438		T2	8		T3	444

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2255419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4947989

1

T1

1357

T2

4

T3

1396

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28902	1			T6	29		T7	6		T9	56
valid_sources[0x01]	25954	1			T5	37		T6	32		T7	8
valid_sources[0x02]	30026	1			T1	3		T6	29		T7	3
valid_sources[0x03]	27693	1			T1	16		T5	12		T6	12
valid_sources[0x04]	24497	1			T1	2		T6	19		T7	8
valid_sources[0x05]	24685	1			T1	17		T6	9		T7	7
valid_sources[0x06]	25256	1			T1	7		T6	20		T7	3
valid_sources[0x07]	26471	1			T1	9		T6	5		T7	4
valid_sources[0x08]	29497	1			T1	3		T6	15		T7	6
valid_sources[0x09]	26058	1			T6	16		T7	2		T9	33
valid_sources[0x0a]	27535	1			T1	11		T6	15		T7	2
valid_sources[0x0b]	25002	1			T5	127		T6	19		T7	3
valid_sources[0x0c]	30379	1			T1	6		T5	69		T6	6
valid_sources[0x0d]	34723	1			T1	18		T6	23		T7	5
valid_sources[0x0e]	24272	1			T1	3		T6	14		T7	3
valid_sources[0x0f]	27983	1			T1	13		T6	8		T7	4
valid_sources[0x10]	26697	1			T1	12		T5	60		T6	26
valid_sources[0x11]	31206	1			T1	3		T6	10		T7	5
valid_sources[0x12]	28013	1			T1	11		T6	14		T7	6
valid_sources[0x13]	26570	1			T1	24		T6	13		T7	3
valid_sources[0x14]	28722	1			T1	12		T5	166		T6	17
valid_sources[0x15]	29624	1			T1	1		T4	4		T6	18
valid_sources[0x16]	27971	1			T1	16		T6	9		T7	6
valid_sources[0x17]	26857	1			T1	16		T5	2		T6	21
valid_sources[0x18]	25752	1			T1	2		T6	8		T7	7
valid_sources[0x19]	28561	1			T1	6		T6	9		T7	4
valid_sources[0x1a]	27638	1			T1	2		T6	7		T7	4
valid_sources[0x1b]	27434	1			T1	5		T5	1		T6	16
valid_sources[0x1c]	31583	1			T1	10		T5	39		T6	23
valid_sources[0x1d]	31988	1			T1	5		T6	6		T7	5
valid_sources[0x1e]	26132	1			T1	1		T6	14		T7	3
valid_sources[0x1f]	28714	1			T5	4		T6	30		T7	6
valid_sources[0x20]	32362	1			T1	2		T5	87		T6	8
valid_sources[0x21]	29609	1			T6	29		T7	3		T9	35
valid_sources[0x22]	28794	1			T1	9		T6	17		T7	4
valid_sources[0x23]	27691	1			T1	14		T5	49		T6	20
valid_sources[0x24]	27275	1			T1	5		T2	6		T5	1
valid_sources[0x25]	25975	1			T6	27		T7	2		T9	11
valid_sources[0x26]	28079	1			T1	5		T6	14		T7	10
valid_sources[0x27]	25143	1			T1	8		T6	21		T7	4
valid_sources[0x28]	27895	1			T1	5		T5	2		T6	23
valid_sources[0x29]	27167	1			T1	12		T6	16		T7	4
valid_sources[0x2a]	27178	1			T1	2		T4	1		T6	5
valid_sources[0x2b]	27787	1			T1	7		T6	11		T7	4
valid_sources[0x2c]	24896	1			T1	2		T6	25		T7	6
valid_sources[0x2d]	30820	1			T1	10		T6	14		T7	6
valid_sources[0x2e]	27035	1			T1	6		T5	163		T6	22
valid_sources[0x2f]	28158	1			T1	3		T5	1		T6	21
valid_sources[0x30]	26453	1			T5	1		T6	15		T7	9
valid_sources[0x31]	31148	1			T5	1		T6	24		T7	3
valid_sources[0x32]	27025	1			T1	1		T6	15		T7	5
valid_sources[0x33]	26450	1			T6	18		T7	3		T8	4
valid_sources[0x34]	26232	1			T5	30		T6	9		T7	4
valid_sources[0x35]	27991	1			T1	15		T5	154		T6	10
valid_sources[0x36]	27471	1			T1	1		T6	24		T7	2
valid_sources[0x37]	25987	1			T1	2		T5	23		T6	13
valid_sources[0x38]	28301	1			T1	1		T5	1		T6	24
valid_sources[0x39]	26783	1			T1	14		T6	18		T7	6
valid_sources[0x3a]	26706	1			T1	17		T6	21		T7	7
valid_sources[0x3b]	25364	1			T1	2		T6	10		T7	4
valid_sources[0x3c]	30001	1			T1	16		T6	19		T7	6
valid_sources[0x3d]	31611	1			T1	1		T6	24		T7	6
valid_sources[0x3e]	28305	1			T1	1		T6	12		T7	1
valid_sources[0x3f]	26184	1			T1	5		T6	25		T7	2
valid_sources[0x40]	30830	1			T1	15		T6	14		T7	5
valid_sources[0x41]	34936	1			T1	27		T6	13		T7	8
valid_sources[0x42]	29067	1			T1	2		T6	25		T7	6
valid_sources[0x43]	27955	1			T1	9		T6	18		T7	4
valid_sources[0x44]	29357	1			T1	10		T6	17		T7	4
valid_sources[0x45]	25338	1			T5	199		T6	26		T7	7
valid_sources[0x46]	26822	1			T1	3		T6	18		T7	3
valid_sources[0x47]	26173	1			T1	11		T5	89		T6	25
valid_sources[0x48]	23936	1			T1	11		T6	18		T7	2
valid_sources[0x49]	26354	1			T1	1		T6	14		T7	9
valid_sources[0x4a]	35449	1			T1	6		T6	24		T7	7
valid_sources[0x4b]	30117	1			T1	6		T6	6		T7	3
valid_sources[0x4c]	24448	1			T1	12		T6	16		T7	5
valid_sources[0x4d]	29139	1			T1	16		T6	12		T7	5
valid_sources[0x4e]	26120	1			T1	2		T4	1		T6	13
valid_sources[0x4f]	27575	1			T1	7		T5	125		T6	33
valid_sources[0x50]	25142	1			T1	3		T6	10		T7	6
valid_sources[0x51]	31666	1			T6	19		T7	4		T9	37
valid_sources[0x52]	28141	1			T1	8		T2	5		T6	22
valid_sources[0x53]	28988	1			T1	1		T6	15		T7	6
valid_sources[0x54]	26567	1			T6	14		T7	4		T9	54
valid_sources[0x55]	33251	1			T1	9		T6	18		T7	7
valid_sources[0x56]	27547	1			T1	6		T6	25		T7	2
valid_sources[0x57]	25661	1			T1	2		T6	10		T7	6
valid_sources[0x58]	27262	1			T1	6		T6	16		T7	6
valid_sources[0x59]	27487	1			T1	27		T6	20		T7	6
valid_sources[0x5a]	25768	1			T1	5		T6	18		T7	3
valid_sources[0x5b]	27430	1			T5	2		T6	10		T7	2
valid_sources[0x5c]	29012	1			T1	8		T5	91		T6	17
valid_sources[0x5d]	30301	1			T1	1		T5	114		T6	11
valid_sources[0x5e]	27729	1			T1	5		T6	15		T7	5
valid_sources[0x5f]	25088	1			T1	2		T6	30		T7	4
valid_sources[0x60]	39944	1			T6	18		T7	2		T8	2
valid_sources[0x61]	24941	1			T6	12		T7	5		T9	16
valid_sources[0x62]	27465	1			T1	3		T6	18		T7	5
valid_sources[0x63]	29021	1			T5	2		T6	17		T7	3
valid_sources[0x64]	37840	1			T1	4		T5	42		T6	21
valid_sources[0x65]	25767	1			T1	10		T5	186		T6	14
valid_sources[0x66]	31183	1			T1	7		T6	17		T7	3
valid_sources[0x67]	25690	1			T5	93		T6	12		T7	7
valid_sources[0x68]	26028	1			T5	2		T6	20		T7	5
valid_sources[0x69]	27027	1			T1	6		T6	23		T7	4
valid_sources[0x6a]	29206	1			T1	8		T6	13		T7	5
valid_sources[0x6b]	28062	1			T1	14		T5	243		T6	8
valid_sources[0x6c]	25710	1			T1	3		T5	4		T6	9
valid_sources[0x6d]	27339	1			T4	2		T5	1		T6	32
valid_sources[0x6e]	27157	1			T1	11		T5	661		T6	21
valid_sources[0x6f]	29198	1			T1	1		T5	2		T6	15
valid_sources[0x70]	27272	1			T1	8		T6	20		T7	2
valid_sources[0x71]	27144	1			T6	5		T7	3		T9	51
valid_sources[0x72]	25733	1			T1	1		T6	8		T7	4
valid_sources[0x73]	28702	1			T6	18		T7	5		T9	45
valid_sources[0x74]	25592	1			T1	19		T6	20		T7	4
valid_sources[0x75]	31062	1			T1	5		T6	11		T7	8
valid_sources[0x76]	27265	1			T1	29		T5	1		T6	31
valid_sources[0x77]	28604	1			T1	9		T6	32		T7	5
valid_sources[0x78]	26931	1			T1	4		T3	452		T6	17
valid_sources[0x79]	26781	1			T1	3		T6	13		T7	3
valid_sources[0x7a]	26521	1			T1	11		T6	15		T7	1
valid_sources[0x7b]	28029	1			T1	2		T6	19		T7	7
valid_sources[0x7c]	23423	1			T1	11		T6	20		T7	1
valid_sources[0x7d]	27616	1			T1	7		T5	452		T6	13
valid_sources[0x7e]	25438	1			T1	9		T6	17		T7	3
valid_sources[0x7f]	30251	1			T1	3		T6	17		T7	5
valid_sources[0x80]	26107	1			T1	2		T5	2		T6	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

948481

1

T1

367

T3

433

T4

1

values[0x0]

all_enables

biggest_size

1551500

1

T1

464

T2

1

T3

434

values[0x1]

all_enables

biggest_size

1528226

1

T1

432

T3

441

T4

3