Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3192582

1

T1

378

T2

16

T3

442

full_word

4027085

1

T1

1263

T2

1

T3

1308

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7219317	1			T1	1641		T2	17		T3	1750
auto[TlIntgErrCmd]	116	1			T93	6		T96	9		T97	5
auto[TlIntgErrData]	126	1			T93	8		T96	12		T97	9
auto[TlIntgErrBoth]	108	1			T93	6		T96	9		T97	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3819546

1

T1

738

T2

1

T3

872

auto[1]

3400121

1

T1

903

T2

16

T3

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2870835	1			T1	371		T2	1		T3	439
auto[TlIntgErrNone]	partial	auto[1]	321433	1			T1	7		T2	15		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	948551	1			T1	367		T3	433		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3078498	1			T1	896		T2	1		T3	875
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T93	3		T96	4		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T93	2		T96	5		T97	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T93	1		T111	2		T160	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T109	1		T160	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T93	4		T96	4		T97	4
auto[TlIntgErrData]	partial	auto[1]	60	1			T93	4		T96	6		T97	3
auto[TlIntgErrData]	full_word	auto[0]	13	1			T96	1		T97	2		T162	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T96	1		T111	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T93	1		T96	2		T97	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T93	5		T96	6		T97	3
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T96	1		T97	1		T111	1