Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_tpm
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.79 99.29 91.20 91.67 96.77 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spi_tpm 95.79 99.29 91.20 91.67 96.77 100.00



Module Instance : tb.dut.u_spi_tpm

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.79 99.29 91.20 91.67 96.77 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.81 99.28 85.25 91.67 95.68 92.16


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arbiter 87.57 100.00 76.47 92.86 80.95
u_cmdaddr_buffer 92.67 100.00 76.92 93.75 100.00
u_csb_sync_rst 100.00 100.00 100.00 100.00
u_hw_reg_slice 100.00 100.00 100.00
u_rdfifo_ready 100.00 100.00 100.00
u_sram_fifo 89.23 95.00 78.57 83.33 100.00
u_tpm_rd_buffer 89.74 100.00 69.23 100.00
u_tpm_wr_buffer 96.15 100.00 84.62 100.00 100.00
u_wrfifo_busy_sync 100.00 100.00 100.00
u_wrfifo_release_reqack 87.50 100.00 50.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_tpm
Line No.TotalCoveredPercent
TOTAL28228099.29
CONT_ASSIGN33511100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN37411100.00
CONT_ASSIGN49211100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN52111100.00
ALWAYS52588100.00
ALWAYS54233100.00
ALWAYS55544100.00
CONT_ASSIGN56411100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN59111100.00
ALWAYS59433100.00
ALWAYS60244100.00
ALWAYS61033100.00
ALWAYS62066100.00
CONT_ASSIGN63711100.00
CONT_ASSIGN64411100.00
ALWAYS64844100.00
CONT_ASSIGN65511100.00
ALWAYS65844100.00
CONT_ASSIGN66511100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN68011100.00
ALWAYS68366100.00
CONT_ASSIGN70611100.00
ALWAYS70966100.00
ALWAYS72144100.00
ALWAYS74333100.00
ALWAYS75133100.00
ALWAYS76366100.00
ALWAYS78066100.00
ALWAYS79633100.00
ALWAYS80266100.00
ALWAYS81344100.00
ALWAYS82344100.00
ALWAYS83244100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN84011100.00
ALWAYS85266100.00
ALWAYS86366100.00
ALWAYS87333100.00
ALWAYS89377100.00
ALWAYS9351515100.00
ALWAYS101233100.00
CONT_ASSIGN102111100.00
ALWAYS102433100.00
CONT_ASSIGN104411100.00
CONT_ASSIGN104511100.00
CONT_ASSIGN104911100.00
ALWAYS105233100.00
ALWAYS106444100.00
CONT_ASSIGN107311100.00
ALWAYS109533100.00
ALWAYS1123727198.61
CONT_ASSIGN137311100.00
CONT_ASSIGN137511100.00
ALWAYS138266100.00
ALWAYS139488100.00
ALWAYS140966100.00
CONT_ASSIGN142511100.00
CONT_ASSIGN1428100.00
CONT_ASSIGN145911100.00
CONT_ASSIGN146511100.00
ALWAYS147066100.00
ALWAYS148044100.00
CONT_ASSIGN148911100.00
CONT_ASSIGN149011100.00
CONT_ASSIGN152211100.00
CONT_ASSIGN155611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
335 1 1
349 1 1
374 1 1
492 1 1
493 1 1
521 1 1
525 1 1
526 1 1
527 1 1
529 1 1
530 1 1
531 1 1
532 1 1
533 1 1
MISSING_ELSE
542 1 1
543 1 1
545 1 1
555 1 1
556 1 1
557 1 1
558 1 1
MISSING_ELSE
564 1 1
566 1 1
591 1 1
594 1 1
595 1 1
597 1 1
602 1 1
603 1 1
604 1 1
605 1 1
MISSING_ELSE
610 1 1
611 1 1
613 1 1
620 1 1
621 1 1
622 1 1
624 1 1
625 1 1
626 1 1
MISSING_ELSE
637 1 1
644 1 1
648 1 1
649 1 1
650 1 1
651 1 1
MISSING_ELSE
655 1 1
658 1 1
659 1 1
660 1 1
661 1 1
MISSING_ELSE
665 1 1
667 1 1
680 1 1
683 1 1
684 1 1
685 1 1
686 1 1
687 1 1
688 1 1
MISSING_ELSE
706 1 1
709 1 1
710 1 1
711 1 1
712 1 1
713 1 1
714 1 1
MISSING_ELSE
721 1 1
722 1 1
727 1 1
733 1 1
743 1 1
744 1 1
746 1 1
MISSING_ELSE
751 1 1
752 1 1
754 1 1
763 1 1
764 1 1
765 1 1
766 1 1
774 1 1
775 1 1
MISSING_ELSE
780 1 1
781 1 1
783 1 1
784 1 1
785 1 1
786 1 1
MISSING_ELSE
796 2 2
797 1 1
802 1 1
803 1 1
804 1 1
805 1 1
806 1 1
807 1 1
MISSING_ELSE
813 1 1
814 1 1
815 1 1
817 1 1
MISSING_ELSE
823 1 1
824 1 1
825 1 1
826 1 1
MISSING_ELSE
832 1 1
833 1 1
834 1 1
836 1 1
MISSING_ELSE
839 1 1
840 1 1
852 1 1
853 1 1
854 1 1
855 1 1
856 1 1
857 1 1
MISSING_ELSE
863 1 1
864 1 1
865 1 1
866 1 1
867 1 1
868 1 1
MISSING_ELSE
873 1 1
874 1 1
876 1 1
893 1 1
895 1 1
897 1 1
901 1 1
905 1 1
909 1 1
913 1 1
935 1 1
937 1 1
939 1 1
940 1 1
941 1 1
MISSING_ELSE
948 1 1
952 1 1
956 1 1
960 1 1
965 1 1
967 1 1
969 1 1
974 1 1
978 1 1
982 1 1
1012 1 1
1013 1 1
1015 1 1
1021 1 1
1024 2 2
1025 1 1
1044 1 1
1045 1 1
1049 1 1
1052 1 1
1053 1 1
1055 1 1
1064 1 1
1065 1 1
1066 1 1
1067 1 1
MISSING_ELSE
1073 1 1
1095 1 1
1096 1 1
1098 1 1
1123 1 1
1126 1 1
1127 1 1
1129 1 1
1130 1 1
1131 1 1
1133 1 1
1134 1 1
1140 1 1
1142 1 1
1144 1 1
1146 1 1
1147 1 1
1148 1 1
1150 1 1
1158 0 1
MISSING_ELSE
1165 1 1
1167 1 1
1169 1 1
1170 1 1
MISSING_ELSE
1174 1 1
1175 1 1
MISSING_ELSE
1179 1 1
1180 1 1
1183 1 1
1188 1 1
1189 1 1
MISSING_ELSE
1191 1 1
1194 1 1
1195 1 1
1198 1 1
1201 1 1
1206 1 1
1207 1 1
MISSING_ELSE
MISSING_ELSE
1212 1 1
1213 1 1
1215 1 1
1219 1 1
MISSING_ELSE
1225 1 1
1226 1 1
1229 1 1
1230 1 1
MISSING_ELSE
1234 1 1
1237 1 1
MISSING_ELSE
1242 1 1
1243 1 1
1245 1 1
1247 1 1
1248 1 1
1249 1 1
1250 1 1
1251 1 1
1252 1 1
==> MISSING_ELSE
MISSING_ELSE
1258 1 1
1260 1 1
1261 1 1
1263 1 1
1264 1 1
MISSING_ELSE
1269 1 1
1270 1 1
1274 1 1
1275 1 1
MISSING_ELSE
1280 1 1
1283 1 1
1285 1 1
1286 1 1
MISSING_ELSE
1292 1 1
1293 1 1
1294 1 1
==> MISSING_ELSE
1299 1 1
1300 1 1
1301 1 1
MISSING_ELSE
1373 1 1
1375 1 1
1382 1 1
1383 1 1
1384 1 1
1385 1 1
1386 1 1
1387 1 1
MISSING_ELSE
1394 1 1
1395 1 1
1396 1 1
1400 1 1
1401 1 1
1402 1 1
1403 1 1
1404 1 1
MISSING_ELSE
1409 1 1
1410 1 1
1411 1 1
1417 1 1
1418 1 1
1419 1 1
MISSING_ELSE
1425 1 1
1428 0 1
1459 1 1
1465 1 1
1470 1 1
1471 1 1
1472 1 1
1473 1 1
1474 1 1
1475 1 1
MISSING_ELSE
1480 1 1
1481 1 1
1482 1 1
1483 1 1
MISSING_ELSE
1489 1 1
1490 1 1
1522 1 1
1556 1 1


Cond Coverage for Module : spi_tpm
TotalCoveredPercent
Conditions21619791.20
Logical21619791.20
Non-Logical00
Event00

 LINE       564
 EXPRESSION ((cmdaddr_bitcnt == 5'b0) && (sck_st_q == StIdle))
             ------------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT1,T2,T3

 LINE       564
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'b0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       564
 SUB-EXPRESSION (sck_st_q == StIdle)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       566
 EXPRESSION (cmdaddr_bitcnt == 5'h1d)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       591
 EXPRESSION (cmdaddr_bitcnt == 5'h1f)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       644
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelHwReg))
             ------1------    -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T27
10CoveredT5,T8,T9
11CoveredT8,T9,T27

 LINE       644
 SUB-EXPRESSION (isck_data_sel == SelHwReg)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T27

 LINE       655
 EXPRESSION (wrdata_bitcnt == 3'h7)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       711
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Write))
             ---------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       711
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT1,T3,T5

 LINE       744
 EXPRESSION (check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr)))
             -------1------    ------------------------------2------------------------------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       744
 SUB-EXPRESSION (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))
                 ---------------1---------------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T9
10CoveredT5,T8,T9

 LINE       744
 SUB-EXPRESSION (addr[23:16] == TpmAddr)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       766
 EXPRESSION (((!sys_clk_tpm_cfg.tpm_mode)) && check_hw_reg && (cmd_type == Read) && is_tpm_reg_q && ((!invalid_locality)) && ((!sys_clk_tpm_cfg.hw_reg_dis)))
             --------------1--------------    ------2-----    ---------3--------    ------4-----    ----------5----------    ---------------6---------------
-1--2--3--4--5--6-StatusTests
011111CoveredT5,T28,T46
101111CoveredT8,T9,T27
110111CoveredT8,T9,T29
111011CoveredT8,T9,T29
111101CoveredT8,T9,T27
111110CoveredT8,T9,T29
111111CoveredT8,T9,T27

 LINE       766
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       784
 EXPRESSION (TpmReturnByHwAddr[i][11:2] == addr[11:2])
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       805
 EXPRESSION (check_locality && is_tpm_reg_d)
             -------1------    ------2-----
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       807
 EXPRESSION ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality)) ? 1'b0 : 1'b1)
             -------------------------1-------------------------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       834
 EXPRESSION ((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en))
             -------------------1------------------    -------------------2------------------
-1--2-StatusTests
00CoveredT5,T8,T9
01CoveredT5,T8,T9
10CoveredT5,T8,T9

 LINE       834
 SUB-EXPRESSION (isck_p2s_sent && sck_rddata_shift_en)
                 ------1------    ---------2---------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       834
 SUB-EXPRESSION (sck_wrfifo_wvalid && wrdata_shift_en)
                 --------1--------    -------2-------
-1--2-StatusTests
01CoveredT5,T8,T9
10Not Covered
11CoveredT5,T8,T9

 LINE       840
 EXPRESSION (xfer_bytes_q == xfer_size)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       856
 EXPRESSION (sys_rdfifo_wvalid_i & sys_rdfifo_wready_o)
             ---------1---------   ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T8,T9

 LINE       867
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       940
 EXPRESSION (((!invalid_locality)) && (4'(i) == locality))
             ----------1----------    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       940
 SUB-EXPRESSION (4'(i) == locality)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       965
 EXPRESSION (((!invalid_locality)) && sys_active_locality[locality[2:0]])
             ----------1----------    -----------------2----------------
-1--2-StatusTests
01Not Covered
10CoveredT9,T27,T29
11CoveredT8,T9,T27

 LINE       1021
 EXPRESSION (isck_p2s_valid && (isck_p2s_bitcnt == '0))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1021
 SUB-EXPRESSION (isck_p2s_bitcnt == '0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1049
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelRdFifo))
             ------1------    --------------2-------------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1049
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1073
 EXPRESSION (((&sck_rdfifo_idx)) && (isck_data_sel == SelRdFifo) && sck_p2s_valid && (isck_p2s_bitcnt == 3'b1))
             ---------1---------    --------------2-------------    ------3------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT5,T8,T9
1011Not Covered
1101Not Covered
1110CoveredT5,T8,T9
1111CoveredT5,T8,T9

 LINE       1073
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1073
 SUB-EXPRESSION (isck_p2s_bitcnt == 3'b1)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1146
 EXPRESSION (cmdaddr_bitcnt == 5'h07)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1174
 EXPRESSION (cmdaddr_bitcnt == 5'h1b)
            ------------1------------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1179
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))
             ------------1------------    ---------2--------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1179
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1179
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1180
 EXPRESSION (((!is_tpm_reg_q)) || sys_clk_tpm_cfg.tpm_mode)
             --------1--------    ------------2-----------
-1--2-StatusTests
00CoveredT8,T9,T27
01CoveredT5,T28,T30
10CoveredT8,T9,T29

 LINE       1188
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1195
 EXPRESSION (invalid_locality && sys_clk_tpm_cfg.invalid_locality)
             --------1-------    ----------------2---------------
-1--2-StatusTests
01CoveredT8,T9,T29
10CoveredT8,T9,T29
11CoveredT8,T9,T27

 LINE       1206
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------
-1-StatusTests
0CoveredT8,T9,T29
1CoveredT8,T9,T29

 LINE       1212
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))
             ------------1------------    ---------2---------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1212
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1212
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1213
 EXPRESSION (((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
             ----------1---------    ------------2-----------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1229
 EXPRESSION ((cmd_type == Read) && ((!sck_rdfifo_cmd_pending)) && ((~|sck_cmdaddr_wdepth)))
             ---------1--------    -------------2-------------    ------------3-----------
-1--2--3-StatusTests
011CoveredT5,T8,T9
101CoveredT5,T8,T9
110CoveredT5,T8,T9
111CoveredT5,T8,T9

 LINE       1229
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1234
 EXPRESSION (isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))))
             ------1------    ---------------------------------------------------------------2---------------------------------------------------------------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1234
 SUB-EXPRESSION (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth))))
                 ------------------------1-----------------------    ------------------------------------2------------------------------------
-1--2-StatusTests
00CoveredT5,T8,T9
01CoveredT5,T8,T9
10CoveredT5,T8,T9

 LINE       1234
 SUB-EXPRESSION ((cmd_type == Read) && enough_payload_in_rdfifo)
                 ---------1--------    ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1234
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1234
 SUB-EXPRESSION ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
                 ---------1---------    ----------2---------    ------------3-----------
-1--2--3-StatusTests
011CoveredT5,T8,T9
101CoveredT5,T8,T9
110CoveredT5,T8,T9
111CoveredT5,T8,T9

 LINE       1234
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1247
 EXPRESSION ((cmd_type == Read) && is_hw_reg)
             ---------1--------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T9
11CoveredT8,T9,T27

 LINE       1247
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1249
 EXPRESSION (cmd_type == Read)
            ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1251
 EXPRESSION (cmd_type == Write)
            ---------1---------
-1-StatusTests
0Not Covered
1CoveredT5,T8,T9

 LINE       1263
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1274
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------
-1--2-StatusTests
01CoveredT8,T9,T27
10CoveredT8,T9,T27
11CoveredT8,T9,T27

 LINE       1283
 EXPRESSION (sck_wrfifo_wvalid && xfer_size_met)
             --------1--------    ------2------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1292
 EXPRESSION (cmd_type == Read)
            ---------1--------
-1-StatusTests
0Not Covered
1CoveredT8,T9,T27

 LINE       1299
 EXPRESSION (cmd_type == Read)
            ---------1--------
-1-StatusTests
0CoveredT5,T8,T9
1CoveredT5,T8,T9

 LINE       1386
 EXPRESSION (sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             -------1-------   ----------2---------   ----------3---------
-1--2--3-StatusTests
011CoveredT5,T8,T9
101Not Covered
110CoveredT5,T8,T9
111CoveredT5,T8,T9

 LINE       1396
 EXPRESSION (cmdaddr_bitcnt == 5'h0f)
            ------------1------------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT5,T8,T9

 LINE       1401
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Read))
             ---------1--------    ---------2--------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1401
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT5,T8,T9

 LINE       1403
 EXPRESSION (isck_p2s_sent && xfer_size_met && (sck_st_q == StReadFifo))
             ------1------    ------2------    ------------3-----------
-1--2--3-StatusTests
011CoveredT5,T8,T9
101CoveredT5,T8,T9
110CoveredT5,T8,T9
111CoveredT5,T8,T9

 LINE       1403
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT5,T8,T9

 LINE       1411
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1418
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1425
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1459
 EXPRESSION (sys_rdfifo_wvalid_i & ((!sys_rdfifo_wready_o)))
             ---------1---------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T8,T9
11Not Covered

 LINE       1465
 EXPRESSION (enough_payload_in_rdfifo && ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte)))
             ------------1-----------    ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT5,T8,T9
10CoveredT5,T8,T9
11CoveredT5,T8,T9

 LINE       1465
 SUB-EXPRESSION ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte))
                 ------------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T9
10CoveredT5,T8,T9

 LINE       1465
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1465
 SUB-EXPRESSION (sck_st_q == StStartByte)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T9

 LINE       1472
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T8,T9

 LINE       1482
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T8,T9

 LINE       1489
 EXPRESSION (rdfifo_active && ((!sck_rdfifo_req_pending)) && ((!sck_rdfifo_full)))
             ------1------    -------------2-------------    ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT5,T8,T9
110CoveredT5,T8,T9
111CoveredT5,T8,T9

FSM Coverage for Module : spi_tpm
Summary for FSM :: sck_st_q
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 12 11 91.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: sck_st_q
statesLine No.CoveredTests
StAddr 1148 Covered T5,T8,T9
StEnd 1158 Covered T5,T8,T9
StIdle 1143 Covered T1,T2,T3
StInvalid 1198 Covered T8,T9,T27
StReadFifo 1250 Covered T5,T8,T9
StReadHwReg 1248 Covered T8,T9,T27
StStartByte 1194 Covered T5,T8,T9
StWait 1183 Covered T5,T8,T9
StWrite 1252 Covered T5,T8,T9


transitionsLine No.CoveredTests
StAddr->StInvalid 1198 Covered T8,T9,T27
StAddr->StStartByte 1194 Covered T5,T8,T9
StAddr->StWait 1183 Covered T5,T8,T9
StIdle->StAddr 1148 Covered T5,T8,T9
StIdle->StEnd 1158 Not Covered
StReadFifo->StEnd 1264 Covered T5,T8,T9
StReadHwReg->StEnd 1275 Covered T8,T9,T27
StStartByte->StReadFifo 1250 Covered T5,T8,T9
StStartByte->StReadHwReg 1248 Covered T8,T9,T27
StStartByte->StWrite 1252 Covered T5,T8,T9
StWait->StStartByte 1237 Covered T5,T8,T9
StWrite->StEnd 1286 Covered T5,T8,T9



Branch Coverage for Module : spi_tpm
Line No.TotalCoveredPercent
Branches 155 150 96.77
IF 525 3 3 100.00
IF 542 2 2 100.00
IF 555 3 3 100.00
IF 594 2 2 100.00
IF 602 3 3 100.00
IF 610 2 2 100.00
IF 620 4 4 100.00
IF 648 3 3 100.00
IF 658 3 3 100.00
IF 683 4 4 100.00
IF 709 4 4 100.00
CASE 722 3 3 100.00
IF 744 2 2 100.00
IF 751 2 2 100.00
IF 763 3 3 100.00
IF 784 2 2 100.00
IF 796 2 2 100.00
IF 802 4 4 100.00
IF 813 3 3 100.00
IF 823 3 3 100.00
IF 832 3 3 100.00
IF 852 4 4 100.00
IF 863 4 4 100.00
IF 873 2 2 100.00
CASE 895 6 5 83.33
CASE 937 11 11 100.00
IF 1012 2 2 100.00
IF 1024 2 2 100.00
IF 1052 2 2 100.00
IF 1064 3 3 100.00
IF 1095 2 2 100.00
CASE 1142 37 33 89.19
IF 1382 4 4 100.00
IF 1394 5 5 100.00
IF 1409 4 4 100.00
IF 1470 4 4 100.00
IF 1480 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 525 if ((!sys_rst_ni)) -2-: 529 if (sys_csb_asserted_pulse)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 542 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 555 if ((!rst_ni)) -2-: 557 if (cmdaddr_shift_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 594 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 602 if ((!rst_ni)) -2-: 604 if (cmdaddr_shift_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 610 if (cmdaddr_shift_en)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 620 if ((!rst_out_ni)) -2-: 622 if (isck_fifoaddr_latch) -3-: 625 if (isck_fifoaddr_inc)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T8,T9,T27
0 0 0 Covered T5,T8,T9


LineNo. Expression -1-: 648 if ((!rst_ni)) -2-: 650 if (wrdata_shift_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 658 if ((!rst_ni)) -2-: 660 if (wrdata_shift_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 683 if ((!sys_rst_ni)) -2-: 685 if (sys_wrfifo_release_i) -3-: 687 if (sys_wrfifo_release_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 709 if ((!sys_rst_ni)) -2-: 711 if ((sck_cmdaddr_wvalid && (cmd_type == Write))) -3-: 713 if (sck_wrfifo_release_req)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T3,T5


LineNo. Expression -1-: 722 case (1'b1)

Branches:
-1-StatusTests
check_locality Covered T5,T8,T9
check_hw_reg Covered T5,T8,T9
default Covered T1,T2,T3


LineNo. Expression -1-: 744 if ((check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))))

Branches:
-1-StatusTests
1 Covered T5,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 751 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 763 if ((!rst_ni)) -2-: 766 if (((((((!sys_clk_tpm_cfg.tpm_mode) && check_hw_reg) && (cmd_type == Read)) && is_tpm_reg_q) && (!invalid_locality)) && (!sys_clk_tpm_cfg.hw_reg_dis)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T9,T27
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 784 if ((TpmReturnByHwAddr[i][11:2] == addr[11:2]))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 796 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 802 if ((!rst_ni)) -2-: 805 if ((check_locality && is_tpm_reg_d)) -3-: 807 ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality))) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 1 Covered T5,T8,T9
0 1 0 Covered T5,T8,T9
0 0 - Covered T5,T8,T9


LineNo. Expression -1-: 813 if ((!rst_ni)) -2-: 815 if (latch_cmd_type)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 823 if ((!rst_ni)) -2-: 825 if (latch_xfer_size)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 832 if ((!rst_ni)) -2-: 834 if (((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 852 if ((!sys_rst_ni)) -2-: 854 if (sys_csb_asserted_pulse) -3-: 856 if ((sys_rdfifo_wvalid_i & sys_rdfifo_wready_o))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 863 if ((!sys_rst_ni)) -2-: 865 if (sys_csb_asserted_pulse) -3-: 867 if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 873 if ((!sys_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 895 case (isck_data_sel)

Branches:
-1-StatusTests
SelWait Covered T1,T2,T3
SelStart Covered T5,T8,T9
SelInvalid Covered T8,T9,T27
SelHwReg Covered T8,T9,T27
SelRdFifo Covered T5,T8,T9
default Not Covered


LineNo. Expression -1-: 937 case (isck_hw_reg_idx) -2-: 965 if (((!invalid_locality) && sys_active_locality[locality[2:0]]))

Branches:
-1--2-StatusTests
RegAccess - Covered T1,T2,T3
RegIntEn - Covered T1,T2,T3
RegIntVect - Covered T1,T2,T3
RegIntSts - Covered T1,T2,T3
RegIntfCap - Covered T1,T2,T3
RegSts 1 Covered T1,T2,T3
RegSts 0 Covered T1,T2,T3
RegHashStart - Covered T1,T2,T3
RegId - Covered T1,T2,T3
RegRid - Covered T1,T2,T3
default - Covered T1,T2,T3


LineNo. Expression -1-: 1012 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 1024 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 1052 if ((!rst_out_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 1064 if ((!rst_ni)) -2-: 1066 if (isck_rd_byte_sent)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


LineNo. Expression -1-: 1095 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T9


LineNo. Expression -1-: 1142 case (sck_st_q) -2-: 1146 if ((cmdaddr_bitcnt == 5'h07)) -3-: 1147 if (sys_clk_tpm_en) -4-: 1167 if ((cmdaddr_bitcnt >= 5'h18)) -5-: 1174 if ((cmdaddr_bitcnt == 5'h1b)) -6-: 1179 if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))) -7-: 1180 if (((!is_tpm_reg_q) || sys_clk_tpm_cfg.tpm_mode)) -8-: 1188 if ((sck_cmdaddr_wdepth == '0)) -9-: 1191 if (is_hw_reg) -10-: 1195 if ((invalid_locality && sys_clk_tpm_cfg.invalid_locality)) -11-: 1206 if ((sck_cmdaddr_wdepth == '0)) -12-: 1212 if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))) -13-: 1213 if (((!sck_wrfifo_busy) && (~|sck_cmdaddr_wdepth))) -14-: 1229 if ((((cmd_type == Read) && (!sck_rdfifo_cmd_pending)) && (~|sck_cmdaddr_wdepth))) -15-: 1234 if ((isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || (((cmd_type == Write) && (!sck_wrfifo_busy)) && (~|sck_cmdaddr_wdepth))))) -16-: 1245 if (isck_p2s_sent) -17-: 1247 if (((cmd_type == Read) && is_hw_reg)) -18-: 1249 if ((cmd_type == Read)) -19-: 1251 if ((cmd_type == Write)) -20-: 1263 if ((isck_p2s_sent && xfer_size_met)) -21-: 1274 if ((isck_p2s_sent && xfer_size_met)) -22-: 1283 if ((sck_wrfifo_wvalid && xfer_size_met)) -23-: 1292 if ((cmd_type == Read)) -24-: 1299 if ((cmd_type == Read))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24-StatusTests
StIdle 1 1 - - - - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StIdle 1 0 - - - - - - - - - - - - - - - - - - - - - Not Covered
StIdle 0 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
StAddr - - 1 - - - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - 0 - - - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - 1 - - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - 0 - - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - 1 1 1 - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - 1 1 0 - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - 1 0 - 1 - - - - - - - - - - - - - - - Covered T8,T9,T27
StAddr - - - - 1 0 - 0 1 - - - - - - - - - - - - - - Covered T8,T9,T27
StAddr - - - - 1 0 - 0 0 1 - - - - - - - - - - - - - Covered T8,T9,T29
StAddr - - - - 1 0 - 0 0 0 - - - - - - - - - - - - - Covered T8,T9,T29
StAddr - - - - 0 - - - - - - - - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - - - - - - - 1 1 - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - - - - - - - 1 0 - - - - - - - - - - - Covered T5,T8,T9
StAddr - - - - - - - - - - 0 - - - - - - - - - - - - Covered T5,T8,T9
StWait - - - - - - - - - - - - 1 - - - - - - - - - - Covered T5,T8,T9
StWait - - - - - - - - - - - - 0 - - - - - - - - - - Covered T5,T8,T9
StWait - - - - - - - - - - - - - 1 - - - - - - - - - Covered T5,T8,T9
StWait - - - - - - - - - - - - - 0 - - - - - - - - - Covered T5,T8,T9
StStartByte - - - - - - - - - - - - - - 1 1 - - - - - - - Covered T8,T9,T27
StStartByte - - - - - - - - - - - - - - 1 0 1 - - - - - - Covered T5,T8,T9
StStartByte - - - - - - - - - - - - - - 1 0 0 1 - - - - - Covered T5,T8,T9
StStartByte - - - - - - - - - - - - - - 1 0 0 0 - - - - - Not Covered
StStartByte - - - - - - - - - - - - - - 0 - - - - - - - - Covered T5,T8,T9
StReadFifo - - - - - - - - - - - - - - - - - - 1 - - - - Covered T5,T8,T9
StReadFifo - - - - - - - - - - - - - - - - - - 0 - - - - Covered T5,T8,T9
StReadHwReg - - - - - - - - - - - - - - - - - - - 1 - - - Covered T8,T9,T27
StReadHwReg - - - - - - - - - - - - - - - - - - - 0 - - - Covered T8,T9,T27
StWrite - - - - - - - - - - - - - - - - - - - - 1 - - Covered T5,T8,T9
StWrite - - - - - - - - - - - - - - - - - - - - 0 - - Covered T5,T8,T9
StInvalid - - - - - - - - - - - - - - - - - - - - - 1 - Covered T8,T9,T27
StInvalid - - - - - - - - - - - - - - - - - - - - - 0 - Not Covered
StEnd - - - - - - - - - - - - - - - - - - - - - - 1 Covered T5,T8,T9
StEnd - - - - - - - - - - - - - - - - - - - - - - 0 Covered T5,T8,T9
default - - - - - - - - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 1382 if ((!sys_rst_ni)) -2-: 1384 if (sys_csb_deasserted_pulse) -3-: 1386 if (((sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o) & sys_cmdaddr_rready_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1394 if ((!sys_rst_ni)) -2-: 1396 if ((cmdaddr_bitcnt == 5'h0f)) -3-: 1401 if ((sck_cmdaddr_wvalid && (cmd_type == Read))) -4-: 1403 if (((isck_p2s_sent && xfer_size_met) && (sck_st_q == StReadFifo)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T5,T8,T9
0 0 1 - Covered T5,T8,T9
0 0 0 1 Covered T5,T8,T9
0 0 0 0 Covered T1,T3,T5


LineNo. Expression -1-: 1409 if ((!sys_rst_ni)) -2-: 1411 if ((sys_csb_deasserted_pulse & (!sys_rdfifo_sync_clr))) -3-: 1418 if ((sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1470 if ((!rst_ni)) -2-: 1472 if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])) -3-: 1474 if (sck_sram_rvalid[SramRdFifo])

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T9
0 0 1 Covered T5,T8,T9
0 0 0 Covered T5,T8,T9


LineNo. Expression -1-: 1480 if ((!rst_ni)) -2-: 1482 if ((sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T9
0 0 Covered T5,T8,T9


Assert Coverage for Module : spi_tpm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CmdAddrAvailable_A 144838004 48258 0 0
CmdAddrBitCntInAddrSt_A 144838004 504728 0 0
CmdAddrInfo_A 144838004 50396 0 0
CmdPowerof2_A 976 976 0 0
DataFifoLessThan64_A 976 976 0 0
DataSelKnown_A 144838954 29353223 0 0
HwRegCondition2_a 144838004 9277 0 0
HwRegCondition_A 144838004 63091 0 0
HwRegIdxKnown_A 144838954 29353223 0 0
LocalityLatchCondition_A 144838004 63091 0 0
RdFifoDepthPoT_A 976 976 0 0
RdFifoNumBytesPoT_A 976 976 0 0
RdPowerof2_A 976 976 0 0
SckFifoAddrLatchCondition_A 144838004 63091 0 0
TpmRegSizeMatch_A 976 976 0 0
WrDepthSpec_A 976 976 0 0
WrFifoAvailable_A 144838004 415838 0 0


CmdAddrAvailable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 48258 0 0
T5 124055 357 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 202 0 0
T9 231924 408 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T15 0 224 0 0
T28 0 333 0 0
T29 0 464 0 0
T30 0 7 0 0
T31 0 90 0 0
T46 0 299 0 0
T48 0 214 0 0

CmdAddrBitCntInAddrSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 504728 0 0
T5 124055 2856 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 2088 0 0
T9 231924 4104 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T27 0 2496 0 0
T28 0 2664 0 0
T29 0 4192 0 0
T30 0 56 0 0
T31 0 920 0 0
T32 0 24 0 0
T33 0 16 0 0

CmdAddrInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 50396 0 0
T5 124055 294 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 183 0 0
T9 231924 366 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T27 0 312 0 0
T28 0 253 0 0
T29 0 358 0 0
T30 0 7 0 0
T31 0 99 0 0
T32 0 3 0 0
T33 0 2 0 0

CmdPowerof2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

DataFifoLessThan64_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

DataSelKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838954 29353223 0 0
T5 124056 118328 0 0
T6 18095 0 0 0
T7 20876 0 0 0
T8 264945 211424 0 0
T9 231925 224640 0 0
T10 49405 0 0 0
T11 143 0 0 0
T12 483473 0 0 0
T13 15280 0 0 0
T14 762318 0 0 0
T27 0 63344 0 0
T28 0 408528 0 0
T29 0 340248 0 0
T30 0 1984 0 0
T31 0 84552 0 0
T32 0 216 0 0
T33 0 144 0 0

HwRegCondition2_a
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 9277 0 0
T8 264944 30 0 0
T9 231924 54 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T15 0 19 0 0
T24 18630 0 0 0
T25 243419 0 0 0
T27 0 201 0 0
T29 0 36 0 0
T31 0 25 0 0
T32 0 3 0 0
T33 0 2 0 0
T47 4128 0 0 0
T48 0 25 0 0
T86 0 14 0 0

HwRegCondition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 63091 0 0
T5 124055 357 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 261 0 0
T9 231924 513 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T27 0 312 0 0
T28 0 333 0 0
T29 0 524 0 0
T30 0 7 0 0
T31 0 115 0 0
T32 0 3 0 0
T33 0 2 0 0

HwRegIdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838954 29353223 0 0
T5 124056 118328 0 0
T6 18095 0 0 0
T7 20876 0 0 0
T8 264945 211424 0 0
T9 231925 224640 0 0
T10 49405 0 0 0
T11 143 0 0 0
T12 483473 0 0 0
T13 15280 0 0 0
T14 762318 0 0 0
T27 0 63344 0 0
T28 0 408528 0 0
T29 0 340248 0 0
T30 0 1984 0 0
T31 0 84552 0 0
T32 0 216 0 0
T33 0 144 0 0

LocalityLatchCondition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 63091 0 0
T5 124055 357 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 261 0 0
T9 231924 513 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T27 0 312 0 0
T28 0 333 0 0
T29 0 524 0 0
T30 0 7 0 0
T31 0 115 0 0
T32 0 3 0 0
T33 0 2 0 0

RdFifoDepthPoT_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

RdFifoNumBytesPoT_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

RdPowerof2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SckFifoAddrLatchCondition_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 63091 0 0
T5 124055 357 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 261 0 0
T9 231924 513 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T27 0 312 0 0
T28 0 333 0 0
T29 0 524 0 0
T30 0 7 0 0
T31 0 115 0 0
T32 0 3 0 0
T33 0 2 0 0

TpmRegSizeMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

WrDepthSpec_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976 976 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

WrFifoAvailable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 144838004 415838 0 0
T5 124055 2493 0 0
T6 18094 0 0 0
T7 20876 0 0 0
T8 264944 1953 0 0
T9 231924 3872 0 0
T10 49404 0 0 0
T11 142 0 0 0
T12 483472 0 0 0
T13 15279 0 0 0
T14 762317 0 0 0
T15 0 1978 0 0
T28 0 2209 0 0
T29 0 4050 0 0
T30 0 121 0 0
T31 0 361 0 0
T46 0 2365 0 0
T48 0 2241 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%