Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	2886166	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	2886166	0	0
T1	24204	1663	0	0
T2	1634	0	0	0
T3	21890	1663	0	0
T4	1203	0	0	0
T5	389446	0	0	0
T6	130284	2180	0	0
T7	9424	1665	0	0
T8	103372	1668	0	0
T9	269614	0	0	0
T10	300554	1663	0	0
T11	0	832	0	0
T12	0	8332	0	0
T13	0	1859	0	0
T14	0	12475	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	3216044	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	3216044	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	0	0	0
T6	130284	1095	0	0
T7	9424	834	0	0
T8	103372	837	0	0
T9	269614	0	0	0
T10	300554	832	0	0
T11	0	832	0	0
T12	0	7834	0	0
T13	0	4402	0	0
T14	0	8320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	191739	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	191739	0	0
T5	389446	642	0	0
T6	130284	0	0	0
T7	9424	0	0	0
T8	103372	633	0	0
T9	269614	1000	0	0
T10	300554	32	0	0
T11	2711	0	0	0
T12	147562	65	0	0
T13	71745	0	0	0
T14	615491	480	0	0
T25	0	64	0	0
T28	0	760	0	0
T29	0	1436	0	0
T40	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	467887	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	467887	0	0
T5	389446	2188	0	0
T6	130284	0	0	0
T7	9424	0	0	0
T8	103372	2590	0	0
T9	269614	4535	0	0
T10	300554	32	0	0
T11	2711	0	0	0
T12	147562	299	0	0
T13	71745	0	0	0
T14	615491	480	0	0
T25	0	64	0	0
T28	0	759	0	0
T29	0	1435	0	0
T40	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	5579119	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	5579119	0	0
T1	24204	809	0	0
T2	1634	17	0	0
T3	21890	918	0	0
T4	1203	10	0	0
T5	389446	8070	0	0
T6	130284	3351	0	0
T7	9424	332	0	0
T8	103372	3650	0	0
T9	269614	7605	0	0
T10	300554	499	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431718072	12543941	0	0
DepthKnown_A	431718072	431590661	0	0
RvalidKnown_A	431718072	431590661	0	0
WreadyKnown_A	431718072	431590661	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	12543941	0	0
T1	24204	809	0	0
T2	1634	59	0	0
T3	21890	3868	0	0
T4	1203	10	0	0
T5	389446	24155	0	0
T6	130284	14572	0	0
T7	9424	1388	0	0
T8	103372	14400	0	0
T9	269614	31374	0	0
T10	300554	499	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431718072	431590661	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0