Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T8,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	719419727	573165280	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	719419727	3772834	0	0
GntImpliesValid_A	719419727	3772834	0	0
GrantKnown_A	719419727	573165280	0	0
IdxKnown_A	719419727	573165280	0	0
IndexIsCorrect_A	719419727	3772834	0	0
LockArbDecision_A	719419727	0	0	0
NoReadyValidNoGrant_A	719419727	0	0	0
ReadyAndValidImplyGrant_A	719419727	3772834	0	0
ReqAndReadyImplyGrant_A	719419727	3772834	0	0
ReqImpliesValid_A	719419727	3772834	0	0
ReqStaysHighUntilGranted0_M	719419727	0	0	0
RoundRobin_A	719419727	8	0	976
ValidKnown_A	719419727	573165280	0	0
gen_data_port_assertion.DataFlow_A	719419727	3772834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	573165280	0	0
T1	45090	44561	0	0
T2	1634	1535	0	0
T3	28122	28048	0	0
T4	1203	1134	0	0
T5	637556	507720	0	0
T6	166472	148283	0	0
T7	51176	29997	0	0
T8	633260	366004	0	0
T9	733462	494155	0	0
T10	399362	349540	0	0
T11	284	142	0	0
T12	966944	482359	0	0
T13	15279	15279	0	0
T14	762317	759858	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	573165280	0	0
T1	45090	44561	0	0
T2	1634	1535	0	0
T3	28122	28048	0	0
T4	1203	1134	0	0
T5	637556	507720	0	0
T6	166472	148283	0	0
T7	51176	29997	0	0
T8	633260	366004	0	0
T9	733462	494155	0	0
T10	399362	349540	0	0
T11	284	142	0	0
T12	966944	482359	0	0
T13	15279	15279	0	0
T14	762317	759858	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	573165280	0	0
T1	45090	44561	0	0
T2	1634	1535	0	0
T3	28122	28048	0	0
T4	1203	1134	0	0
T5	637556	507720	0	0
T6	166472	148283	0	0
T7	51176	29997	0	0
T8	633260	366004	0	0
T9	733462	494155	0	0
T10	399362	349540	0	0
T11	284	142	0	0
T12	966944	482359	0	0
T13	15279	15279	0	0
T14	762317	759858	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	8	0	976
T35	0	1	0	0
T46	829508	0	0	1
T48	178187	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	126409	0	0	1
T56	1467	0	0	1
T57	123566	0	0	1
T58	18560	0	0	1
T59	5691	0	0	1
T60	2899	0	0	1
T61	940969	0	0	1
T62	146500	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	573165280	0	0
T1	45090	44561	0	0
T2	1634	1535	0	0
T3	28122	28048	0	0
T4	1203	1134	0	0
T5	637556	507720	0	0
T6	166472	148283	0	0
T7	51176	29997	0	0
T8	633260	366004	0	0
T9	733462	494155	0	0
T10	399362	349540	0	0
T11	284	142	0	0
T12	966944	482359	0	0
T13	15279	15279	0	0
T14	762317	759858	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719419727	3772834	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	513501	6434	0	0
T6	148378	1088	0	0
T7	30300	832	0	0
T8	633260	7587	0	0
T9	733462	8188	0	0
T10	399362	1004	0	0
T11	284	832	0	0
T12	966944	6633	0	0
T13	30558	0	0	0
T14	1524634	5867	0	0
T15	0	3006	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	5264	0	0
T29	0	9520	0	0
T30	0	141	0	0
T31	0	714	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T46	0	3680	0	0
T47	4128	0	0	0
T48	0	3121	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144838004	29353223	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	144838004	624926	0	0
GntImpliesValid_A	144838004	624926	0	0
GrantKnown_A	144838004	29353223	0	0
IdxKnown_A	144838004	29353223	0	0
IndexIsCorrect_A	144838004	624926	0	0
LockArbDecision_A	144838004	0	0	0
NoReadyValidNoGrant_A	144838004	0	0	0
ReadyAndValidImplyGrant_A	144838004	624926	0	0
ReqAndReadyImplyGrant_A	144838004	624926	0	0
ReqImpliesValid_A	144838004	624926	0	0
ReqStaysHighUntilGranted0_M	144838004	0	0	0
RoundRobin_A	144838004	0	0	0
ValidKnown_A	144838004	29353223	0	0
gen_data_port_assertion.DataFlow_A	144838004	624926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	29353223	0	0
T5	124055	118328	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	211424	0	0
T9	231924	224640	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	29353223	0	0
T5	124055	118328	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	211424	0	0
T9	231924	224640	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	29353223	0	0
T5	124055	118328	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	211424	0	0
T9	231924	224640	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	29353223	0	0
T5	124055	118328	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	211424	0	0
T9	231924	224640	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T27	0	63344	0	0
T28	0	408528	0	0
T29	0	340248	0	0
T30	0	1984	0	0
T31	0	84552	0	0
T32	0	216	0	0
T33	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	624926	0	0
T5	124055	4215	0	0
T6	18094	0	0	0
T7	20876	0	0	0
T8	264944	2643	0	0
T9	231924	5603	0	0
T10	49404	0	0	0
T11	142	0	0	0
T12	483472	0	0	0
T13	15279	0	0	0
T14	762317	0	0	0
T15	0	3006	0	0
T28	0	3968	0	0
T29	0	5672	0	0
T30	0	141	0	0
T31	0	714	0	0
T46	0	3680	0	0
T48	0	3121	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T8,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144838004	114154451	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	144838004	880553	0	0
GntImpliesValid_A	144838004	880553	0	0
GrantKnown_A	144838004	114154451	0	0
IdxKnown_A	144838004	114154451	0	0
IndexIsCorrect_A	144838004	880553	0	0
LockArbDecision_A	144838004	0	0	0
NoReadyValidNoGrant_A	144838004	0	0	0
ReadyAndValidImplyGrant_A	144838004	880553	0	0
ReqAndReadyImplyGrant_A	144838004	880553	0	0
ReqImpliesValid_A	144838004	880553	0	0
ReqStaysHighUntilGranted0_M	144838004	0	0	0
RoundRobin_A	144838004	0	0	0
ValidKnown_A	144838004	114154451	0	0
gen_data_port_assertion.DataFlow_A	144838004	880553	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	114154451	0	0
T1	20886	20408	0	0
T3	6232	6232	0	0
T5	124055	0	0	0
T6	18094	18094	0	0
T7	20876	20670	0	0
T8	264944	51694	0	0
T9	231924	0	0	0
T10	49404	49047	0	0
T11	142	142	0	0
T12	483472	482359	0	0
T13	0	15279	0	0
T14	0	759858	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	114154451	0	0
T1	20886	20408	0	0
T3	6232	6232	0	0
T5	124055	0	0	0
T6	18094	18094	0	0
T7	20876	20670	0	0
T8	264944	51694	0	0
T9	231924	0	0	0
T10	49404	49047	0	0
T11	142	142	0	0
T12	483472	482359	0	0
T13	0	15279	0	0
T14	0	759858	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	114154451	0	0
T1	20886	20408	0	0
T3	6232	6232	0	0
T5	124055	0	0	0
T6	18094	18094	0	0
T7	20876	20670	0	0
T8	264944	51694	0	0
T9	231924	0	0	0
T10	49404	49047	0	0
T11	142	142	0	0
T12	483472	482359	0	0
T13	0	15279	0	0
T14	0	759858	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	114154451	0	0
T1	20886	20408	0	0
T3	6232	6232	0	0
T5	124055	0	0	0
T6	18094	18094	0	0
T7	20876	20670	0	0
T8	264944	51694	0	0
T9	231924	0	0	0
T10	49404	49047	0	0
T11	142	142	0	0
T12	483472	482359	0	0
T13	0	15279	0	0
T14	0	759858	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144838004	880553	0	0
T8	264944	2916	0	0
T9	231924	0	0	0
T10	49404	134	0	0
T11	142	0	0	0
T12	483472	1572	0	0
T13	15279	0	0	0
T14	762317	5867	0	0
T24	18630	0	0	0
T25	243419	265	0	0
T28	0	1296	0	0
T29	0	3848	0	0
T40	0	2160	0	0
T44	0	11843	0	0
T47	4128	0	0	0
T63	0	3689	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429743719	429657606	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	429743719	2267355	0	0
GntImpliesValid_A	429743719	2267355	0	0
GrantKnown_A	429743719	429657606	0	0
IdxKnown_A	429743719	429657606	0	0
IndexIsCorrect_A	429743719	2267355	0	0
LockArbDecision_A	429743719	0	0	0
NoReadyValidNoGrant_A	429743719	0	0	0
ReadyAndValidImplyGrant_A	429743719	2267355	0	0
ReqAndReadyImplyGrant_A	429743719	2267355	0	0
ReqImpliesValid_A	429743719	2267355	0	0
ReqStaysHighUntilGranted0_M	429743719	0	0	0
RoundRobin_A	429743719	8	0	976
ValidKnown_A	429743719	429657606	0	0
gen_data_port_assertion.DataFlow_A	429743719	2267355	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	429657606	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	429657606	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	429657606	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	8	0	976
T35	0	1	0	0
T46	829508	0	0	1
T48	178187	1	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	126409	0	0	1
T56	1467	0	0	1
T57	123566	0	0	1
T58	18560	0	0	1
T59	5691	0	0	1
T60	2899	0	0	1
T61	940969	0	0	1
T62	146500	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	429657606	0	0
T1	24204	24153	0	0
T2	1634	1535	0	0
T3	21890	21816	0	0
T4	1203	1134	0	0
T5	389446	389392	0	0
T6	130284	130189	0	0
T7	9424	9327	0	0
T8	103372	102886	0	0
T9	269614	269515	0	0
T10	300554	300493	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429743719	2267355	0	0
T1	24204	832	0	0
T2	1634	0	0	0
T3	21890	832	0	0
T4	1203	0	0	0
T5	389446	2219	0	0
T6	130284	1088	0	0
T7	9424	832	0	0
T8	103372	2028	0	0
T9	269614	2585	0	0
T10	300554	870	0	0
T11	0	832	0	0
T12	0	5061	0	0