Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3424 |
0 |
0 |
T91 |
2323 |
3 |
0 |
0 |
T92 |
12329 |
140 |
0 |
0 |
T93 |
71008 |
2 |
0 |
0 |
T94 |
2210 |
40 |
0 |
0 |
T95 |
6320 |
241 |
0 |
0 |
T96 |
29203 |
5 |
0 |
0 |
T97 |
19252 |
3 |
0 |
0 |
T106 |
4047 |
8 |
0 |
0 |
T108 |
3838 |
5 |
0 |
0 |
T109 |
9835 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2263 |
0 |
0 |
T93 |
71008 |
72 |
0 |
0 |
T110 |
10176 |
13 |
0 |
0 |
T115 |
74631 |
508 |
0 |
0 |
T120 |
234707 |
436 |
0 |
0 |
T149 |
34593 |
42 |
0 |
0 |
T150 |
19536 |
52 |
0 |
0 |
T151 |
5445 |
7 |
0 |
0 |
T152 |
4278 |
1 |
0 |
0 |
T153 |
14352 |
29 |
0 |
0 |
T154 |
19947 |
103 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2149 |
0 |
0 |
T81 |
1772 |
2 |
0 |
0 |
T93 |
71008 |
58 |
0 |
0 |
T98 |
17746 |
2 |
0 |
0 |
T110 |
10176 |
15 |
0 |
0 |
T115 |
74631 |
439 |
0 |
0 |
T120 |
234707 |
425 |
0 |
0 |
T149 |
34593 |
33 |
0 |
0 |
T150 |
19536 |
66 |
0 |
0 |
T151 |
5445 |
2 |
0 |
0 |
T153 |
14352 |
42 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2664 |
0 |
0 |
T93 |
71008 |
189 |
0 |
0 |
T110 |
10176 |
17 |
0 |
0 |
T115 |
74631 |
588 |
0 |
0 |
T120 |
234707 |
334 |
0 |
0 |
T141 |
4536 |
6 |
0 |
0 |
T149 |
34593 |
92 |
0 |
0 |
T150 |
19536 |
82 |
0 |
0 |
T151 |
5445 |
13 |
0 |
0 |
T152 |
4278 |
9 |
0 |
0 |
T153 |
14352 |
41 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
7878 |
0 |
0 |
T93 |
71008 |
1202 |
0 |
0 |
T110 |
10176 |
295 |
0 |
0 |
T115 |
74631 |
511 |
0 |
0 |
T120 |
234707 |
409 |
0 |
0 |
T141 |
4536 |
76 |
0 |
0 |
T149 |
34593 |
635 |
0 |
0 |
T150 |
19536 |
71 |
0 |
0 |
T151 |
5445 |
9 |
0 |
0 |
T152 |
4278 |
79 |
0 |
0 |
T153 |
14352 |
44 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
6767 |
0 |
0 |
T93 |
71008 |
1053 |
0 |
0 |
T110 |
10176 |
231 |
0 |
0 |
T115 |
74631 |
481 |
0 |
0 |
T120 |
234707 |
462 |
0 |
0 |
T149 |
34593 |
627 |
0 |
0 |
T150 |
19536 |
63 |
0 |
0 |
T151 |
5445 |
57 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
33 |
0 |
0 |
T154 |
19947 |
95 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
6200 |
0 |
0 |
T92 |
12329 |
4 |
0 |
0 |
T93 |
71008 |
1045 |
0 |
0 |
T110 |
10176 |
116 |
0 |
0 |
T115 |
74631 |
475 |
0 |
0 |
T141 |
4536 |
9 |
0 |
0 |
T149 |
34593 |
373 |
0 |
0 |
T150 |
19536 |
142 |
0 |
0 |
T151 |
5445 |
70 |
0 |
0 |
T152 |
4278 |
67 |
0 |
0 |
T153 |
14352 |
23 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
6935 |
0 |
0 |
T81 |
1772 |
1 |
0 |
0 |
T93 |
71008 |
1337 |
0 |
0 |
T110 |
10176 |
136 |
0 |
0 |
T115 |
74631 |
446 |
0 |
0 |
T141 |
4536 |
68 |
0 |
0 |
T149 |
34593 |
588 |
0 |
0 |
T150 |
19536 |
62 |
0 |
0 |
T151 |
5445 |
66 |
0 |
0 |
T152 |
4278 |
94 |
0 |
0 |
T153 |
14352 |
61 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
6432 |
0 |
0 |
T93 |
71008 |
1416 |
0 |
0 |
T110 |
10176 |
143 |
0 |
0 |
T115 |
74631 |
491 |
0 |
0 |
T120 |
234707 |
332 |
0 |
0 |
T149 |
34593 |
279 |
0 |
0 |
T150 |
19536 |
58 |
0 |
0 |
T151 |
5445 |
13 |
0 |
0 |
T152 |
4278 |
93 |
0 |
0 |
T153 |
14352 |
35 |
0 |
0 |
T154 |
19947 |
78 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
7434 |
0 |
0 |
T81 |
1772 |
7 |
0 |
0 |
T93 |
71008 |
1300 |
0 |
0 |
T110 |
10176 |
140 |
0 |
0 |
T115 |
74631 |
549 |
0 |
0 |
T120 |
234707 |
380 |
0 |
0 |
T149 |
34593 |
535 |
0 |
0 |
T150 |
19536 |
65 |
0 |
0 |
T152 |
4278 |
108 |
0 |
0 |
T153 |
14352 |
40 |
0 |
0 |
T154 |
19947 |
69 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
7215 |
0 |
0 |
T93 |
71008 |
1613 |
0 |
0 |
T110 |
10176 |
14 |
0 |
0 |
T115 |
74631 |
508 |
0 |
0 |
T120 |
234707 |
362 |
0 |
0 |
T141 |
4536 |
43 |
0 |
0 |
T149 |
34593 |
911 |
0 |
0 |
T150 |
19536 |
29 |
0 |
0 |
T151 |
5445 |
7 |
0 |
0 |
T152 |
4278 |
42 |
0 |
0 |
T153 |
14352 |
33 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
6283 |
0 |
0 |
T92 |
12329 |
1 |
0 |
0 |
T93 |
71008 |
1189 |
0 |
0 |
T110 |
10176 |
135 |
0 |
0 |
T115 |
74631 |
503 |
0 |
0 |
T120 |
234707 |
459 |
0 |
0 |
T149 |
34593 |
468 |
0 |
0 |
T150 |
19536 |
93 |
0 |
0 |
T151 |
5445 |
45 |
0 |
0 |
T153 |
14352 |
81 |
0 |
0 |
T154 |
19947 |
27 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4139 |
0 |
0 |
T81 |
1772 |
3 |
0 |
0 |
T93 |
71008 |
669 |
0 |
0 |
T110 |
10176 |
23 |
0 |
0 |
T115 |
74631 |
540 |
0 |
0 |
T120 |
234707 |
399 |
0 |
0 |
T141 |
4536 |
10 |
0 |
0 |
T149 |
34593 |
217 |
0 |
0 |
T150 |
19536 |
38 |
0 |
0 |
T151 |
5445 |
41 |
0 |
0 |
T153 |
14352 |
33 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3882 |
0 |
0 |
T81 |
1772 |
7 |
0 |
0 |
T93 |
71008 |
448 |
0 |
0 |
T110 |
10176 |
58 |
0 |
0 |
T115 |
74631 |
493 |
0 |
0 |
T141 |
4536 |
20 |
0 |
0 |
T149 |
34593 |
197 |
0 |
0 |
T150 |
19536 |
66 |
0 |
0 |
T151 |
5445 |
1 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
51 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4491 |
0 |
0 |
T93 |
71008 |
570 |
0 |
0 |
T110 |
10176 |
22 |
0 |
0 |
T115 |
74631 |
554 |
0 |
0 |
T120 |
234707 |
471 |
0 |
0 |
T141 |
4536 |
48 |
0 |
0 |
T149 |
34593 |
270 |
0 |
0 |
T150 |
19536 |
72 |
0 |
0 |
T152 |
4278 |
1 |
0 |
0 |
T153 |
14352 |
68 |
0 |
0 |
T154 |
19947 |
135 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3753 |
0 |
0 |
T81 |
1772 |
2 |
0 |
0 |
T93 |
71008 |
571 |
0 |
0 |
T110 |
10176 |
77 |
0 |
0 |
T115 |
74631 |
460 |
0 |
0 |
T120 |
234707 |
394 |
0 |
0 |
T149 |
34593 |
206 |
0 |
0 |
T150 |
19536 |
85 |
0 |
0 |
T151 |
5445 |
32 |
0 |
0 |
T152 |
4278 |
29 |
0 |
0 |
T153 |
14352 |
38 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3536 |
0 |
0 |
T93 |
71008 |
433 |
0 |
0 |
T110 |
10176 |
58 |
0 |
0 |
T115 |
74631 |
480 |
0 |
0 |
T120 |
234707 |
399 |
0 |
0 |
T141 |
4536 |
29 |
0 |
0 |
T149 |
34593 |
249 |
0 |
0 |
T150 |
19536 |
79 |
0 |
0 |
T151 |
5445 |
4 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
45 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3806 |
0 |
0 |
T81 |
1772 |
5 |
0 |
0 |
T93 |
71008 |
468 |
0 |
0 |
T110 |
10176 |
67 |
0 |
0 |
T115 |
74631 |
435 |
0 |
0 |
T120 |
234707 |
395 |
0 |
0 |
T149 |
34593 |
264 |
0 |
0 |
T150 |
19536 |
98 |
0 |
0 |
T151 |
5445 |
15 |
0 |
0 |
T152 |
4278 |
1 |
0 |
0 |
T153 |
14352 |
49 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3744 |
0 |
0 |
T93 |
71008 |
620 |
0 |
0 |
T110 |
10176 |
72 |
0 |
0 |
T115 |
74631 |
498 |
0 |
0 |
T120 |
234707 |
366 |
0 |
0 |
T141 |
4536 |
7 |
0 |
0 |
T149 |
34593 |
273 |
0 |
0 |
T150 |
19536 |
47 |
0 |
0 |
T151 |
5445 |
20 |
0 |
0 |
T152 |
4278 |
26 |
0 |
0 |
T153 |
14352 |
8 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3914 |
0 |
0 |
T93 |
71008 |
603 |
0 |
0 |
T110 |
10176 |
11 |
0 |
0 |
T115 |
74631 |
459 |
0 |
0 |
T120 |
234707 |
347 |
0 |
0 |
T141 |
4536 |
3 |
0 |
0 |
T149 |
34593 |
439 |
0 |
0 |
T150 |
19536 |
28 |
0 |
0 |
T151 |
5445 |
12 |
0 |
0 |
T153 |
14352 |
41 |
0 |
0 |
T154 |
19947 |
22 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4184 |
0 |
0 |
T93 |
71008 |
669 |
0 |
0 |
T110 |
10176 |
60 |
0 |
0 |
T115 |
74631 |
501 |
0 |
0 |
T120 |
234707 |
396 |
0 |
0 |
T141 |
4536 |
24 |
0 |
0 |
T149 |
34593 |
257 |
0 |
0 |
T150 |
19536 |
65 |
0 |
0 |
T151 |
5445 |
4 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
47 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3789 |
0 |
0 |
T81 |
1772 |
5 |
0 |
0 |
T93 |
71008 |
530 |
0 |
0 |
T110 |
10176 |
61 |
0 |
0 |
T115 |
74631 |
532 |
0 |
0 |
T141 |
4536 |
26 |
0 |
0 |
T149 |
34593 |
135 |
0 |
0 |
T150 |
19536 |
83 |
0 |
0 |
T151 |
5445 |
34 |
0 |
0 |
T152 |
4278 |
37 |
0 |
0 |
T153 |
14352 |
79 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4119 |
0 |
0 |
T93 |
71008 |
570 |
0 |
0 |
T110 |
10176 |
112 |
0 |
0 |
T115 |
74631 |
494 |
0 |
0 |
T120 |
234707 |
397 |
0 |
0 |
T149 |
34593 |
264 |
0 |
0 |
T150 |
19536 |
32 |
0 |
0 |
T151 |
5445 |
32 |
0 |
0 |
T152 |
4278 |
29 |
0 |
0 |
T153 |
14352 |
30 |
0 |
0 |
T154 |
19947 |
36 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3978 |
0 |
0 |
T81 |
1772 |
1 |
0 |
0 |
T93 |
71008 |
668 |
0 |
0 |
T110 |
10176 |
11 |
0 |
0 |
T115 |
74631 |
503 |
0 |
0 |
T141 |
4536 |
1 |
0 |
0 |
T149 |
34593 |
183 |
0 |
0 |
T150 |
19536 |
63 |
0 |
0 |
T151 |
5445 |
3 |
0 |
0 |
T152 |
4278 |
15 |
0 |
0 |
T153 |
14352 |
53 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4135 |
0 |
0 |
T93 |
71008 |
338 |
0 |
0 |
T110 |
10176 |
51 |
0 |
0 |
T115 |
74631 |
489 |
0 |
0 |
T120 |
234707 |
402 |
0 |
0 |
T141 |
4536 |
29 |
0 |
0 |
T149 |
34593 |
264 |
0 |
0 |
T150 |
19536 |
101 |
0 |
0 |
T152 |
4278 |
23 |
0 |
0 |
T153 |
14352 |
81 |
0 |
0 |
T154 |
19947 |
62 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3641 |
0 |
0 |
T81 |
1772 |
7 |
0 |
0 |
T93 |
71008 |
302 |
0 |
0 |
T110 |
10176 |
19 |
0 |
0 |
T115 |
74631 |
450 |
0 |
0 |
T120 |
234707 |
419 |
0 |
0 |
T141 |
4536 |
22 |
0 |
0 |
T149 |
34593 |
284 |
0 |
0 |
T150 |
19536 |
56 |
0 |
0 |
T151 |
5445 |
25 |
0 |
0 |
T153 |
14352 |
81 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3991 |
0 |
0 |
T81 |
1772 |
5 |
0 |
0 |
T93 |
71008 |
561 |
0 |
0 |
T110 |
10176 |
61 |
0 |
0 |
T115 |
74631 |
496 |
0 |
0 |
T141 |
4536 |
22 |
0 |
0 |
T149 |
34593 |
195 |
0 |
0 |
T150 |
19536 |
73 |
0 |
0 |
T151 |
5445 |
44 |
0 |
0 |
T152 |
4278 |
21 |
0 |
0 |
T153 |
14352 |
39 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3999 |
0 |
0 |
T93 |
71008 |
593 |
0 |
0 |
T110 |
10176 |
79 |
0 |
0 |
T115 |
74631 |
490 |
0 |
0 |
T120 |
234707 |
391 |
0 |
0 |
T141 |
4536 |
21 |
0 |
0 |
T149 |
34593 |
223 |
0 |
0 |
T150 |
19536 |
79 |
0 |
0 |
T153 |
14352 |
33 |
0 |
0 |
T154 |
19947 |
113 |
0 |
0 |
T155 |
97747 |
795 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3797 |
0 |
0 |
T81 |
1772 |
5 |
0 |
0 |
T93 |
71008 |
468 |
0 |
0 |
T110 |
10176 |
54 |
0 |
0 |
T115 |
74631 |
446 |
0 |
0 |
T120 |
234707 |
446 |
0 |
0 |
T141 |
4536 |
52 |
0 |
0 |
T149 |
34593 |
187 |
0 |
0 |
T150 |
19536 |
36 |
0 |
0 |
T153 |
14352 |
38 |
0 |
0 |
T154 |
19947 |
111 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4090 |
0 |
0 |
T81 |
1772 |
3 |
0 |
0 |
T93 |
71008 |
453 |
0 |
0 |
T110 |
10176 |
21 |
0 |
0 |
T115 |
74631 |
504 |
0 |
0 |
T141 |
4536 |
24 |
0 |
0 |
T149 |
34593 |
234 |
0 |
0 |
T150 |
19536 |
78 |
0 |
0 |
T151 |
5445 |
4 |
0 |
0 |
T152 |
4278 |
15 |
0 |
0 |
T153 |
14352 |
40 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4005 |
0 |
0 |
T93 |
71008 |
593 |
0 |
0 |
T110 |
10176 |
127 |
0 |
0 |
T115 |
74631 |
491 |
0 |
0 |
T120 |
234707 |
453 |
0 |
0 |
T141 |
4536 |
6 |
0 |
0 |
T149 |
34593 |
360 |
0 |
0 |
T150 |
19536 |
29 |
0 |
0 |
T152 |
4278 |
14 |
0 |
0 |
T153 |
14352 |
32 |
0 |
0 |
T154 |
19947 |
84 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3993 |
0 |
0 |
T93 |
71008 |
329 |
0 |
0 |
T110 |
10176 |
68 |
0 |
0 |
T115 |
74631 |
492 |
0 |
0 |
T120 |
234707 |
398 |
0 |
0 |
T141 |
4536 |
26 |
0 |
0 |
T149 |
34593 |
301 |
0 |
0 |
T150 |
19536 |
82 |
0 |
0 |
T151 |
5445 |
24 |
0 |
0 |
T152 |
4278 |
36 |
0 |
0 |
T153 |
14352 |
66 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3993 |
0 |
0 |
T81 |
1772 |
1 |
0 |
0 |
T93 |
71008 |
640 |
0 |
0 |
T110 |
10176 |
55 |
0 |
0 |
T115 |
74631 |
501 |
0 |
0 |
T141 |
4536 |
32 |
0 |
0 |
T149 |
34593 |
287 |
0 |
0 |
T150 |
19536 |
37 |
0 |
0 |
T151 |
5445 |
27 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
29 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3918 |
0 |
0 |
T81 |
1772 |
7 |
0 |
0 |
T93 |
71008 |
580 |
0 |
0 |
T110 |
10176 |
67 |
0 |
0 |
T115 |
74631 |
460 |
0 |
0 |
T120 |
234707 |
383 |
0 |
0 |
T141 |
4536 |
41 |
0 |
0 |
T149 |
34593 |
353 |
0 |
0 |
T150 |
19536 |
16 |
0 |
0 |
T151 |
5445 |
9 |
0 |
0 |
T153 |
14352 |
84 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4124 |
0 |
0 |
T93 |
71008 |
372 |
0 |
0 |
T110 |
10176 |
82 |
0 |
0 |
T115 |
74631 |
505 |
0 |
0 |
T120 |
234707 |
505 |
0 |
0 |
T141 |
4536 |
39 |
0 |
0 |
T149 |
34593 |
262 |
0 |
0 |
T150 |
19536 |
44 |
0 |
0 |
T151 |
5445 |
1 |
0 |
0 |
T153 |
14352 |
42 |
0 |
0 |
T154 |
19947 |
74 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
3889 |
0 |
0 |
T93 |
71008 |
398 |
0 |
0 |
T110 |
10176 |
116 |
0 |
0 |
T115 |
74631 |
534 |
0 |
0 |
T120 |
234707 |
381 |
0 |
0 |
T141 |
4536 |
31 |
0 |
0 |
T149 |
34593 |
225 |
0 |
0 |
T150 |
19536 |
43 |
0 |
0 |
T151 |
5445 |
48 |
0 |
0 |
T152 |
4278 |
39 |
0 |
0 |
T153 |
14352 |
29 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2189 |
0 |
0 |
T81 |
1772 |
3 |
0 |
0 |
T93 |
71008 |
111 |
0 |
0 |
T110 |
10176 |
11 |
0 |
0 |
T115 |
74631 |
479 |
0 |
0 |
T141 |
4536 |
11 |
0 |
0 |
T149 |
34593 |
44 |
0 |
0 |
T150 |
19536 |
37 |
0 |
0 |
T151 |
5445 |
1 |
0 |
0 |
T152 |
4278 |
4 |
0 |
0 |
T153 |
14352 |
50 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2490 |
0 |
0 |
T93 |
71008 |
115 |
0 |
0 |
T110 |
10176 |
8 |
0 |
0 |
T115 |
74631 |
563 |
0 |
0 |
T120 |
234707 |
410 |
0 |
0 |
T141 |
4536 |
4 |
0 |
0 |
T149 |
34593 |
52 |
0 |
0 |
T150 |
19536 |
59 |
0 |
0 |
T151 |
5445 |
9 |
0 |
0 |
T152 |
4278 |
6 |
0 |
0 |
T153 |
14352 |
65 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2338 |
0 |
0 |
T81 |
1772 |
4 |
0 |
0 |
T93 |
71008 |
116 |
0 |
0 |
T110 |
10176 |
12 |
0 |
0 |
T115 |
74631 |
488 |
0 |
0 |
T120 |
234707 |
396 |
0 |
0 |
T149 |
34593 |
76 |
0 |
0 |
T150 |
19536 |
25 |
0 |
0 |
T151 |
5445 |
2 |
0 |
0 |
T152 |
4278 |
6 |
0 |
0 |
T153 |
14352 |
82 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2471 |
0 |
0 |
T93 |
71008 |
105 |
0 |
0 |
T110 |
10176 |
23 |
0 |
0 |
T115 |
74631 |
509 |
0 |
0 |
T120 |
234707 |
478 |
0 |
0 |
T141 |
4536 |
11 |
0 |
0 |
T149 |
34593 |
51 |
0 |
0 |
T150 |
19536 |
32 |
0 |
0 |
T151 |
5445 |
6 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
68 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2866 |
0 |
0 |
T93 |
71008 |
203 |
0 |
0 |
T110 |
10176 |
11 |
0 |
0 |
T115 |
74631 |
504 |
0 |
0 |
T120 |
234707 |
463 |
0 |
0 |
T141 |
4536 |
3 |
0 |
0 |
T149 |
34593 |
153 |
0 |
0 |
T150 |
19536 |
51 |
0 |
0 |
T153 |
14352 |
69 |
0 |
0 |
T154 |
19947 |
42 |
0 |
0 |
T155 |
97747 |
355 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
4090 |
0 |
0 |
T8 |
103372 |
104 |
0 |
0 |
T9 |
269614 |
0 |
0 |
0 |
T10 |
300554 |
0 |
0 |
0 |
T11 |
2711 |
0 |
0 |
0 |
T12 |
147562 |
0 |
0 |
0 |
T13 |
71745 |
0 |
0 |
0 |
T14 |
615491 |
0 |
0 |
0 |
T17 |
0 |
21 |
0 |
0 |
T19 |
0 |
17 |
0 |
0 |
T23 |
0 |
23 |
0 |
0 |
T24 |
122806 |
0 |
0 |
0 |
T25 |
282473 |
0 |
0 |
0 |
T26 |
902 |
0 |
0 |
0 |
T35 |
0 |
36 |
0 |
0 |
T136 |
0 |
24 |
0 |
0 |
T156 |
0 |
56 |
0 |
0 |
T157 |
0 |
42 |
0 |
0 |
T158 |
0 |
34 |
0 |
0 |
T159 |
0 |
24 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2387 |
0 |
0 |
T81 |
1772 |
6 |
0 |
0 |
T93 |
71008 |
87 |
0 |
0 |
T110 |
10176 |
10 |
0 |
0 |
T115 |
74631 |
505 |
0 |
0 |
T141 |
4536 |
4 |
0 |
0 |
T149 |
34593 |
40 |
0 |
0 |
T150 |
19536 |
52 |
0 |
0 |
T151 |
5445 |
10 |
0 |
0 |
T152 |
4278 |
3 |
0 |
0 |
T153 |
14352 |
71 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2186 |
0 |
0 |
T81 |
1772 |
8 |
0 |
0 |
T93 |
71008 |
97 |
0 |
0 |
T110 |
10176 |
18 |
0 |
0 |
T115 |
74631 |
488 |
0 |
0 |
T120 |
234707 |
354 |
0 |
0 |
T149 |
34593 |
68 |
0 |
0 |
T150 |
19536 |
84 |
0 |
0 |
T151 |
5445 |
12 |
0 |
0 |
T153 |
14352 |
14 |
0 |
0 |
T154 |
19947 |
81 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2190 |
0 |
0 |
T81 |
1772 |
1 |
0 |
0 |
T93 |
71008 |
55 |
0 |
0 |
T110 |
10176 |
17 |
0 |
0 |
T115 |
74631 |
475 |
0 |
0 |
T141 |
4536 |
4 |
0 |
0 |
T149 |
34593 |
33 |
0 |
0 |
T150 |
19536 |
90 |
0 |
0 |
T151 |
5445 |
1 |
0 |
0 |
T152 |
4278 |
7 |
0 |
0 |
T153 |
14352 |
42 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2116 |
0 |
0 |
T93 |
71008 |
82 |
0 |
0 |
T100 |
22491 |
4 |
0 |
0 |
T110 |
10176 |
15 |
0 |
0 |
T115 |
74631 |
544 |
0 |
0 |
T120 |
234707 |
310 |
0 |
0 |
T141 |
4536 |
2 |
0 |
0 |
T149 |
34593 |
46 |
0 |
0 |
T150 |
19536 |
115 |
0 |
0 |
T153 |
14352 |
17 |
0 |
0 |
T154 |
19947 |
62 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2265 |
0 |
0 |
T93 |
71008 |
107 |
0 |
0 |
T110 |
10176 |
9 |
0 |
0 |
T115 |
74631 |
495 |
0 |
0 |
T120 |
234707 |
457 |
0 |
0 |
T141 |
4536 |
1 |
0 |
0 |
T149 |
34593 |
46 |
0 |
0 |
T150 |
19536 |
61 |
0 |
0 |
T151 |
5445 |
6 |
0 |
0 |
T152 |
4278 |
4 |
0 |
0 |
T153 |
14352 |
38 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2122 |
0 |
0 |
T93 |
71008 |
73 |
0 |
0 |
T110 |
10176 |
10 |
0 |
0 |
T115 |
74631 |
543 |
0 |
0 |
T120 |
234707 |
409 |
0 |
0 |
T123 |
9361 |
11 |
0 |
0 |
T149 |
34593 |
35 |
0 |
0 |
T150 |
19536 |
24 |
0 |
0 |
T153 |
14352 |
64 |
0 |
0 |
T154 |
19947 |
60 |
0 |
0 |
T155 |
97747 |
122 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2768 |
0 |
0 |
T93 |
71008 |
222 |
0 |
0 |
T110 |
10176 |
38 |
0 |
0 |
T115 |
74631 |
544 |
0 |
0 |
T120 |
234707 |
446 |
0 |
0 |
T141 |
4536 |
2 |
0 |
0 |
T149 |
34593 |
93 |
0 |
0 |
T150 |
19536 |
35 |
0 |
0 |
T151 |
5445 |
2 |
0 |
0 |
T152 |
4278 |
5 |
0 |
0 |
T153 |
14352 |
28 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2101 |
0 |
0 |
T92 |
12329 |
7 |
0 |
0 |
T93 |
71008 |
53 |
0 |
0 |
T110 |
10176 |
19 |
0 |
0 |
T115 |
74631 |
462 |
0 |
0 |
T141 |
4536 |
6 |
0 |
0 |
T149 |
34593 |
35 |
0 |
0 |
T150 |
19536 |
62 |
0 |
0 |
T151 |
5445 |
1 |
0 |
0 |
T152 |
4278 |
3 |
0 |
0 |
T153 |
14352 |
28 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2814 |
0 |
0 |
T93 |
71008 |
267 |
0 |
0 |
T110 |
10176 |
41 |
0 |
0 |
T115 |
74631 |
484 |
0 |
0 |
T120 |
234707 |
370 |
0 |
0 |
T149 |
34593 |
103 |
0 |
0 |
T150 |
19536 |
75 |
0 |
0 |
T151 |
5445 |
19 |
0 |
0 |
T153 |
14352 |
10 |
0 |
0 |
T154 |
19947 |
56 |
0 |
0 |
T155 |
97747 |
326 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2345 |
0 |
0 |
T93 |
71008 |
127 |
0 |
0 |
T110 |
10176 |
14 |
0 |
0 |
T115 |
74631 |
448 |
0 |
0 |
T120 |
234707 |
412 |
0 |
0 |
T149 |
34593 |
58 |
0 |
0 |
T150 |
19536 |
85 |
0 |
0 |
T151 |
5445 |
2 |
0 |
0 |
T152 |
4278 |
6 |
0 |
0 |
T153 |
14352 |
50 |
0 |
0 |
T154 |
19947 |
41 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2328 |
0 |
0 |
T93 |
71008 |
67 |
0 |
0 |
T100 |
22491 |
1 |
0 |
0 |
T110 |
10176 |
11 |
0 |
0 |
T115 |
74631 |
528 |
0 |
0 |
T120 |
234707 |
418 |
0 |
0 |
T141 |
4536 |
5 |
0 |
0 |
T149 |
34593 |
47 |
0 |
0 |
T150 |
19536 |
72 |
0 |
0 |
T153 |
14352 |
54 |
0 |
0 |
T154 |
19947 |
134 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2273 |
0 |
0 |
T81 |
1772 |
5 |
0 |
0 |
T93 |
71008 |
77 |
0 |
0 |
T110 |
10176 |
13 |
0 |
0 |
T115 |
74631 |
455 |
0 |
0 |
T120 |
234707 |
442 |
0 |
0 |
T141 |
4536 |
3 |
0 |
0 |
T149 |
34593 |
54 |
0 |
0 |
T150 |
19536 |
60 |
0 |
0 |
T151 |
5445 |
5 |
0 |
0 |
T153 |
14352 |
63 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2270 |
0 |
0 |
T81 |
1772 |
9 |
0 |
0 |
T93 |
71008 |
68 |
0 |
0 |
T110 |
10176 |
12 |
0 |
0 |
T115 |
74631 |
492 |
0 |
0 |
T120 |
234707 |
420 |
0 |
0 |
T141 |
4536 |
1 |
0 |
0 |
T149 |
34593 |
53 |
0 |
0 |
T150 |
19536 |
81 |
0 |
0 |
T151 |
5445 |
2 |
0 |
0 |
T153 |
14352 |
26 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2103 |
0 |
0 |
T81 |
1772 |
2 |
0 |
0 |
T93 |
71008 |
66 |
0 |
0 |
T110 |
10176 |
22 |
0 |
0 |
T115 |
74631 |
488 |
0 |
0 |
T120 |
234707 |
421 |
0 |
0 |
T149 |
34593 |
32 |
0 |
0 |
T150 |
19536 |
74 |
0 |
0 |
T151 |
5445 |
9 |
0 |
0 |
T153 |
14352 |
7 |
0 |
0 |
T154 |
19947 |
56 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2157 |
0 |
0 |
T93 |
71008 |
75 |
0 |
0 |
T110 |
10176 |
14 |
0 |
0 |
T115 |
74631 |
474 |
0 |
0 |
T120 |
234707 |
414 |
0 |
0 |
T149 |
34593 |
38 |
0 |
0 |
T150 |
19536 |
79 |
0 |
0 |
T151 |
5445 |
3 |
0 |
0 |
T152 |
4278 |
1 |
0 |
0 |
T153 |
14352 |
11 |
0 |
0 |
T154 |
19947 |
33 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
431718072 |
2169 |
0 |
0 |
T81 |
1772 |
2 |
0 |
0 |
T93 |
71008 |
54 |
0 |
0 |
T110 |
10176 |
22 |
0 |
0 |
T115 |
74631 |
517 |
0 |
0 |
T120 |
234707 |
414 |
0 |
0 |
T141 |
4536 |
3 |
0 |
0 |
T149 |
34593 |
30 |
0 |
0 |
T150 |
19536 |
73 |
0 |
0 |
T151 |
5445 |
3 |
0 |
0 |
T153 |
14352 |
11 |
0 |
0 |