Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3426676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4098977

1

T1

961

T2

1707

T3

892

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4121004	1			T1	176		T2	1661		T3	6
values[0x0]	1700968	1			T1	448		T2	434		T3	436
values[0x1]	1703681	1			T1	440		T2	479		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2428498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5097155

1

T1

983

T2

1890

T3

893

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27659	1			T1	4		T2	18		T6	3
valid_sources[0x01]	29730	1			T1	2		T2	4		T5	6
valid_sources[0x02]	26109	1			T1	6		T2	10		T5	27
valid_sources[0x03]	28313	1			T1	1		T2	11		T6	1
valid_sources[0x04]	29039	1			T2	8		T6	1		T11	51
valid_sources[0x05]	25945	1			T1	8		T2	22		T11	37
valid_sources[0x06]	31684	1			T1	6		T2	14		T11	58
valid_sources[0x07]	28611	1			T1	7		T2	6		T6	1
valid_sources[0x08]	34029	1			T2	4		T5	4		T11	37
valid_sources[0x09]	25792	1			T2	20		T11	26		T13	5
valid_sources[0x0a]	27032	1			T1	1		T2	7		T5	17
valid_sources[0x0b]	29449	1			T1	6		T2	6		T6	2
valid_sources[0x0c]	27950	1			T1	5		T2	8		T5	6
valid_sources[0x0d]	30591	1			T1	7		T2	9		T6	1
valid_sources[0x0e]	28157	1			T1	3		T2	7		T5	8
valid_sources[0x0f]	29572	1			T1	4		T2	12		T6	1
valid_sources[0x10]	36647	1			T1	3		T2	7		T11	33
valid_sources[0x11]	26435	1			T1	2		T2	10		T5	7
valid_sources[0x12]	31822	1			T1	1		T2	7		T6	2
valid_sources[0x13]	35893	1			T1	1		T2	6		T11	30
valid_sources[0x14]	27705	1			T2	8		T11	41		T13	1
valid_sources[0x15]	28816	1			T1	3		T2	3		T6	2
valid_sources[0x16]	32068	1			T1	6		T2	15		T6	2
valid_sources[0x17]	29922	1			T2	3		T5	3		T11	61
valid_sources[0x18]	28177	1			T2	6		T5	1		T11	56
valid_sources[0x19]	30749	1			T2	4		T5	3		T6	2
valid_sources[0x1a]	29600	1			T1	14		T2	15		T5	7
valid_sources[0x1b]	26994	1			T1	2		T2	12		T5	11
valid_sources[0x1c]	26304	1			T1	1		T2	5		T5	8
valid_sources[0x1d]	29289	1			T1	2		T2	10		T6	2
valid_sources[0x1e]	29407	1			T1	1		T2	10		T5	4
valid_sources[0x1f]	33622	1			T1	2		T2	1		T5	48
valid_sources[0x20]	27332	1			T1	4		T2	7		T5	39
valid_sources[0x21]	25379	1			T1	7		T2	12		T6	1
valid_sources[0x22]	30173	1			T1	4		T2	8		T11	30
valid_sources[0x23]	30597	1			T1	3		T2	12		T5	12
valid_sources[0x24]	26575	1			T1	15		T2	11		T11	61
valid_sources[0x25]	27645	1			T1	1		T2	20		T11	52
valid_sources[0x26]	26183	1			T1	7		T2	8		T6	1
valid_sources[0x27]	40176	1			T1	4		T2	13		T5	5
valid_sources[0x28]	30513	1			T1	8		T2	15		T6	1
valid_sources[0x29]	26975	1			T1	4		T2	16		T5	24
valid_sources[0x2a]	31972	1			T1	3		T2	3		T11	45
valid_sources[0x2b]	27821	1			T1	2		T2	12		T11	43
valid_sources[0x2c]	28317	1			T1	9		T2	5		T6	4
valid_sources[0x2d]	28718	1			T1	4		T2	4		T5	10
valid_sources[0x2e]	28390	1			T1	5		T2	15		T5	21
valid_sources[0x2f]	32480	1			T1	4		T2	7		T5	1
valid_sources[0x30]	25797	1			T1	3		T2	5		T11	44
valid_sources[0x31]	28406	1			T1	2		T2	11		T5	4
valid_sources[0x32]	27350	1			T1	1		T2	14		T5	2
valid_sources[0x33]	28695	1			T1	2		T2	2		T5	26
valid_sources[0x34]	28711	1			T1	3		T2	10		T5	10
valid_sources[0x35]	28090	1			T1	3		T2	12		T6	1
valid_sources[0x36]	26205	1			T1	1		T2	5		T11	45
valid_sources[0x37]	28152	1			T1	3		T2	5		T6	1
valid_sources[0x38]	28170	1			T1	5		T2	5		T5	1
valid_sources[0x39]	28956	1			T1	8		T2	8		T5	7
valid_sources[0x3a]	28401	1			T1	2		T2	6		T11	42
valid_sources[0x3b]	27371	1			T1	6		T2	14		T5	1
valid_sources[0x3c]	30176	1			T1	4		T2	17		T11	40
valid_sources[0x3d]	30267	1			T1	5		T2	5		T11	75
valid_sources[0x3e]	26934	1			T1	7		T2	11		T5	4
valid_sources[0x3f]	29043	1			T1	6		T2	5		T5	3
valid_sources[0x40]	26901	1			T1	7		T2	12		T5	6
valid_sources[0x41]	27395	1			T1	1		T2	17		T11	45
valid_sources[0x42]	25565	1			T1	4		T2	18		T6	1
valid_sources[0x43]	28810	1			T2	7		T5	7		T6	1
valid_sources[0x44]	27751	1			T1	5		T2	9		T4	1
valid_sources[0x45]	27504	1			T1	10		T2	6		T6	1
valid_sources[0x46]	26803	1			T1	9		T2	5		T5	1
valid_sources[0x47]	27984	1			T1	11		T2	5		T6	1
valid_sources[0x48]	26846	1			T1	4		T2	12		T5	1
valid_sources[0x49]	28323	1			T1	12		T2	14		T6	3
valid_sources[0x4a]	30202	1			T1	3		T2	10		T5	11
valid_sources[0x4b]	28545	1			T1	1		T2	11		T5	1
valid_sources[0x4c]	28265	1			T1	12		T2	8		T5	5
valid_sources[0x4d]	28080	1			T1	13		T2	6		T5	8
valid_sources[0x4e]	27475	1			T1	4		T2	15		T11	43
valid_sources[0x4f]	26409	1			T1	1		T2	11		T5	17
valid_sources[0x50]	28168	1			T1	3		T2	12		T5	4
valid_sources[0x51]	25745	1			T1	6		T2	15		T11	42
valid_sources[0x52]	27475	1			T1	4		T2	1		T11	51
valid_sources[0x53]	27148	1			T1	9		T2	7		T11	57
valid_sources[0x54]	28644	1			T1	9		T2	6		T5	4
valid_sources[0x55]	48910	1			T1	1		T2	10		T11	40
valid_sources[0x56]	29502	1			T1	4		T2	16		T5	7
valid_sources[0x57]	26530	1			T1	3		T2	14		T11	46
valid_sources[0x58]	31783	1			T1	14		T2	10		T5	6
valid_sources[0x59]	29422	1			T2	9		T5	2		T11	32
valid_sources[0x5a]	28382	1			T1	9		T2	13		T4	467
valid_sources[0x5b]	26192	1			T1	3		T2	16		T5	8
valid_sources[0x5c]	29811	1			T1	15		T2	8		T5	4
valid_sources[0x5d]	28279	1			T1	4		T2	10		T5	11
valid_sources[0x5e]	28705	1			T1	4		T2	16		T6	2
valid_sources[0x5f]	34588	1			T1	5		T2	7		T5	1
valid_sources[0x60]	26400	1			T1	2		T2	4		T5	22
valid_sources[0x61]	30866	1			T1	3		T2	9		T5	10
valid_sources[0x62]	28369	1			T1	5		T2	8		T5	5
valid_sources[0x63]	31957	1			T1	4		T2	13		T11	43
valid_sources[0x64]	30926	1			T1	1		T2	10		T11	64
valid_sources[0x65]	27468	1			T1	6		T2	13		T11	48
valid_sources[0x66]	28782	1			T2	3		T11	42		T13	6
valid_sources[0x67]	26421	1			T1	4		T2	11		T11	60
valid_sources[0x68]	34115	1			T1	4		T2	6		T5	4
valid_sources[0x69]	29654	1			T1	6		T2	10		T11	50
valid_sources[0x6a]	24846	1			T1	9		T2	2		T6	1
valid_sources[0x6b]	28408	1			T1	6		T2	14		T6	2
valid_sources[0x6c]	35435	1			T1	1		T2	13		T5	29
valid_sources[0x6d]	29340	1			T1	1		T2	10		T6	1
valid_sources[0x6e]	28474	1			T1	1		T2	8		T11	35
valid_sources[0x6f]	27437	1			T1	7		T2	11		T5	3
valid_sources[0x70]	25392	1			T1	4		T2	13		T11	50
valid_sources[0x71]	27792	1			T1	2		T2	13		T11	55
valid_sources[0x72]	29478	1			T1	3		T2	11		T11	40
valid_sources[0x73]	27394	1			T1	2		T2	4		T5	1
valid_sources[0x74]	25933	1			T1	10		T2	4		T11	40
valid_sources[0x75]	25669	1			T1	5		T2	12		T5	17
valid_sources[0x76]	30186	1			T1	2		T2	12		T11	43
valid_sources[0x77]	27411	1			T1	1		T2	10		T5	16
valid_sources[0x78]	27805	1			T1	7		T2	17		T5	7
valid_sources[0x79]	30932	1			T2	6		T5	34		T11	50
valid_sources[0x7a]	50997	1			T1	2		T2	8		T5	43
valid_sources[0x7b]	27127	1			T1	12		T2	5		T5	1
valid_sources[0x7c]	27213	1			T1	9		T2	7		T5	5
valid_sources[0x7d]	37204	1			T1	5		T2	14		T5	6
valid_sources[0x7e]	27630	1			T1	10		T2	6		T6	1
valid_sources[0x7f]	27374	1			T1	3		T2	9		T3	896
valid_sources[0x80]	35922	1			T1	4		T2	1		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1003223

1

T1

86

T2

802

T3

3

values[0x0]

all_enables

biggest_size

1557740

1

T1

443

T2

432

T3

436

values[0x1]

all_enables

biggest_size

1538014

1

T1

432

T2

473

T3

453