Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3444606

1

T1

103

T2

867

T3

4

full_word

4097947

1

T1

961

T2

1707

T3

892

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7542193	1			T1	1064		T2	2574		T3	896
auto[TlIntgErrCmd]	132	1			T114	7		T117	11		T118	3
auto[TlIntgErrData]	105	1			T117	7		T118	4		T127	6
auto[TlIntgErrBoth]	123	1			T114	3		T117	12		T118	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4122530

1

T1

176

T2

1661

T3

6

auto[1]

3420023

1

T1

888

T2

913

T3

890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3119038	1			T1	90		T2	859		T3	3
auto[TlIntgErrNone]	partial	auto[1]	325234	1			T1	13		T2	8		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	1003328	1			T1	86		T2	802		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	3094593	1			T1	875		T2	905		T3	889
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T114	2		T117	5		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T114	5		T117	6		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T118	1		T127	1		T191	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T192	3		T193	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1			T117	4		T118	3		T127	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T117	3		T118	1		T127	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T127	1		T191	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T194	1		T193	1		T190	2
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T117	5		T118	1		T127	4
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T114	3		T117	6		T118	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T188	1		T191	1		T192	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T117	1		T195	1		T191	1