Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T15
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T15,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T15
1	0	Covered	T1,T15,T39
1	1	Covered	T1,T13,T15

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1334383095	2767	0	0
SrcPulseCheck_M	423344397	2767	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1334383095	2767	0	0
T1	33880	7	0	0
T2	64980	0	0	0
T3	323626	0	0	0
T4	8280	0	0	0
T5	46654	0	0	0
T6	4608	0	0	0
T7	22224	0	0	0
T8	1666	0	0	0
T9	7810	0	0	0
T10	2712	0	0	0
T13	50071	1	0	0
T14	100324	0	0	0
T15	60342	3	0	0
T16	163871	0	0	0
T17	8325	0	0	0
T25	258918	0	0	0
T26	1600	0	0	0
T27	427288	0	0	0
T28	22463	2	0	0
T31	0	13	0	0
T36	0	4	0	0
T39	0	7	0	0
T40	0	1	0	0
T43	0	9	0	0
T50	0	2	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	5	0	0
T55	0	6	0	0
T80	0	5	0	0
T82	0	7	0	0
T83	1147	0	0	0
T120	0	3	0	0
T136	0	2	0	0
T165	0	7	0	0
T166	0	9	0	0
T167	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423344397	2767	0	0
T1	48102	7	0	0
T2	92118	0	0	0
T3	79500	0	0	0
T4	32	0	0	0
T5	20544	0	0	0
T6	2640	0	0	0
T7	2048	0	0	0
T11	68216	0	0	0
T13	69204	1	0	0
T14	429096	0	0	0
T15	165238	3	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	2	0	0
T31	0	13	0	0
T36	0	4	0	0
T39	9496	7	0	0
T40	9781	1	0	0
T43	0	9	0	0
T50	0	2	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	5	0	0
T55	0	6	0	0
T80	0	5	0	0
T82	0	7	0	0
T120	0	3	0	0
T136	0	2	0	0
T165	0	7	0	0
T166	0	9	0	0
T167	0	3	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T28,T39
1	0	Covered	T1,T28,T39
1	1	Covered	T1,T39,T43

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T28,T39
1	0	Covered	T1,T39,T43
1	1	Covered	T1,T28,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	444794365	196	0	0
SrcPulseCheck_M	141114799	196	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	196	0	0
T1	16940	2	0	0
T2	32490	0	0	0
T3	161813	0	0	0
T4	4140	0	0	0
T5	23327	0	0	0
T6	2304	0	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	5	0	0
T82	0	2	0	0
T136	0	1	0	0
T165	0	2	0	0
T166	0	5	0	0
T167	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	196	0	0
T1	24051	2	0	0
T2	46059	0	0	0
T3	39750	0	0	0
T4	16	0	0	0
T5	10272	0	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	5	0	0
T82	0	2	0	0
T136	0	1	0	0
T165	0	2	0	0
T166	0	5	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T28,T39
1	0	Covered	T1,T28,T39
1	1	Covered	T1,T39,T43

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T28,T39
1	0	Covered	T1,T39,T43
1	1	Covered	T1,T28,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	444794365	335	0	0
SrcPulseCheck_M	141114799	335	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	335	0	0
T1	16940	5	0	0
T2	32490	0	0	0
T3	161813	0	0	0
T4	4140	0	0	0
T5	23327	0	0	0
T6	2304	0	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T28	0	1	0	0
T39	0	5	0	0
T43	0	4	0	0
T82	0	5	0	0
T120	0	3	0	0
T136	0	1	0	0
T165	0	5	0	0
T166	0	4	0	0
T167	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	335	0	0
T1	24051	5	0	0
T2	46059	0	0	0
T3	39750	0	0	0
T4	16	0	0	0
T5	10272	0	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T28	0	1	0	0
T39	0	5	0	0
T43	0	4	0	0
T82	0	5	0	0
T120	0	3	0	0
T136	0	1	0	0
T165	0	5	0	0
T166	0	4	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T55
1	0	Covered	T13,T15,T55
1	1	Covered	T15,T55,T50

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T55
1	0	Covered	T15,T55,T50
1	1	Covered	T13,T15,T55

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	444794365	2236	0	0
SrcPulseCheck_M	141114799	2236	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2236	0	0
T13	50071	1	0	0
T14	100324	0	0	0
T15	60342	3	0	0
T16	163871	0	0	0
T17	8325	0	0	0
T25	258918	0	0	0
T26	1600	0	0	0
T27	427288	0	0	0
T28	22463	0	0	0
T31	0	13	0	0
T36	0	4	0	0
T50	0	2	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	5	0	0
T55	0	6	0	0
T80	0	5	0	0
T83	1147	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	2236	0	0
T13	23068	1	0	0
T14	143032	0	0	0
T15	165238	3	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	13	0	0
T36	0	4	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	2	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	5	0	0
T55	0	6	0	0
T80	0	5	0	0