Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	2821446	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	2821446	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	1663	0	0
T5	23327	1663	0	0
T6	2304	0	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	1663	0	0
T15	0	3327	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	3187230	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	3187230	0	0
T1	16940	3819	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	0	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	2496	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	175493	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	175493	0	0
T6	2304	11	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	139294	0	0	0
T12	2175	0	0	0
T13	50071	32	0	0
T14	100324	0	0	0
T15	60342	0	0	0
T25	0	602	0	0
T26	0	3	0	0
T31	0	1083	0	0
T33	0	1	0	0
T34	0	16	0	0
T50	0	128	0	0
T51	0	193	0	0
T52	0	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	423294	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	423294	0	0
T6	2304	11	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	139294	0	0	0
T12	2175	0	0	0
T13	50071	32	0	0
T14	100324	0	0	0
T15	60342	0	0	0
T25	0	602	0	0
T26	0	9	0	0
T31	0	1080	0	0
T33	0	1	0	0
T34	0	64	0	0
T50	0	128	0	0
T51	0	893	0	0
T52	0	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	5917081	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	5917081	0	0
T1	16940	232	0	0
T2	32490	1743	0	0
T3	161813	64	0	0
T4	4140	54	0	0
T5	23327	745	0	0
T6	2304	143	0	0
T7	11112	20	0	0
T8	833	8	0	0
T9	3905	3	0	0
T10	1356	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	447094412	13786231	0	0
DepthKnown_A	447094412	446963702	0	0
RvalidKnown_A	447094412	446963702	0	0
WreadyKnown_A	447094412	446963702	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	13786231	0	0
T1	16940	990	0	0
T2	32490	1742	0	0
T3	161813	64	0	0
T4	4140	54	0	0
T5	23327	745	0	0
T6	2304	143	0	0
T7	11112	20	0	0
T8	833	13	0	0
T9	3905	3	0	0
T10	1356	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447094412	446963702	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0