Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T26
1	0	Covered	T6,T25,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T25
1	0	Unreachable
1	1	Covered	T6,T25,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T55

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T55
1	0	Covered	T13,T15,T55

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T13,T15,T55

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T13,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T13,T15
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	727023963	584561315	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	727023963	3542536	0	0
GntImpliesValid_A	727023963	3542536	0	0
GrantKnown_A	727023963	584561315	0	0
IdxKnown_A	727023963	584561315	0	0
IndexIsCorrect_A	727023963	3542536	0	0
LockArbDecision_A	727023963	0	0	0
NoReadyValidNoGrant_A	727023963	0	0	0
ReadyAndValidImplyGrant_A	727023963	3542536	0	0
ReqAndReadyImplyGrant_A	727023963	3542536	0	0
ReqImpliesValid_A	727023963	3542536	0	0
ReqStaysHighUntilGranted0_M	727023963	0	0	0
RoundRobin_A	727023963	4	0	976
ValidKnown_A	727023963	584561315	0	0
gen_data_port_assertion.DataFlow_A	727023963	3542536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	584561315	0	0
T1	40991	40595	0	0
T2	78549	77821	0	0
T3	201563	201486	0	0
T4	4156	4060	0	0
T5	33599	33542	0	0
T6	4944	3567	0	0
T7	13160	11465	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0
T11	68216	34108	0	0
T13	46136	22748	0	0
T14	286064	142824	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	584561315	0	0
T1	40991	40595	0	0
T2	78549	77821	0	0
T3	201563	201486	0	0
T4	4156	4060	0	0
T5	33599	33542	0	0
T6	4944	3567	0	0
T7	13160	11465	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0
T11	68216	34108	0	0
T13	46136	22748	0	0
T14	286064	142824	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	584561315	0	0
T1	40991	40595	0	0
T2	78549	77821	0	0
T3	201563	201486	0	0
T4	4156	4060	0	0
T5	33599	33542	0	0
T6	4944	3567	0	0
T7	13160	11465	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0
T11	68216	34108	0	0
T13	46136	22748	0	0
T14	286064	142824	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	4	0	976
T46	182307	1	0	1
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	25157	0	0	1
T72	6462	0	0	1
T73	3481	0	0	1
T74	946	0	0	1
T75	1337	0	0	1
T76	597083	0	0	1
T77	1395	0	0	1
T78	3097	0	0	1
T79	46518	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	584561315	0	0
T1	40991	40595	0	0
T2	78549	77821	0	0
T3	201563	201486	0	0
T4	4156	4060	0	0
T5	33599	33542	0	0
T6	4944	3567	0	0
T7	13160	11465	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0
T11	68216	34108	0	0
T13	46136	22748	0	0
T14	286064	142824	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	727023963	3542536	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	3624	89	0	0
T7	12136	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	34108	832	0	0
T13	46136	996	0	0
T14	286064	832	0	0
T15	330476	2506	0	0
T16	160924	0	0	0
T18	0	2672	0	0
T25	172258	3241	0	0
T26	1456	16	0	0
T27	140606	0	0	0
T28	52724	0	0	0
T31	0	5400	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	2133	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T55	0	12	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T26
1	0	Covered	T6,T25,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T25
1	0	Unreachable
1	1	Covered	T6,T25,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T25,T26
0	0	1	Unreachable
0	0	0	Covered	T6,T7,T25

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141114799	23599675	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	141114799	572483	0	0
GntImpliesValid_A	141114799	572483	0	0
GrantKnown_A	141114799	23599675	0	0
IdxKnown_A	141114799	23599675	0	0
IndexIsCorrect_A	141114799	572483	0	0
LockArbDecision_A	141114799	0	0	0
NoReadyValidNoGrant_A	141114799	0	0	0
ReadyAndValidImplyGrant_A	141114799	572483	0	0
ReqAndReadyImplyGrant_A	141114799	572483	0	0
ReqImpliesValid_A	141114799	572483	0	0
ReqStaysHighUntilGranted0_M	141114799	0	0	0
RoundRobin_A	141114799	0	0	0
ValidKnown_A	141114799	23599675	0	0
gen_data_port_assertion.DataFlow_A	141114799	572483	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	23599675	0	0
T6	1320	1320	0	0
T7	1024	432	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	23599675	0	0
T6	1320	1320	0	0
T7	1024	432	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	23599675	0	0
T6	1320	1320	0	0
T7	1024	432	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	23599675	0	0
T6	1320	1320	0	0
T7	1024	432	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T25	86129	82815	0	0
T26	728	728	0	0
T27	70303	0	0	0
T29	0	14328	0	0
T31	0	293760	0	0
T32	0	18024	0	0
T33	0	72	0	0
T34	0	552	0	0
T35	0	6320	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	572483	0	0
T6	1320	61	0	0
T7	1024	0	0	0
T11	34108	0	0	0
T13	23068	0	0	0
T14	143032	0	0	0
T15	165238	0	0	0
T16	80462	0	0	0
T18	0	2672	0	0
T25	86129	3241	0	0
T26	728	16	0	0
T27	70303	0	0	0
T31	0	3762	0	0
T32	0	314	0	0
T33	0	4	0	0
T34	0	64	0	0
T35	0	257	0	0
T36	0	1357	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T55

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T55
1	0	Covered	T13,T15,T55

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T13,T15,T55

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T15,T55
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T55
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T55
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141114799	116255496	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	141114799	775557	0	0
GntImpliesValid_A	141114799	775557	0	0
GrantKnown_A	141114799	116255496	0	0
IdxKnown_A	141114799	116255496	0	0
IndexIsCorrect_A	141114799	775557	0	0
LockArbDecision_A	141114799	0	0	0
NoReadyValidNoGrant_A	141114799	0	0	0
ReadyAndValidImplyGrant_A	141114799	775557	0	0
ReqAndReadyImplyGrant_A	141114799	775557	0	0
ReqImpliesValid_A	141114799	775557	0	0
ReqStaysHighUntilGranted0_M	141114799	0	0	0
RoundRobin_A	141114799	0	0	0
ValidKnown_A	141114799	116255496	0	0
gen_data_port_assertion.DataFlow_A	141114799	775557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	116255496	0	0
T1	24051	23737	0	0
T2	46059	45408	0	0
T3	39750	39750	0	0
T4	16	16	0	0
T5	10272	10272	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	34108	0	0
T13	23068	22748	0	0
T14	143032	142824	0	0
T15	0	163501	0	0
T16	0	80462	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	116255496	0	0
T1	24051	23737	0	0
T2	46059	45408	0	0
T3	39750	39750	0	0
T4	16	16	0	0
T5	10272	10272	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	34108	0	0
T13	23068	22748	0	0
T14	143032	142824	0	0
T15	0	163501	0	0
T16	0	80462	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	116255496	0	0
T1	24051	23737	0	0
T2	46059	45408	0	0
T3	39750	39750	0	0
T4	16	16	0	0
T5	10272	10272	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	34108	0	0
T13	23068	22748	0	0
T14	143032	142824	0	0
T15	0	163501	0	0
T16	0	80462	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	116255496	0	0
T1	24051	23737	0	0
T2	46059	45408	0	0
T3	39750	39750	0	0
T4	16	16	0	0
T5	10272	10272	0	0
T6	1320	0	0	0
T7	1024	0	0	0
T11	34108	34108	0	0
T13	23068	22748	0	0
T14	143032	142824	0	0
T15	0	163501	0	0
T16	0	80462	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141114799	775557	0	0
T13	23068	130	0	0
T14	143032	0	0	0
T15	165238	5	0	0
T16	80462	0	0	0
T25	86129	0	0	0
T26	728	0	0	0
T27	70303	0	0	0
T28	52724	0	0	0
T31	0	1638	0	0
T36	0	776	0	0
T39	9496	0	0	0
T40	9781	0	0	0
T50	0	514	0	0
T51	0	1441	0	0
T52	0	648	0	0
T53	0	2961	0	0
T55	0	12	0	0
T80	0	1419	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T13,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T13,T15
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444794365	444706144	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	444794365	2194496	0	0
GntImpliesValid_A	444794365	2194496	0	0
GrantKnown_A	444794365	444706144	0	0
IdxKnown_A	444794365	444706144	0	0
IndexIsCorrect_A	444794365	2194496	0	0
LockArbDecision_A	444794365	0	0	0
NoReadyValidNoGrant_A	444794365	0	0	0
ReadyAndValidImplyGrant_A	444794365	2194496	0	0
ReqAndReadyImplyGrant_A	444794365	2194496	0	0
ReqImpliesValid_A	444794365	2194496	0	0
ReqStaysHighUntilGranted0_M	444794365	0	0	0
RoundRobin_A	444794365	4	0	976
ValidKnown_A	444794365	444706144	0	0
gen_data_port_assertion.DataFlow_A	444794365	2194496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	444706144	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	444706144	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	444706144	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	4	0	976
T46	182307	1	0	1
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	25157	0	0	1
T72	6462	0	0	1
T73	3481	0	0	1
T74	946	0	0	1
T75	1337	0	0	1
T76	597083	0	0	1
T77	1395	0	0	1
T78	3097	0	0	1
T79	46518	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	444706144	0	0
T1	16940	16858	0	0
T2	32490	32413	0	0
T3	161813	161736	0	0
T4	4140	4044	0	0
T5	23327	23270	0	0
T6	2304	2247	0	0
T7	11112	11033	0	0
T8	833	738	0	0
T9	3905	3836	0	0
T10	1356	1299	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444794365	2194496	0	0
T1	16940	832	0	0
T2	32490	832	0	0
T3	161813	832	0	0
T4	4140	832	0	0
T5	23327	832	0	0
T6	2304	28	0	0
T7	11112	0	0	0
T8	833	0	0	0
T9	3905	0	0	0
T10	1356	0	0	0
T11	0	832	0	0
T13	0	866	0	0
T14	0	832	0	0
T15	0	2501	0	0