Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3636 |
0 |
0 |
T113 |
3045 |
64 |
0 |
0 |
T114 |
9443 |
2 |
0 |
0 |
T115 |
13877 |
6 |
0 |
0 |
T116 |
3737 |
9 |
0 |
0 |
T117 |
28212 |
5 |
0 |
0 |
T119 |
3900 |
11 |
0 |
0 |
T121 |
16513 |
355 |
0 |
0 |
T124 |
3328 |
94 |
0 |
0 |
T131 |
5343 |
20 |
0 |
0 |
T135 |
15682 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2303 |
0 |
0 |
T115 |
13877 |
19 |
0 |
0 |
T132 |
10163 |
6 |
0 |
0 |
T134 |
14381 |
16 |
0 |
0 |
T135 |
15682 |
23 |
0 |
0 |
T141 |
102220 |
388 |
0 |
0 |
T164 |
13275 |
49 |
0 |
0 |
T168 |
13330 |
36 |
0 |
0 |
T169 |
7020 |
24 |
0 |
0 |
T170 |
6604 |
19 |
0 |
0 |
T171 |
5984 |
2 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2278 |
0 |
0 |
T115 |
13877 |
11 |
0 |
0 |
T132 |
10163 |
15 |
0 |
0 |
T134 |
14381 |
16 |
0 |
0 |
T135 |
15682 |
12 |
0 |
0 |
T141 |
102220 |
417 |
0 |
0 |
T164 |
13275 |
28 |
0 |
0 |
T168 |
13330 |
39 |
0 |
0 |
T169 |
7020 |
18 |
0 |
0 |
T170 |
6604 |
16 |
0 |
0 |
T172 |
7145 |
21 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2420 |
0 |
0 |
T115 |
13877 |
15 |
0 |
0 |
T132 |
10163 |
12 |
0 |
0 |
T134 |
14381 |
40 |
0 |
0 |
T135 |
15682 |
50 |
0 |
0 |
T141 |
102220 |
332 |
0 |
0 |
T164 |
13275 |
35 |
0 |
0 |
T168 |
13330 |
45 |
0 |
0 |
T169 |
7020 |
9 |
0 |
0 |
T170 |
6604 |
6 |
0 |
0 |
T172 |
7145 |
27 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
5092 |
0 |
0 |
T115 |
13877 |
102 |
0 |
0 |
T132 |
10163 |
133 |
0 |
0 |
T134 |
14381 |
213 |
0 |
0 |
T135 |
15682 |
263 |
0 |
0 |
T141 |
102220 |
342 |
0 |
0 |
T164 |
13275 |
63 |
0 |
0 |
T168 |
13330 |
37 |
0 |
0 |
T169 |
7020 |
37 |
0 |
0 |
T170 |
6604 |
7 |
0 |
0 |
T172 |
7145 |
53 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
5572 |
0 |
0 |
T115 |
13877 |
15 |
0 |
0 |
T132 |
10163 |
239 |
0 |
0 |
T134 |
14381 |
288 |
0 |
0 |
T135 |
15682 |
265 |
0 |
0 |
T141 |
102220 |
375 |
0 |
0 |
T164 |
13275 |
30 |
0 |
0 |
T168 |
13330 |
42 |
0 |
0 |
T169 |
7020 |
9 |
0 |
0 |
T170 |
6604 |
42 |
0 |
0 |
T172 |
7145 |
35 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
4971 |
0 |
0 |
T115 |
13877 |
128 |
0 |
0 |
T132 |
10163 |
6 |
0 |
0 |
T134 |
14381 |
112 |
0 |
0 |
T135 |
15682 |
140 |
0 |
0 |
T141 |
102220 |
437 |
0 |
0 |
T164 |
13275 |
84 |
0 |
0 |
T168 |
13330 |
64 |
0 |
0 |
T169 |
7020 |
23 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
7 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
5256 |
0 |
0 |
T115 |
13877 |
87 |
0 |
0 |
T132 |
10163 |
267 |
0 |
0 |
T134 |
14381 |
107 |
0 |
0 |
T135 |
15682 |
121 |
0 |
0 |
T141 |
102220 |
350 |
0 |
0 |
T164 |
13275 |
61 |
0 |
0 |
T168 |
13330 |
59 |
0 |
0 |
T169 |
7020 |
32 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
33 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
5068 |
0 |
0 |
T115 |
13877 |
150 |
0 |
0 |
T132 |
10163 |
7 |
0 |
0 |
T134 |
14381 |
96 |
0 |
0 |
T135 |
15682 |
286 |
0 |
0 |
T141 |
102220 |
431 |
0 |
0 |
T164 |
13275 |
49 |
0 |
0 |
T168 |
13330 |
35 |
0 |
0 |
T169 |
7020 |
8 |
0 |
0 |
T170 |
6604 |
24 |
0 |
0 |
T172 |
7145 |
35 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
4947 |
0 |
0 |
T115 |
13877 |
91 |
0 |
0 |
T132 |
10163 |
116 |
0 |
0 |
T134 |
14381 |
162 |
0 |
0 |
T135 |
15682 |
268 |
0 |
0 |
T141 |
102220 |
327 |
0 |
0 |
T164 |
13275 |
89 |
0 |
0 |
T168 |
13330 |
70 |
0 |
0 |
T169 |
7020 |
14 |
0 |
0 |
T170 |
6604 |
28 |
0 |
0 |
T172 |
7145 |
23 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
5383 |
0 |
0 |
T115 |
13877 |
71 |
0 |
0 |
T132 |
10163 |
259 |
0 |
0 |
T134 |
14381 |
23 |
0 |
0 |
T135 |
15682 |
118 |
0 |
0 |
T141 |
102220 |
390 |
0 |
0 |
T164 |
13275 |
94 |
0 |
0 |
T168 |
13330 |
41 |
0 |
0 |
T169 |
7020 |
6 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
32 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
4534 |
0 |
0 |
T115 |
13877 |
129 |
0 |
0 |
T132 |
10163 |
228 |
0 |
0 |
T134 |
14381 |
132 |
0 |
0 |
T135 |
15682 |
371 |
0 |
0 |
T141 |
102220 |
370 |
0 |
0 |
T164 |
13275 |
33 |
0 |
0 |
T168 |
13330 |
46 |
0 |
0 |
T169 |
7020 |
2 |
0 |
0 |
T170 |
6604 |
14 |
0 |
0 |
T172 |
7145 |
39 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3301 |
0 |
0 |
T115 |
13877 |
59 |
0 |
0 |
T132 |
10163 |
113 |
0 |
0 |
T134 |
14381 |
42 |
0 |
0 |
T135 |
15682 |
80 |
0 |
0 |
T141 |
102220 |
412 |
0 |
0 |
T164 |
13275 |
50 |
0 |
0 |
T168 |
13330 |
36 |
0 |
0 |
T169 |
7020 |
24 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
43 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3201 |
0 |
0 |
T115 |
13877 |
62 |
0 |
0 |
T132 |
10163 |
19 |
0 |
0 |
T134 |
14381 |
97 |
0 |
0 |
T135 |
15682 |
100 |
0 |
0 |
T141 |
102220 |
416 |
0 |
0 |
T164 |
13275 |
38 |
0 |
0 |
T168 |
13330 |
48 |
0 |
0 |
T169 |
7020 |
10 |
0 |
0 |
T170 |
6604 |
23 |
0 |
0 |
T172 |
7145 |
36 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3109 |
0 |
0 |
T115 |
13877 |
48 |
0 |
0 |
T132 |
10163 |
59 |
0 |
0 |
T134 |
14381 |
83 |
0 |
0 |
T135 |
15682 |
150 |
0 |
0 |
T141 |
102220 |
333 |
0 |
0 |
T164 |
13275 |
27 |
0 |
0 |
T168 |
13330 |
48 |
0 |
0 |
T169 |
7020 |
23 |
0 |
0 |
T170 |
6604 |
32 |
0 |
0 |
T172 |
7145 |
34 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3266 |
0 |
0 |
T115 |
13877 |
101 |
0 |
0 |
T132 |
10163 |
66 |
0 |
0 |
T134 |
14381 |
15 |
0 |
0 |
T135 |
15682 |
59 |
0 |
0 |
T141 |
102220 |
370 |
0 |
0 |
T164 |
13275 |
52 |
0 |
0 |
T168 |
13330 |
6 |
0 |
0 |
T169 |
7020 |
5 |
0 |
0 |
T170 |
6604 |
18 |
0 |
0 |
T172 |
7145 |
25 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3242 |
0 |
0 |
T115 |
13877 |
78 |
0 |
0 |
T132 |
10163 |
86 |
0 |
0 |
T134 |
14381 |
33 |
0 |
0 |
T135 |
15682 |
126 |
0 |
0 |
T141 |
102220 |
434 |
0 |
0 |
T164 |
13275 |
44 |
0 |
0 |
T168 |
13330 |
45 |
0 |
0 |
T169 |
7020 |
14 |
0 |
0 |
T170 |
6604 |
15 |
0 |
0 |
T172 |
7145 |
36 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3145 |
0 |
0 |
T115 |
13877 |
37 |
0 |
0 |
T132 |
10163 |
12 |
0 |
0 |
T134 |
14381 |
73 |
0 |
0 |
T135 |
15682 |
77 |
0 |
0 |
T141 |
102220 |
356 |
0 |
0 |
T164 |
13275 |
40 |
0 |
0 |
T168 |
13330 |
30 |
0 |
0 |
T169 |
7020 |
22 |
0 |
0 |
T170 |
6604 |
20 |
0 |
0 |
T172 |
7145 |
9 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3434 |
0 |
0 |
T115 |
13877 |
35 |
0 |
0 |
T132 |
10163 |
14 |
0 |
0 |
T134 |
14381 |
103 |
0 |
0 |
T135 |
15682 |
121 |
0 |
0 |
T141 |
102220 |
426 |
0 |
0 |
T164 |
13275 |
27 |
0 |
0 |
T168 |
13330 |
38 |
0 |
0 |
T169 |
7020 |
34 |
0 |
0 |
T170 |
6604 |
11 |
0 |
0 |
T172 |
7145 |
13 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3550 |
0 |
0 |
T115 |
13877 |
93 |
0 |
0 |
T132 |
10163 |
14 |
0 |
0 |
T134 |
14381 |
149 |
0 |
0 |
T135 |
15682 |
108 |
0 |
0 |
T141 |
102220 |
408 |
0 |
0 |
T164 |
13275 |
81 |
0 |
0 |
T168 |
13330 |
33 |
0 |
0 |
T169 |
7020 |
5 |
0 |
0 |
T170 |
6604 |
24 |
0 |
0 |
T172 |
7145 |
16 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3247 |
0 |
0 |
T115 |
13877 |
39 |
0 |
0 |
T132 |
10163 |
54 |
0 |
0 |
T134 |
14381 |
83 |
0 |
0 |
T135 |
15682 |
94 |
0 |
0 |
T141 |
102220 |
422 |
0 |
0 |
T164 |
13275 |
22 |
0 |
0 |
T168 |
13330 |
54 |
0 |
0 |
T169 |
7020 |
57 |
0 |
0 |
T171 |
5984 |
29 |
0 |
0 |
T172 |
7145 |
4 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3365 |
0 |
0 |
T115 |
13877 |
36 |
0 |
0 |
T132 |
10163 |
62 |
0 |
0 |
T134 |
14381 |
87 |
0 |
0 |
T135 |
15682 |
66 |
0 |
0 |
T141 |
102220 |
362 |
0 |
0 |
T164 |
13275 |
58 |
0 |
0 |
T168 |
13330 |
87 |
0 |
0 |
T169 |
7020 |
16 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
27 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3024 |
0 |
0 |
T115 |
13877 |
17 |
0 |
0 |
T132 |
10163 |
48 |
0 |
0 |
T134 |
14381 |
121 |
0 |
0 |
T135 |
15682 |
138 |
0 |
0 |
T141 |
102220 |
412 |
0 |
0 |
T164 |
13275 |
43 |
0 |
0 |
T168 |
13330 |
43 |
0 |
0 |
T169 |
7020 |
10 |
0 |
0 |
T170 |
6604 |
40 |
0 |
0 |
T172 |
7145 |
2 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3522 |
0 |
0 |
T115 |
13877 |
106 |
0 |
0 |
T132 |
10163 |
95 |
0 |
0 |
T134 |
14381 |
90 |
0 |
0 |
T135 |
15682 |
136 |
0 |
0 |
T141 |
102220 |
440 |
0 |
0 |
T164 |
13275 |
16 |
0 |
0 |
T168 |
13330 |
40 |
0 |
0 |
T169 |
7020 |
8 |
0 |
0 |
T170 |
6604 |
6 |
0 |
0 |
T172 |
7145 |
37 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2945 |
0 |
0 |
T115 |
13877 |
47 |
0 |
0 |
T132 |
10163 |
40 |
0 |
0 |
T134 |
14381 |
54 |
0 |
0 |
T135 |
15682 |
132 |
0 |
0 |
T141 |
102220 |
377 |
0 |
0 |
T164 |
13275 |
15 |
0 |
0 |
T168 |
13330 |
61 |
0 |
0 |
T169 |
7020 |
30 |
0 |
0 |
T170 |
6604 |
23 |
0 |
0 |
T172 |
7145 |
10 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3335 |
0 |
0 |
T115 |
13877 |
58 |
0 |
0 |
T132 |
10163 |
91 |
0 |
0 |
T134 |
14381 |
78 |
0 |
0 |
T135 |
15682 |
74 |
0 |
0 |
T141 |
102220 |
446 |
0 |
0 |
T164 |
13275 |
52 |
0 |
0 |
T168 |
13330 |
47 |
0 |
0 |
T169 |
7020 |
15 |
0 |
0 |
T170 |
6604 |
22 |
0 |
0 |
T172 |
7145 |
17 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3313 |
0 |
0 |
T115 |
13877 |
59 |
0 |
0 |
T132 |
10163 |
6 |
0 |
0 |
T134 |
14381 |
76 |
0 |
0 |
T135 |
15682 |
65 |
0 |
0 |
T141 |
102220 |
365 |
0 |
0 |
T164 |
13275 |
68 |
0 |
0 |
T168 |
13330 |
30 |
0 |
0 |
T169 |
7020 |
10 |
0 |
0 |
T170 |
6604 |
11 |
0 |
0 |
T172 |
7145 |
29 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3255 |
0 |
0 |
T115 |
13877 |
66 |
0 |
0 |
T132 |
10163 |
16 |
0 |
0 |
T134 |
14381 |
118 |
0 |
0 |
T135 |
15682 |
22 |
0 |
0 |
T141 |
102220 |
386 |
0 |
0 |
T164 |
13275 |
59 |
0 |
0 |
T168 |
13330 |
40 |
0 |
0 |
T169 |
7020 |
34 |
0 |
0 |
T170 |
6604 |
20 |
0 |
0 |
T172 |
7145 |
8 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3296 |
0 |
0 |
T115 |
13877 |
13 |
0 |
0 |
T132 |
10163 |
70 |
0 |
0 |
T134 |
14381 |
88 |
0 |
0 |
T135 |
15682 |
48 |
0 |
0 |
T141 |
102220 |
384 |
0 |
0 |
T164 |
13275 |
73 |
0 |
0 |
T168 |
13330 |
65 |
0 |
0 |
T169 |
7020 |
4 |
0 |
0 |
T170 |
6604 |
46 |
0 |
0 |
T172 |
7145 |
35 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3287 |
0 |
0 |
T115 |
13877 |
93 |
0 |
0 |
T132 |
10163 |
46 |
0 |
0 |
T134 |
14381 |
133 |
0 |
0 |
T135 |
15682 |
161 |
0 |
0 |
T141 |
102220 |
383 |
0 |
0 |
T164 |
13275 |
48 |
0 |
0 |
T168 |
13330 |
19 |
0 |
0 |
T169 |
7020 |
8 |
0 |
0 |
T170 |
6604 |
21 |
0 |
0 |
T172 |
7145 |
56 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3239 |
0 |
0 |
T115 |
13877 |
32 |
0 |
0 |
T132 |
10163 |
56 |
0 |
0 |
T134 |
14381 |
103 |
0 |
0 |
T135 |
15682 |
123 |
0 |
0 |
T141 |
102220 |
381 |
0 |
0 |
T164 |
13275 |
59 |
0 |
0 |
T168 |
13330 |
53 |
0 |
0 |
T169 |
7020 |
15 |
0 |
0 |
T170 |
6604 |
19 |
0 |
0 |
T172 |
7145 |
39 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3402 |
0 |
0 |
T115 |
13877 |
45 |
0 |
0 |
T132 |
10163 |
63 |
0 |
0 |
T134 |
14381 |
69 |
0 |
0 |
T135 |
15682 |
168 |
0 |
0 |
T141 |
102220 |
420 |
0 |
0 |
T164 |
13275 |
22 |
0 |
0 |
T168 |
13330 |
32 |
0 |
0 |
T169 |
7020 |
19 |
0 |
0 |
T170 |
6604 |
17 |
0 |
0 |
T172 |
7145 |
28 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3141 |
0 |
0 |
T115 |
13877 |
82 |
0 |
0 |
T132 |
10163 |
12 |
0 |
0 |
T134 |
14381 |
136 |
0 |
0 |
T135 |
15682 |
88 |
0 |
0 |
T141 |
102220 |
350 |
0 |
0 |
T164 |
13275 |
24 |
0 |
0 |
T168 |
13330 |
42 |
0 |
0 |
T169 |
7020 |
26 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T171 |
5984 |
3 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3334 |
0 |
0 |
T115 |
13877 |
77 |
0 |
0 |
T132 |
10163 |
81 |
0 |
0 |
T134 |
14381 |
110 |
0 |
0 |
T135 |
15682 |
87 |
0 |
0 |
T141 |
102220 |
373 |
0 |
0 |
T164 |
13275 |
23 |
0 |
0 |
T168 |
13330 |
36 |
0 |
0 |
T169 |
7020 |
8 |
0 |
0 |
T172 |
7145 |
9 |
0 |
0 |
T173 |
16105 |
2 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3307 |
0 |
0 |
T115 |
13877 |
31 |
0 |
0 |
T132 |
10163 |
63 |
0 |
0 |
T134 |
14381 |
99 |
0 |
0 |
T135 |
15682 |
179 |
0 |
0 |
T141 |
102220 |
377 |
0 |
0 |
T164 |
13275 |
48 |
0 |
0 |
T168 |
13330 |
2 |
0 |
0 |
T169 |
7020 |
31 |
0 |
0 |
T170 |
6604 |
20 |
0 |
0 |
T172 |
7145 |
37 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3029 |
0 |
0 |
T115 |
13877 |
9 |
0 |
0 |
T132 |
10163 |
46 |
0 |
0 |
T134 |
14381 |
79 |
0 |
0 |
T135 |
15682 |
79 |
0 |
0 |
T141 |
102220 |
374 |
0 |
0 |
T164 |
13275 |
45 |
0 |
0 |
T168 |
13330 |
37 |
0 |
0 |
T169 |
7020 |
32 |
0 |
0 |
T170 |
6604 |
38 |
0 |
0 |
T172 |
7145 |
6 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2493 |
0 |
0 |
T115 |
13877 |
14 |
0 |
0 |
T132 |
10163 |
19 |
0 |
0 |
T134 |
14381 |
32 |
0 |
0 |
T135 |
15682 |
32 |
0 |
0 |
T141 |
102220 |
438 |
0 |
0 |
T164 |
13275 |
13 |
0 |
0 |
T168 |
13330 |
54 |
0 |
0 |
T169 |
7020 |
21 |
0 |
0 |
T170 |
6604 |
29 |
0 |
0 |
T172 |
7145 |
28 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2371 |
0 |
0 |
T115 |
13877 |
11 |
0 |
0 |
T132 |
10163 |
25 |
0 |
0 |
T134 |
14381 |
37 |
0 |
0 |
T135 |
15682 |
27 |
0 |
0 |
T141 |
102220 |
344 |
0 |
0 |
T164 |
13275 |
56 |
0 |
0 |
T168 |
13330 |
52 |
0 |
0 |
T169 |
7020 |
25 |
0 |
0 |
T170 |
6604 |
17 |
0 |
0 |
T172 |
7145 |
11 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2366 |
0 |
0 |
T115 |
13877 |
11 |
0 |
0 |
T132 |
10163 |
17 |
0 |
0 |
T134 |
14381 |
42 |
0 |
0 |
T135 |
15682 |
32 |
0 |
0 |
T141 |
102220 |
360 |
0 |
0 |
T164 |
13275 |
49 |
0 |
0 |
T168 |
13330 |
50 |
0 |
0 |
T169 |
7020 |
19 |
0 |
0 |
T170 |
6604 |
21 |
0 |
0 |
T172 |
7145 |
19 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2279 |
0 |
0 |
T115 |
13877 |
15 |
0 |
0 |
T132 |
10163 |
16 |
0 |
0 |
T134 |
14381 |
23 |
0 |
0 |
T135 |
15682 |
28 |
0 |
0 |
T141 |
102220 |
356 |
0 |
0 |
T164 |
13275 |
54 |
0 |
0 |
T168 |
13330 |
41 |
0 |
0 |
T169 |
7020 |
19 |
0 |
0 |
T170 |
6604 |
14 |
0 |
0 |
T172 |
7145 |
17 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2424 |
0 |
0 |
T115 |
13877 |
38 |
0 |
0 |
T132 |
10163 |
32 |
0 |
0 |
T134 |
14381 |
38 |
0 |
0 |
T135 |
15682 |
29 |
0 |
0 |
T141 |
102220 |
347 |
0 |
0 |
T164 |
13275 |
20 |
0 |
0 |
T168 |
13330 |
26 |
0 |
0 |
T169 |
7020 |
16 |
0 |
0 |
T170 |
6604 |
13 |
0 |
0 |
T172 |
7145 |
41 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
3640 |
0 |
0 |
T18 |
281172 |
18 |
0 |
0 |
T19 |
0 |
38 |
0 |
0 |
T38 |
0 |
8 |
0 |
0 |
T66 |
137049 |
0 |
0 |
0 |
T67 |
886037 |
0 |
0 |
0 |
T101 |
230827 |
0 |
0 |
0 |
T102 |
927 |
0 |
0 |
0 |
T137 |
2701 |
0 |
0 |
0 |
T165 |
48451 |
0 |
0 |
0 |
T166 |
21437 |
0 |
0 |
0 |
T174 |
0 |
23 |
0 |
0 |
T175 |
0 |
58 |
0 |
0 |
T176 |
0 |
23 |
0 |
0 |
T177 |
0 |
15 |
0 |
0 |
T178 |
0 |
11 |
0 |
0 |
T179 |
0 |
14 |
0 |
0 |
T180 |
0 |
37 |
0 |
0 |
T181 |
334676 |
0 |
0 |
0 |
T182 |
2954 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2315 |
0 |
0 |
T115 |
13877 |
8 |
0 |
0 |
T132 |
10163 |
25 |
0 |
0 |
T134 |
14381 |
12 |
0 |
0 |
T135 |
15682 |
27 |
0 |
0 |
T141 |
102220 |
403 |
0 |
0 |
T164 |
13275 |
14 |
0 |
0 |
T168 |
13330 |
48 |
0 |
0 |
T169 |
7020 |
53 |
0 |
0 |
T170 |
6604 |
19 |
0 |
0 |
T172 |
7145 |
39 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2251 |
0 |
0 |
T115 |
13877 |
1 |
0 |
0 |
T132 |
10163 |
28 |
0 |
0 |
T134 |
14381 |
26 |
0 |
0 |
T135 |
15682 |
29 |
0 |
0 |
T141 |
102220 |
404 |
0 |
0 |
T164 |
13275 |
20 |
0 |
0 |
T168 |
13330 |
38 |
0 |
0 |
T169 |
7020 |
16 |
0 |
0 |
T170 |
6604 |
6 |
0 |
0 |
T172 |
7145 |
9 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2150 |
0 |
0 |
T115 |
13877 |
12 |
0 |
0 |
T132 |
10163 |
15 |
0 |
0 |
T134 |
14381 |
14 |
0 |
0 |
T135 |
15682 |
25 |
0 |
0 |
T141 |
102220 |
367 |
0 |
0 |
T164 |
13275 |
34 |
0 |
0 |
T168 |
13330 |
36 |
0 |
0 |
T169 |
7020 |
19 |
0 |
0 |
T170 |
6604 |
15 |
0 |
0 |
T172 |
7145 |
30 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2315 |
0 |
0 |
T115 |
13877 |
6 |
0 |
0 |
T132 |
10163 |
21 |
0 |
0 |
T134 |
14381 |
32 |
0 |
0 |
T135 |
15682 |
21 |
0 |
0 |
T141 |
102220 |
393 |
0 |
0 |
T164 |
13275 |
54 |
0 |
0 |
T168 |
13330 |
89 |
0 |
0 |
T169 |
7020 |
5 |
0 |
0 |
T170 |
6604 |
7 |
0 |
0 |
T172 |
7145 |
18 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2268 |
0 |
0 |
T115 |
13877 |
30 |
0 |
0 |
T132 |
10163 |
8 |
0 |
0 |
T134 |
14381 |
28 |
0 |
0 |
T135 |
15682 |
17 |
0 |
0 |
T141 |
102220 |
380 |
0 |
0 |
T164 |
13275 |
36 |
0 |
0 |
T168 |
13330 |
25 |
0 |
0 |
T169 |
7020 |
11 |
0 |
0 |
T170 |
6604 |
14 |
0 |
0 |
T172 |
7145 |
44 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2282 |
0 |
0 |
T115 |
13877 |
10 |
0 |
0 |
T132 |
10163 |
22 |
0 |
0 |
T134 |
14381 |
11 |
0 |
0 |
T135 |
15682 |
21 |
0 |
0 |
T141 |
102220 |
410 |
0 |
0 |
T164 |
13275 |
37 |
0 |
0 |
T168 |
13330 |
33 |
0 |
0 |
T169 |
7020 |
1 |
0 |
0 |
T170 |
6604 |
8 |
0 |
0 |
T172 |
7145 |
35 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2417 |
0 |
0 |
T115 |
13877 |
26 |
0 |
0 |
T132 |
10163 |
17 |
0 |
0 |
T134 |
14381 |
34 |
0 |
0 |
T135 |
15682 |
35 |
0 |
0 |
T141 |
102220 |
415 |
0 |
0 |
T164 |
13275 |
6 |
0 |
0 |
T168 |
13330 |
48 |
0 |
0 |
T169 |
7020 |
10 |
0 |
0 |
T170 |
6604 |
12 |
0 |
0 |
T172 |
7145 |
47 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2259 |
0 |
0 |
T115 |
13877 |
21 |
0 |
0 |
T132 |
10163 |
8 |
0 |
0 |
T134 |
14381 |
26 |
0 |
0 |
T135 |
15682 |
23 |
0 |
0 |
T141 |
102220 |
362 |
0 |
0 |
T164 |
13275 |
33 |
0 |
0 |
T168 |
13330 |
28 |
0 |
0 |
T169 |
7020 |
61 |
0 |
0 |
T170 |
6604 |
7 |
0 |
0 |
T172 |
7145 |
22 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2770 |
0 |
0 |
T115 |
13877 |
38 |
0 |
0 |
T132 |
10163 |
50 |
0 |
0 |
T134 |
14381 |
35 |
0 |
0 |
T135 |
15682 |
61 |
0 |
0 |
T141 |
102220 |
413 |
0 |
0 |
T164 |
13275 |
42 |
0 |
0 |
T168 |
13330 |
9 |
0 |
0 |
T169 |
7020 |
2 |
0 |
0 |
T170 |
6604 |
39 |
0 |
0 |
T172 |
7145 |
30 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2177 |
0 |
0 |
T115 |
13877 |
4 |
0 |
0 |
T132 |
10163 |
13 |
0 |
0 |
T134 |
14381 |
30 |
0 |
0 |
T135 |
15682 |
27 |
0 |
0 |
T141 |
102220 |
359 |
0 |
0 |
T164 |
13275 |
38 |
0 |
0 |
T168 |
13330 |
28 |
0 |
0 |
T169 |
7020 |
8 |
0 |
0 |
T170 |
6604 |
18 |
0 |
0 |
T172 |
7145 |
26 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2274 |
0 |
0 |
T115 |
13877 |
19 |
0 |
0 |
T132 |
10163 |
17 |
0 |
0 |
T134 |
14381 |
27 |
0 |
0 |
T135 |
15682 |
33 |
0 |
0 |
T141 |
102220 |
388 |
0 |
0 |
T164 |
13275 |
34 |
0 |
0 |
T168 |
13330 |
62 |
0 |
0 |
T169 |
7020 |
25 |
0 |
0 |
T170 |
6604 |
17 |
0 |
0 |
T172 |
7145 |
16 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2036 |
0 |
0 |
T115 |
13877 |
6 |
0 |
0 |
T132 |
10163 |
17 |
0 |
0 |
T134 |
14381 |
19 |
0 |
0 |
T135 |
15682 |
26 |
0 |
0 |
T141 |
102220 |
390 |
0 |
0 |
T164 |
13275 |
2 |
0 |
0 |
T168 |
13330 |
1 |
0 |
0 |
T169 |
7020 |
17 |
0 |
0 |
T170 |
6604 |
34 |
0 |
0 |
T171 |
5984 |
8 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2136 |
0 |
0 |
T115 |
13877 |
14 |
0 |
0 |
T132 |
10163 |
11 |
0 |
0 |
T134 |
14381 |
22 |
0 |
0 |
T135 |
15682 |
30 |
0 |
0 |
T141 |
102220 |
369 |
0 |
0 |
T164 |
13275 |
13 |
0 |
0 |
T168 |
13330 |
34 |
0 |
0 |
T169 |
7020 |
21 |
0 |
0 |
T170 |
6604 |
9 |
0 |
0 |
T172 |
7145 |
9 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2227 |
0 |
0 |
T115 |
13877 |
23 |
0 |
0 |
T132 |
10163 |
22 |
0 |
0 |
T134 |
14381 |
19 |
0 |
0 |
T135 |
15682 |
26 |
0 |
0 |
T141 |
102220 |
351 |
0 |
0 |
T164 |
13275 |
94 |
0 |
0 |
T168 |
13330 |
31 |
0 |
0 |
T169 |
7020 |
24 |
0 |
0 |
T170 |
6604 |
11 |
0 |
0 |
T172 |
7145 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2031 |
0 |
0 |
T115 |
13877 |
10 |
0 |
0 |
T132 |
10163 |
2 |
0 |
0 |
T134 |
14381 |
17 |
0 |
0 |
T135 |
15682 |
24 |
0 |
0 |
T141 |
102220 |
348 |
0 |
0 |
T164 |
13275 |
57 |
0 |
0 |
T168 |
13330 |
20 |
0 |
0 |
T169 |
7020 |
17 |
0 |
0 |
T171 |
5984 |
11 |
0 |
0 |
T172 |
7145 |
19 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
447094412 |
2241 |
0 |
0 |
T115 |
13877 |
15 |
0 |
0 |
T132 |
10163 |
14 |
0 |
0 |
T134 |
14381 |
19 |
0 |
0 |
T135 |
15682 |
20 |
0 |
0 |
T141 |
102220 |
430 |
0 |
0 |
T164 |
13275 |
37 |
0 |
0 |
T168 |
13330 |
11 |
0 |
0 |
T169 |
7020 |
21 |
0 |
0 |
T172 |
7145 |
15 |
0 |
0 |
T173 |
16105 |
1 |
0 |
0 |