Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3367684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4029895

1

T1

12176

T2

7

T3

303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4060721	1			T1	1131		T2	1		T3	1
values[0x0]	1665856	1			T1	5820		T2	5		T3	191
values[0x1]	1671002	1			T1	5638		T2	5		T3	177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2389887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5007692

1

T1

12294

T2

7

T3

315

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26794	1			T1	4		T4	8		T6	65
valid_sources[0x01]	26131	1			T6	43		T8	8		T10	2
valid_sources[0x02]	26205	1			T6	21		T8	5		T10	1
valid_sources[0x03]	30916	1			T1	1		T6	56		T8	1
valid_sources[0x04]	25666	1			T1	1		T6	31		T8	3
valid_sources[0x05]	28528	1			T6	44		T8	5		T11	7
valid_sources[0x06]	26147	1			T2	1		T6	43		T8	5
valid_sources[0x07]	28587	1			T6	60		T8	8		T10	4
valid_sources[0x08]	27136	1			T4	33		T6	27		T8	6
valid_sources[0x09]	28390	1			T6	39		T8	1		T10	6
valid_sources[0x0a]	26653	1			T1	1		T6	29		T8	3
valid_sources[0x0b]	30101	1			T6	50		T8	9		T10	4
valid_sources[0x0c]	26972	1			T6	40		T8	4		T10	4
valid_sources[0x0d]	27182	1			T6	40		T8	1		T10	7
valid_sources[0x0e]	28705	1			T6	37		T10	9		T11	3
valid_sources[0x0f]	27505	1			T1	1		T2	1		T6	71
valid_sources[0x10]	28538	1			T1	1		T6	56		T8	3
valid_sources[0x11]	26041	1			T6	38		T8	5		T10	2
valid_sources[0x12]	27818	1			T6	31		T8	2		T10	4
valid_sources[0x13]	33176	1			T6	46		T8	1		T10	3
valid_sources[0x14]	27026	1			T6	55		T8	9		T10	8
valid_sources[0x15]	27841	1			T6	37		T8	4		T10	2
valid_sources[0x16]	25811	1			T6	41		T8	5		T10	2
valid_sources[0x17]	28043	1			T6	40		T8	4		T10	8
valid_sources[0x18]	27027	1			T6	46		T8	4		T10	1
valid_sources[0x19]	26549	1			T6	47		T7	450		T8	4
valid_sources[0x1a]	26813	1			T6	37		T7	441		T8	2
valid_sources[0x1b]	26126	1			T6	35		T8	2		T10	6
valid_sources[0x1c]	26608	1			T6	47		T8	4		T10	5
valid_sources[0x1d]	38957	1			T6	49		T8	8		T10	2
valid_sources[0x1e]	25908	1			T6	44		T8	3		T10	5
valid_sources[0x1f]	28688	1			T1	20		T6	39		T8	5
valid_sources[0x20]	33068	1			T1	1559		T6	37		T8	3
valid_sources[0x21]	31207	1			T6	45		T8	2		T10	4
valid_sources[0x22]	27328	1			T6	37		T8	3		T10	3
valid_sources[0x23]	29324	1			T6	40		T8	2		T10	3
valid_sources[0x24]	28998	1			T1	1		T6	38		T8	5
valid_sources[0x25]	25400	1			T1	1		T6	34		T8	9
valid_sources[0x26]	29766	1			T1	831		T6	27		T8	2
valid_sources[0x27]	41294	1			T6	59		T8	8		T10	4
valid_sources[0x28]	26193	1			T6	42		T8	4		T10	4
valid_sources[0x29]	30367	1			T6	35		T8	5		T10	5
valid_sources[0x2a]	27605	1			T1	498		T6	58		T8	6
valid_sources[0x2b]	29870	1			T6	42		T8	5		T10	2
valid_sources[0x2c]	28898	1			T6	61		T8	1		T10	1
valid_sources[0x2d]	26652	1			T1	1		T6	59		T8	5
valid_sources[0x2e]	27260	1			T1	1		T6	31		T8	3
valid_sources[0x2f]	26491	1			T6	47		T8	5		T10	2
valid_sources[0x30]	26573	1			T1	1		T6	39		T8	1
valid_sources[0x31]	25479	1			T1	6		T4	120		T6	42
valid_sources[0x32]	29010	1			T6	36		T8	5		T10	9
valid_sources[0x33]	29741	1			T2	1		T6	49		T8	8
valid_sources[0x34]	29748	1			T6	41		T8	5		T10	4
valid_sources[0x35]	25895	1			T6	60		T8	3		T10	3
valid_sources[0x36]	28920	1			T1	441		T6	45		T8	3
valid_sources[0x37]	42947	1			T6	34		T8	9		T10	7
valid_sources[0x38]	29294	1			T6	47		T8	4		T10	4
valid_sources[0x39]	27317	1			T1	64		T6	38		T8	3
valid_sources[0x3a]	32651	1			T6	61		T8	4		T10	3
valid_sources[0x3b]	28005	1			T6	58		T10	2		T11	8
valid_sources[0x3c]	28285	1			T1	903		T6	23		T8	2
valid_sources[0x3d]	28711	1			T6	54		T8	7		T10	1
valid_sources[0x3e]	26746	1			T1	553		T6	49		T8	9
valid_sources[0x3f]	28794	1			T6	33		T8	8		T10	5
valid_sources[0x40]	28204	1			T1	314		T6	37		T8	2
valid_sources[0x41]	29160	1			T5	1		T6	21		T8	3
valid_sources[0x42]	25974	1			T6	44		T8	5		T10	3
valid_sources[0x43]	27088	1			T1	2		T6	59		T8	2
valid_sources[0x44]	27370	1			T6	44		T8	4		T10	2
valid_sources[0x45]	30774	1			T6	42		T8	10		T10	1
valid_sources[0x46]	27862	1			T1	107		T6	25		T8	11
valid_sources[0x47]	29498	1			T6	42		T8	6		T10	1
valid_sources[0x48]	26965	1			T6	34		T8	3		T10	2
valid_sources[0x49]	24864	1			T6	47		T8	3		T10	4
valid_sources[0x4a]	25903	1			T6	48		T8	5		T10	6
valid_sources[0x4b]	27169	1			T1	1		T6	47		T8	4
valid_sources[0x4c]	45797	1			T1	1		T5	14336		T6	36
valid_sources[0x4d]	28267	1			T1	1090		T6	36		T8	5
valid_sources[0x4e]	28060	1			T6	67		T8	4		T10	6
valid_sources[0x4f]	26987	1			T6	38		T8	1		T10	1
valid_sources[0x50]	25959	1			T6	49		T8	11		T11	8
valid_sources[0x51]	27304	1			T6	36		T8	6		T10	2
valid_sources[0x52]	30028	1			T1	1		T6	46		T8	2
valid_sources[0x53]	26496	1			T6	44		T8	6		T10	2
valid_sources[0x54]	27596	1			T1	653		T6	61		T8	5
valid_sources[0x55]	28999	1			T1	2		T6	53		T8	4
valid_sources[0x56]	29664	1			T1	417		T6	41		T8	2
valid_sources[0x57]	29564	1			T6	43		T8	6		T10	4
valid_sources[0x58]	26996	1			T6	54		T8	6		T10	3
valid_sources[0x59]	27847	1			T1	2		T6	39		T8	3
valid_sources[0x5a]	26604	1			T6	61		T8	1		T10	3
valid_sources[0x5b]	29742	1			T6	30		T8	8		T10	1
valid_sources[0x5c]	35697	1			T1	416		T2	1		T6	72
valid_sources[0x5d]	30071	1			T6	51		T8	5		T10	5
valid_sources[0x5e]	24921	1			T6	59		T8	2		T10	1
valid_sources[0x5f]	28124	1			T6	56		T8	4		T10	3
valid_sources[0x60]	27377	1			T6	41		T8	3		T10	3
valid_sources[0x61]	26419	1			T4	70		T6	34		T8	1
valid_sources[0x62]	26554	1			T1	1		T6	40		T8	2
valid_sources[0x63]	28396	1			T1	1		T2	1		T6	43
valid_sources[0x64]	24725	1			T6	39		T8	2		T10	1
valid_sources[0x65]	30172	1			T6	53		T8	7		T10	5
valid_sources[0x66]	31006	1			T6	31		T8	5		T10	4
valid_sources[0x67]	26037	1			T1	1		T6	27		T8	10
valid_sources[0x68]	27497	1			T1	1		T6	45		T8	1
valid_sources[0x69]	37913	1			T6	25		T8	1		T9	22
valid_sources[0x6a]	26730	1			T6	18		T8	4		T10	1
valid_sources[0x6b]	30940	1			T6	53		T8	2		T10	4
valid_sources[0x6c]	31083	1			T1	1		T6	57		T8	1
valid_sources[0x6d]	28326	1			T6	32		T8	7		T10	2
valid_sources[0x6e]	29618	1			T6	52		T8	8		T10	6
valid_sources[0x6f]	41921	1			T5	452		T6	25		T8	4
valid_sources[0x70]	26572	1			T2	1		T6	39		T8	2
valid_sources[0x71]	27404	1			T6	77		T8	4		T10	6
valid_sources[0x72]	26764	1			T6	54		T8	1		T9	417
valid_sources[0x73]	26964	1			T5	591		T6	48		T8	5
valid_sources[0x74]	25681	1			T6	39		T8	6		T10	5
valid_sources[0x75]	45968	1			T6	59		T8	4		T11	10
valid_sources[0x76]	26699	1			T1	74		T6	53		T8	3
valid_sources[0x77]	28466	1			T6	34		T8	1		T10	1
valid_sources[0x78]	34104	1			T1	1		T6	59		T8	3
valid_sources[0x79]	25428	1			T6	22		T8	2		T10	3
valid_sources[0x7a]	27460	1			T6	67		T8	4		T10	1
valid_sources[0x7b]	47044	1			T1	1		T6	36		T8	2
valid_sources[0x7c]	28111	1			T1	1		T6	49		T8	5
valid_sources[0x7d]	26526	1			T6	40		T8	2		T10	5
valid_sources[0x7e]	26347	1			T1	1		T6	49		T8	2
valid_sources[0x7f]	28401	1			T6	55		T8	4		T10	1
valid_sources[0x80]	24768	1			T6	51		T8	5		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1002646

1

T1

782

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1522846

1

T1

5796

T2

3

T3

155

values[0x1]

all_enables

biggest_size

1504403

1

T1

5598

T2

3

T3

147