Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3385501

1

T1

413

T2

4

T3

66

full_word

4028836

1

T1

12176

T2

7

T3

303

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7413937	1			T1	12589		T2	11		T3	369
auto[TlIntgErrCmd]	144	1			T103	7		T107	6		T109	7
auto[TlIntgErrData]	123	1			T103	6		T107	8		T109	7
auto[TlIntgErrBoth]	133	1			T103	7		T107	6		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4062169

1

T1

1131

T2

1

T3

1

auto[1]

3352168

1

T1

11458

T2

10

T3

368

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3059290	1			T1	349		T5	18523		T6	489
auto[TlIntgErrNone]	partial	auto[1]	325837	1			T1	64		T2	4		T3	66
auto[TlIntgErrNone]	full_word	auto[0]	1002703	1			T1	782		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3026107	1			T1	11394		T2	6		T3	302
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T103	4		T107	2		T109	5
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T103	2		T107	4		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T103	1		T182	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T184	1		T186	1		T185	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T103	1		T107	3		T109	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T103	4		T107	4		T109	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T107	1		T109	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T103	1		T187	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T103	2		T107	2		T109	3
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T103	5		T107	4		T109	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T187	1		T186	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T184	1		T186	1		-	-