Unified Coverage Report :: Module :: spid_jedec

Module : spid_jedec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_jedec	99.38	100.00	100.00		100.00	96.88	100.00

---

Module Instance : tb.dut.u_jedec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
TOTAL		47	47	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
ALWAYS	83	4	4	100.00
ALWAYS	91	5	5	100.00
ALWAYS	101	8	8	100.00
ALWAYS	121	4	4	100.00
CONT_ASSIGN	125	1	1	100.00
ALWAYS	132	3	3	100.00
ALWAYS	138	16	16	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
73	2	2
74	2	2
			MISSING_ELSE
79	1	1
83	2	2
84	1	1
85	1	1
			MISSING_ELSE
91	1	1
92	1	1
93	1	1
95	1	1
96	1	1
101	1	1
103	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
113	1	1
121	2	2
122	2	2
			MISSING_ELSE
125	1	1
132	2	2
133	1	1
138	1	1
140	1	1
141	1	1
143	1	1
145	1	1
146	1	1
149	1	1
			MISSING_ELSE
160	1	1
161	1	1
			MISSING_ELSE
164	1	1
168	1	1
169	1	1
			MISSING_ELSE
172	1	1
179	1	1
181	1	1
182	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spid_jedec

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION ((st_q == StCC) && outclk_p2s_sent_i)
             -------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T25
1	0	Covered	T1,T6,T25
1	1	Covered	T1,T6,T25

 LINE       84
 SUB-EXPRESSION (st_q == StCC)
                -------1------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T6,T25

 LINE       103
 EXPRESSION (st_q == StIdle)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION (cc_needed ? jedec.cc : jedec.jedec_id)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       106
 EXPRESSION (st_q == StCC)
            -------1------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       108
 EXPRESSION (st_q == StJedecId)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       113
 EXPRESSION ((byte_sel_q >= 2'b10) ? 8'b0 : ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0]))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       113
 SUB-EXPRESSION ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0])
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       113
 SUB-EXPRESSION (byte_sel_q == 2'b1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       125
 EXPRESSION ((byte_sel_q == 2'b10) ? 2'b10 : ((byte_sel_q + 1'b1)))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T25

 LINE       125
 SUB-EXPRESSION (byte_sel_q == 2'b10)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T25

 LINE       145
 EXPRESSION (sel_dp_i == DpReadJEDEC)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T25

 LINE       146
 EXPRESSION (cc_needed ? StCC : StJedecId)
             ----1----

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

 LINE       160
 EXPRESSION (cc_count == jedec.num_cc)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T6,T25
1	Covered	T1,T6,T25

---

FSM Coverage for Module : spid_jedec

Summary for FSM :: st_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StCC	146	Covered	T1,T6,T25
StDevId	169	Covered	T1,T6,T25
StIdle	103	Covered	T1,T2,T3
StJedecId	146	Covered	T1,T6,T25

transitions	Line No.	Covered	Tests
StCC->StJedecId	161	Covered	T1,T6,T25
StIdle->StCC	146	Covered	T1,T6,T25
StIdle->StJedecId	146	Covered	T1,T6,T25
StJedecId->StDevId	169	Covered	T1,T6,T25

---

Branch Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
Branches		32	31	96.88
TERNARY	125	2	2	100.00
IF	73	3	3	100.00
IF	83	3	3	100.00
IF	91	2	2	100.00
IF	103	7	7	100.00
IF	121	3	3	100.00
IF	132	2	2	100.00
CASE	143	10	9	90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	((byte_sel_q == 2'b10)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	74	if (cmd_sync_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	83	if ((!rst_ni))
-2-:	84	if (((st_q == StCC) && outclk_p2s_sent_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T6,T25
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	91	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	103	if ((st_q == StIdle))
-2-:	105	(cc_needed) ? 
-3-:	106	if ((st_q == StCC))
-4-:	108	if ((st_q == StJedecId))
-5-:	113	((byte_sel_q >= 2'b10)) ? 
-6-:	113	((byte_sel_q == 2'b1)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	1	-	-	-	-	Covered	T1,T5,T6
1	0	-	-	-	-	Covered	T1,T2,T3
0	-	1	-	-	-	Covered	T1,T6,T25
0	-	0	1	-	-	Covered	T1,T6,T25
0	-	0	0	1	-	Covered	T1,T6,T25
0	-	0	0	0	1	Covered	T1,T6,T25
0	-	0	0	0	0	Covered	T1,T6,T25

	LineNo.	Expression
-1-:	121	if ((!rst_ni))
-2-:	122	if (next_byte)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T6,T25
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	132	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	143	case (st_q)
-2-:	145	if ((sel_dp_i == DpReadJEDEC))
-3-:	146	(cc_needed) ? 
-4-:	160	if ((cc_count == jedec.num_cc))
-5-:	168	if (outclk_p2s_sent_i)
-6-:	181	if (outclk_p2s_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	1	-	-	-	Covered	T1,T6,T25
StIdle	1	0	-	-	-	Covered	T1,T6,T25
StIdle	0	-	-	-	-	Covered	T1,T2,T3
StCC	-	-	1	-	-	Covered	T1,T6,T25
StCC	-	-	0	-	-	Covered	T1,T6,T25
StJedecId	-	-	-	1	-	Covered	T1,T6,T25
StJedecId	-	-	-	0	-	Covered	T1,T6,T25
StDevId	-	-	-	-	1	Covered	T1,T6,T25
StDevId	-	-	-	-	0	Covered	T1,T6,T25
default	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spid_jedec

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
JedecStKnown_A	138927465	111388448	0	0

JedecStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	111388448	0	0
T1	497600	495149	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	157120	0	0
T6	881672	878711	0	0
T7	56975	56252	0	0
T8	102209	0	0	0
T9	256	256	0	0
T10	109617	109256	0	0
T11	3008	0	0	0
T12	0	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0