Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	2736197	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	2736197	0	0
T1	268092	15831	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	1663	0	0
T6	556922	13340	0	0
T7	19193	1663	0	0
T8	835281	0	0	0
T9	5580	1663	0	0
T10	448307	832	0	0
T12	0	1663	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	3013969	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	3013969	0	0
T1	268092	31491	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	26781	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T16	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	178036	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	178036	0	0
T1	268092	512	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	0	0	0
T6	556922	583	0	0
T7	19193	0	0	0
T8	835281	0	0	0
T9	5580	0	0	0
T10	448307	0	0	0
T11	0	61	0	0
T17	0	1193	0	0
T25	0	1034	0	0
T26	0	603	0	0
T27	0	1	0	0
T28	0	1002	0	0
T36	0	100	0	0
T40	0	271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	393215	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	393215	0	0
T1	268092	2257	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	0	0	0
T6	556922	2482	0	0
T7	19193	0	0	0
T8	835281	0	0	0
T9	5580	0	0	0
T10	448307	0	0	0
T11	0	61	0	0
T17	0	1193	0	0
T25	0	1034	0	0
T26	0	603	0	0
T27	0	1	0	0
T28	0	1002	0	0
T36	0	100	0	0
T40	0	271	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	5834443	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	5834443	0	0
T1	268092	1295	0	0
T2	876	11	0	0
T3	77513	369	0	0
T4	242990	826	0	0
T5	793485	37026	0	0
T6	556922	1530	0	0
T7	19193	59	0	0
T8	835281	1068	0	0
T9	5580	74	0	0
T10	448307	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	424186993	11958534	0	0
DepthKnown_A	424186993	424053567	0	0
RvalidKnown_A	424186993	424053567	0	0
WreadyKnown_A	424186993	424053567	0	0
gen_passthru_fifo.paramCheckPass	1150	1150	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	11958534	0	0
T1	268092	5603	0	0
T2	876	11	0	0
T3	77513	369	0	0
T4	242990	3666	0	0
T5	793485	37025	0	0
T6	556922	6427	0	0
T7	19193	59	0	0
T8	835281	1068	0	0
T9	5580	303	0	0
T10	448307	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	424186993	424053567	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0