Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T25,T26
1	0	Covered	T11,T25,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Unreachable
1	1	Covered	T11,T25,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T25

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T25
1	0	Covered	T1,T6,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T6,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T11
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	699288495	559004232	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	699288495	3556578	0	0
GntImpliesValid_A	699288495	3556578	0	0
GrantKnown_A	699288495	559004232	0	0
IdxKnown_A	699288495	559004232	0	0
IndexIsCorrect_A	699288495	3556578	0	0
LockArbDecision_A	699288495	0	0	0
NoReadyValidNoGrant_A	699288495	0	0	0
ReadyAndValidImplyGrant_A	699288495	3556578	0	0
ReqAndReadyImplyGrant_A	699288495	3556578	0	0
ReqImpliesValid_A	699288495	3556578	0	0
ReqStaysHighUntilGranted0_M	699288495	0	0	0
RoundRobin_A	699288495	6	0	975
ValidKnown_A	699288495	559004232	0	0
gen_data_port_assertion.DataFlow_A	699288495	3556578	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	559004232	0	0
T1	765692	763189	0	0
T2	876	825	0	0
T3	187909	128256	0	0
T4	450412	343017	0	0
T5	1110469	950506	0	0
T6	2320266	1435536	0	0
T7	133143	75354	0	0
T8	1039699	933450	0	0
T9	6092	5736	0	0
T10	667541	557470	0	0
T11	6016	3008	0	0
T12	74864	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	559004232	0	0
T1	765692	763189	0	0
T2	876	825	0	0
T3	187909	128256	0	0
T4	450412	343017	0	0
T5	1110469	950506	0	0
T6	2320266	1435536	0	0
T7	133143	75354	0	0
T8	1039699	933450	0	0
T9	6092	5736	0	0
T10	667541	557470	0	0
T11	6016	3008	0	0
T12	74864	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	559004232	0	0
T1	765692	763189	0	0
T2	876	825	0	0
T3	187909	128256	0	0
T4	450412	343017	0	0
T5	1110469	950506	0	0
T6	2320266	1435536	0	0
T7	133143	75354	0	0
T8	1039699	933450	0	0
T9	6092	5736	0	0
T10	667541	557470	0	0
T11	6016	3008	0	0
T12	74864	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	6	0	975
T56	181946	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	141213	0	0	1
T63	1248	0	0	1
T64	1329	0	0	1
T65	495062	0	0	1
T66	38735	0	0	1
T67	129665	0	0	1
T68	141034	0	0	1
T69	10690	0	0	1
T70	118996	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	559004232	0	0
T1	765692	763189	0	0
T2	876	825	0	0
T3	187909	128256	0	0
T4	450412	343017	0	0
T5	1110469	950506	0	0
T6	2320266	1435536	0	0
T7	133143	75354	0	0
T8	1039699	933450	0	0
T9	6092	5736	0	0
T10	667541	557470	0	0
T11	6016	3008	0	0
T12	74864	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699288495	3556578	0	0
T1	765692	16770	0	0
T2	876	0	0	0
T3	132711	0	0	0
T4	346701	0	0	0
T5	951977	832	0	0
T6	1438594	20777	0	0
T7	76168	832	0	0
T8	937490	0	0	0
T9	5836	832	0	0
T10	557924	832	0	0
T11	6016	336	0	0
T12	74864	832	0	0
T13	98906	832	0	0
T14	43142	832	0	0
T16	14494	0	0	0
T17	813238	12277	0	0
T18	0	13804	0	0
T25	951822	12607	0	0
T26	194490	2935	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	1388	0	0
T52	0	5501	0	0
T53	0	10	0	0
T54	0	1294	0	0
T55	0	7756	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T25,T26
1	0	Covered	T11,T25,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T8
1	0	Unreachable
1	1	Covered	T11,T25,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T25,T26
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T25,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T25,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138927465	26270857	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	138927465	579620	0	0
GntImpliesValid_A	138927465	579620	0	0
GrantKnown_A	138927465	26270857	0	0
IdxKnown_A	138927465	26270857	0	0
IndexIsCorrect_A	138927465	579620	0	0
LockArbDecision_A	138927465	0	0	0
NoReadyValidNoGrant_A	138927465	0	0	0
ReadyAndValidImplyGrant_A	138927465	579620	0	0
ReqAndReadyImplyGrant_A	138927465	579620	0	0
ReqImpliesValid_A	138927465	579620	0	0
ReqStaysHighUntilGranted0_M	138927465	0	0	0
RoundRobin_A	138927465	0	0	0
ValidKnown_A	138927465	26270857	0	0
gen_data_port_assertion.DataFlow_A	138927465	579620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	26270857	0	0
T3	55198	50800	0	0
T4	103711	100088	0	0
T5	158492	0	0	0
T6	881672	0	0	0
T7	56975	0	0	0
T8	102209	98248	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	3008	0	0
T12	74864	0	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	26270857	0	0
T3	55198	50800	0	0
T4	103711	100088	0	0
T5	158492	0	0	0
T6	881672	0	0	0
T7	56975	0	0	0
T8	102209	98248	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	3008	0	0
T12	74864	0	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	26270857	0	0
T3	55198	50800	0	0
T4	103711	100088	0	0
T5	158492	0	0	0
T6	881672	0	0	0
T7	56975	0	0	0
T8	102209	98248	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	3008	0	0
T12	74864	0	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	26270857	0	0
T3	55198	50800	0	0
T4	103711	100088	0	0
T5	158492	0	0	0
T6	881672	0	0	0
T7	56975	0	0	0
T8	102209	98248	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	3008	0	0
T12	74864	0	0	0
T17	0	57448	0	0
T25	0	103864	0	0
T26	0	77952	0	0
T27	0	768	0	0
T28	0	143376	0	0
T29	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	579620	0	0
T11	3008	257	0	0
T12	74864	0	0	0
T13	98906	0	0	0
T14	43142	0	0	0
T16	14494	0	0	0
T17	813238	2519	0	0
T18	0	4432	0	0
T25	951822	3754	0	0
T26	194490	2640	0	0
T27	768	21	0	0
T28	151413	5821	0	0
T40	0	991	0	0
T52	0	5244	0	0
T53	0	10	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T25

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T25
1	0	Covered	T1,T6,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T6,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T25
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T25
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138927465	111388448	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	138927465	831126	0	0
GntImpliesValid_A	138927465	831126	0	0
GrantKnown_A	138927465	111388448	0	0
IdxKnown_A	138927465	111388448	0	0
IndexIsCorrect_A	138927465	831126	0	0
LockArbDecision_A	138927465	0	0	0
NoReadyValidNoGrant_A	138927465	0	0	0
ReadyAndValidImplyGrant_A	138927465	831126	0	0
ReqAndReadyImplyGrant_A	138927465	831126	0	0
ReqImpliesValid_A	138927465	831126	0	0
ReqStaysHighUntilGranted0_M	138927465	0	0	0
RoundRobin_A	138927465	0	0	0
ValidKnown_A	138927465	111388448	0	0
gen_data_port_assertion.DataFlow_A	138927465	831126	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	111388448	0	0
T1	497600	495149	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	157120	0	0
T6	881672	878711	0	0
T7	56975	56252	0	0
T8	102209	0	0	0
T9	256	256	0	0
T10	109617	109256	0	0
T11	3008	0	0	0
T12	0	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	111388448	0	0
T1	497600	495149	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	157120	0	0
T6	881672	878711	0	0
T7	56975	56252	0	0
T8	102209	0	0	0
T9	256	256	0	0
T10	109617	109256	0	0
T11	3008	0	0	0
T12	0	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	111388448	0	0
T1	497600	495149	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	157120	0	0
T6	881672	878711	0	0
T7	56975	56252	0	0
T8	102209	0	0	0
T9	256	256	0	0
T10	109617	109256	0	0
T11	3008	0	0	0
T12	0	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	111388448	0	0
T1	497600	495149	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	157120	0	0
T6	881672	878711	0	0
T7	56975	56252	0	0
T8	102209	0	0	0
T9	256	256	0	0
T10	109617	109256	0	0
T11	3008	0	0	0
T12	0	74596	0	0
T13	0	98694	0	0
T14	0	43142	0	0
T16	0	14494	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138927465	831126	0	0
T1	497600	5405	0	0
T3	55198	0	0	0
T4	103711	0	0	0
T5	158492	0	0	0
T6	881672	11012	0	0
T7	56975	0	0	0
T8	102209	0	0	0
T9	256	0	0	0
T10	109617	0	0	0
T11	3008	0	0	0
T17	0	9758	0	0
T18	0	9372	0	0
T25	0	8853	0	0
T26	0	295	0	0
T40	0	397	0	0
T52	0	257	0	0
T54	0	1294	0	0
T55	0	7756	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T11
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421433565	421344927	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	421433565	2145832	0	0
GntImpliesValid_A	421433565	2145832	0	0
GrantKnown_A	421433565	421344927	0	0
IdxKnown_A	421433565	421344927	0	0
IndexIsCorrect_A	421433565	2145832	0	0
LockArbDecision_A	421433565	0	0	0
NoReadyValidNoGrant_A	421433565	0	0	0
ReadyAndValidImplyGrant_A	421433565	2145832	0	0
ReqAndReadyImplyGrant_A	421433565	2145832	0	0
ReqImpliesValid_A	421433565	2145832	0	0
ReqStaysHighUntilGranted0_M	421433565	0	0	0
RoundRobin_A	421433565	6	0	975
ValidKnown_A	421433565	421344927	0	0
gen_data_port_assertion.DataFlow_A	421433565	2145832	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	421344927	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	421344927	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	421344927	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	6	0	975
T56	181946	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	141213	0	0	1
T63	1248	0	0	1
T64	1329	0	0	1
T65	495062	0	0	1
T66	38735	0	0	1
T67	129665	0	0	1
T68	141034	0	0	1
T69	10690	0	0	1
T70	118996	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	421344927	0	0
T1	268092	268040	0	0
T2	876	825	0	0
T3	77513	77456	0	0
T4	242990	242929	0	0
T5	793485	793386	0	0
T6	556922	556825	0	0
T7	19193	19102	0	0
T8	835281	835202	0	0
T9	5580	5480	0	0
T10	448307	448214	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421433565	2145832	0	0
T1	268092	11365	0	0
T2	876	0	0	0
T3	77513	0	0	0
T4	242990	0	0	0
T5	793485	832	0	0
T6	556922	9765	0	0
T7	19193	832	0	0
T8	835281	0	0	0
T9	5580	832	0	0
T10	448307	832	0	0
T11	0	79	0	0
T12	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0