Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3752 |
0 |
0 |
T103 |
54018 |
3 |
0 |
0 |
T104 |
8902 |
108 |
0 |
0 |
T105 |
4725 |
43 |
0 |
0 |
T106 |
4469 |
3 |
0 |
0 |
T107 |
52985 |
4 |
0 |
0 |
T108 |
13852 |
238 |
0 |
0 |
T110 |
5049 |
4 |
0 |
0 |
T120 |
2603 |
146 |
0 |
0 |
T129 |
5658 |
11 |
0 |
0 |
T130 |
4819 |
9 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3347 |
0 |
0 |
T133 |
37363 |
240 |
0 |
0 |
T134 |
6466 |
1 |
0 |
0 |
T135 |
113555 |
822 |
0 |
0 |
T138 |
8345 |
9 |
0 |
0 |
T142 |
10163 |
11 |
0 |
0 |
T163 |
180450 |
433 |
0 |
0 |
T164 |
17802 |
32 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
1 |
0 |
0 |
T167 |
4605 |
6 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3630 |
0 |
0 |
T133 |
37363 |
220 |
0 |
0 |
T135 |
113555 |
781 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
8 |
0 |
0 |
T143 |
181709 |
475 |
0 |
0 |
T163 |
180450 |
456 |
0 |
0 |
T164 |
17802 |
50 |
0 |
0 |
T165 |
7251 |
2 |
0 |
0 |
T166 |
9876 |
7 |
0 |
0 |
T167 |
4605 |
6 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
4183 |
0 |
0 |
T133 |
37363 |
208 |
0 |
0 |
T134 |
6466 |
6 |
0 |
0 |
T135 |
113555 |
851 |
0 |
0 |
T138 |
8345 |
19 |
0 |
0 |
T142 |
10163 |
25 |
0 |
0 |
T163 |
180450 |
443 |
0 |
0 |
T164 |
17802 |
63 |
0 |
0 |
T165 |
7251 |
14 |
0 |
0 |
T166 |
9876 |
3 |
0 |
0 |
T167 |
4605 |
16 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13105 |
0 |
0 |
T133 |
37363 |
256 |
0 |
0 |
T134 |
6466 |
2 |
0 |
0 |
T135 |
113555 |
837 |
0 |
0 |
T138 |
8345 |
147 |
0 |
0 |
T142 |
10163 |
9 |
0 |
0 |
T163 |
180450 |
409 |
0 |
0 |
T164 |
17802 |
74 |
0 |
0 |
T165 |
7251 |
13 |
0 |
0 |
T166 |
9876 |
55 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13647 |
0 |
0 |
T133 |
37363 |
206 |
0 |
0 |
T135 |
113555 |
873 |
0 |
0 |
T138 |
8345 |
120 |
0 |
0 |
T142 |
10163 |
230 |
0 |
0 |
T143 |
181709 |
474 |
0 |
0 |
T163 |
180450 |
482 |
0 |
0 |
T164 |
17802 |
60 |
0 |
0 |
T165 |
7251 |
44 |
0 |
0 |
T166 |
9876 |
167 |
0 |
0 |
T167 |
4605 |
129 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13010 |
0 |
0 |
T133 |
37363 |
197 |
0 |
0 |
T134 |
6466 |
50 |
0 |
0 |
T135 |
113555 |
774 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
10 |
0 |
0 |
T163 |
180450 |
428 |
0 |
0 |
T164 |
17802 |
91 |
0 |
0 |
T165 |
7251 |
32 |
0 |
0 |
T166 |
9876 |
80 |
0 |
0 |
T167 |
4605 |
116 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
14072 |
0 |
0 |
T133 |
37363 |
211 |
0 |
0 |
T134 |
6466 |
63 |
0 |
0 |
T135 |
113555 |
773 |
0 |
0 |
T138 |
8345 |
148 |
0 |
0 |
T142 |
10163 |
158 |
0 |
0 |
T163 |
180450 |
428 |
0 |
0 |
T164 |
17802 |
76 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
59 |
0 |
0 |
T167 |
4605 |
148 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13807 |
0 |
0 |
T133 |
37363 |
206 |
0 |
0 |
T135 |
113555 |
824 |
0 |
0 |
T138 |
8345 |
104 |
0 |
0 |
T142 |
10163 |
143 |
0 |
0 |
T143 |
181709 |
442 |
0 |
0 |
T163 |
180450 |
477 |
0 |
0 |
T164 |
17802 |
55 |
0 |
0 |
T165 |
7251 |
35 |
0 |
0 |
T166 |
9876 |
16 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13668 |
0 |
0 |
T133 |
37363 |
201 |
0 |
0 |
T134 |
6466 |
80 |
0 |
0 |
T135 |
113555 |
760 |
0 |
0 |
T138 |
8345 |
252 |
0 |
0 |
T142 |
10163 |
292 |
0 |
0 |
T163 |
180450 |
427 |
0 |
0 |
T164 |
17802 |
50 |
0 |
0 |
T165 |
7251 |
37 |
0 |
0 |
T166 |
9876 |
77 |
0 |
0 |
T167 |
4605 |
112 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
13189 |
0 |
0 |
T133 |
37363 |
252 |
0 |
0 |
T134 |
6466 |
62 |
0 |
0 |
T135 |
113555 |
827 |
0 |
0 |
T138 |
8345 |
250 |
0 |
0 |
T142 |
10163 |
122 |
0 |
0 |
T163 |
180450 |
405 |
0 |
0 |
T164 |
17802 |
81 |
0 |
0 |
T165 |
7251 |
28 |
0 |
0 |
T166 |
9876 |
97 |
0 |
0 |
T167 |
4605 |
5 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
14505 |
0 |
0 |
T133 |
37363 |
231 |
0 |
0 |
T134 |
6466 |
138 |
0 |
0 |
T135 |
113555 |
815 |
0 |
0 |
T138 |
8345 |
231 |
0 |
0 |
T142 |
10163 |
241 |
0 |
0 |
T163 |
180450 |
413 |
0 |
0 |
T164 |
17802 |
36 |
0 |
0 |
T165 |
7251 |
18 |
0 |
0 |
T166 |
9876 |
147 |
0 |
0 |
T167 |
4605 |
109 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7249 |
0 |
0 |
T133 |
37363 |
230 |
0 |
0 |
T134 |
6466 |
28 |
0 |
0 |
T135 |
113555 |
759 |
0 |
0 |
T138 |
8345 |
91 |
0 |
0 |
T142 |
10163 |
7 |
0 |
0 |
T163 |
180450 |
493 |
0 |
0 |
T164 |
17802 |
54 |
0 |
0 |
T165 |
7251 |
10 |
0 |
0 |
T166 |
9876 |
61 |
0 |
0 |
T167 |
4605 |
44 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
6827 |
0 |
0 |
T133 |
37363 |
236 |
0 |
0 |
T134 |
6466 |
23 |
0 |
0 |
T135 |
113555 |
760 |
0 |
0 |
T138 |
8345 |
62 |
0 |
0 |
T142 |
10163 |
97 |
0 |
0 |
T163 |
180450 |
419 |
0 |
0 |
T164 |
17802 |
73 |
0 |
0 |
T165 |
7251 |
10 |
0 |
0 |
T166 |
9876 |
20 |
0 |
0 |
T167 |
4605 |
44 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
6834 |
0 |
0 |
T133 |
37363 |
245 |
0 |
0 |
T134 |
6466 |
9 |
0 |
0 |
T135 |
113555 |
749 |
0 |
0 |
T138 |
8345 |
74 |
0 |
0 |
T142 |
10163 |
35 |
0 |
0 |
T163 |
180450 |
394 |
0 |
0 |
T164 |
17802 |
43 |
0 |
0 |
T165 |
7251 |
6 |
0 |
0 |
T166 |
9876 |
46 |
0 |
0 |
T167 |
4605 |
1 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7475 |
0 |
0 |
T133 |
37363 |
286 |
0 |
0 |
T134 |
6466 |
38 |
0 |
0 |
T135 |
113555 |
840 |
0 |
0 |
T138 |
8345 |
105 |
0 |
0 |
T142 |
10163 |
41 |
0 |
0 |
T163 |
180450 |
442 |
0 |
0 |
T164 |
17802 |
23 |
0 |
0 |
T165 |
7251 |
22 |
0 |
0 |
T166 |
9876 |
8 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7730 |
0 |
0 |
T133 |
37363 |
235 |
0 |
0 |
T135 |
113555 |
755 |
0 |
0 |
T138 |
8345 |
91 |
0 |
0 |
T142 |
10163 |
66 |
0 |
0 |
T143 |
181709 |
434 |
0 |
0 |
T163 |
180450 |
399 |
0 |
0 |
T164 |
17802 |
34 |
0 |
0 |
T165 |
7251 |
16 |
0 |
0 |
T167 |
4605 |
5 |
0 |
0 |
T168 |
5787 |
4 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7453 |
0 |
0 |
T133 |
37363 |
228 |
0 |
0 |
T134 |
6466 |
61 |
0 |
0 |
T135 |
113555 |
751 |
0 |
0 |
T138 |
8345 |
53 |
0 |
0 |
T142 |
10163 |
29 |
0 |
0 |
T143 |
181709 |
447 |
0 |
0 |
T163 |
180450 |
456 |
0 |
0 |
T164 |
17802 |
88 |
0 |
0 |
T165 |
7251 |
31 |
0 |
0 |
T166 |
9876 |
30 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7350 |
0 |
0 |
T133 |
37363 |
233 |
0 |
0 |
T134 |
6466 |
33 |
0 |
0 |
T135 |
113555 |
697 |
0 |
0 |
T138 |
8345 |
67 |
0 |
0 |
T142 |
10163 |
65 |
0 |
0 |
T163 |
180450 |
384 |
0 |
0 |
T164 |
17802 |
38 |
0 |
0 |
T165 |
7251 |
28 |
0 |
0 |
T166 |
9876 |
26 |
0 |
0 |
T167 |
4605 |
56 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7542 |
0 |
0 |
T133 |
37363 |
246 |
0 |
0 |
T135 |
113555 |
757 |
0 |
0 |
T138 |
8345 |
42 |
0 |
0 |
T142 |
10163 |
95 |
0 |
0 |
T143 |
181709 |
458 |
0 |
0 |
T163 |
180450 |
411 |
0 |
0 |
T164 |
17802 |
65 |
0 |
0 |
T165 |
7251 |
10 |
0 |
0 |
T166 |
9876 |
63 |
0 |
0 |
T167 |
4605 |
7 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7278 |
0 |
0 |
T104 |
8902 |
3 |
0 |
0 |
T133 |
37363 |
252 |
0 |
0 |
T134 |
6466 |
49 |
0 |
0 |
T135 |
113555 |
774 |
0 |
0 |
T138 |
8345 |
14 |
0 |
0 |
T142 |
10163 |
68 |
0 |
0 |
T163 |
180450 |
436 |
0 |
0 |
T164 |
17802 |
56 |
0 |
0 |
T165 |
7251 |
9 |
0 |
0 |
T166 |
9876 |
42 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7284 |
0 |
0 |
T133 |
37363 |
255 |
0 |
0 |
T134 |
6466 |
29 |
0 |
0 |
T135 |
113555 |
740 |
0 |
0 |
T138 |
8345 |
70 |
0 |
0 |
T142 |
10163 |
114 |
0 |
0 |
T163 |
180450 |
461 |
0 |
0 |
T164 |
17802 |
42 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
27 |
0 |
0 |
T167 |
4605 |
50 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7011 |
0 |
0 |
T133 |
37363 |
235 |
0 |
0 |
T134 |
6466 |
16 |
0 |
0 |
T135 |
113555 |
755 |
0 |
0 |
T138 |
8345 |
97 |
0 |
0 |
T142 |
10163 |
164 |
0 |
0 |
T163 |
180450 |
435 |
0 |
0 |
T164 |
17802 |
48 |
0 |
0 |
T165 |
7251 |
32 |
0 |
0 |
T166 |
9876 |
69 |
0 |
0 |
T167 |
4605 |
53 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7078 |
0 |
0 |
T133 |
37363 |
209 |
0 |
0 |
T134 |
6466 |
35 |
0 |
0 |
T135 |
113555 |
795 |
0 |
0 |
T138 |
8345 |
75 |
0 |
0 |
T142 |
10163 |
6 |
0 |
0 |
T163 |
180450 |
483 |
0 |
0 |
T164 |
17802 |
50 |
0 |
0 |
T165 |
7251 |
4 |
0 |
0 |
T166 |
9876 |
36 |
0 |
0 |
T167 |
4605 |
46 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7467 |
0 |
0 |
T133 |
37363 |
237 |
0 |
0 |
T134 |
6466 |
2 |
0 |
0 |
T135 |
113555 |
888 |
0 |
0 |
T138 |
8345 |
65 |
0 |
0 |
T142 |
10163 |
110 |
0 |
0 |
T163 |
180450 |
428 |
0 |
0 |
T164 |
17802 |
49 |
0 |
0 |
T165 |
7251 |
10 |
0 |
0 |
T166 |
9876 |
8 |
0 |
0 |
T167 |
4605 |
65 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7675 |
0 |
0 |
T133 |
37363 |
259 |
0 |
0 |
T134 |
6466 |
17 |
0 |
0 |
T135 |
113555 |
848 |
0 |
0 |
T138 |
8345 |
97 |
0 |
0 |
T142 |
10163 |
169 |
0 |
0 |
T163 |
180450 |
499 |
0 |
0 |
T164 |
17802 |
122 |
0 |
0 |
T165 |
7251 |
43 |
0 |
0 |
T166 |
9876 |
45 |
0 |
0 |
T167 |
4605 |
62 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7104 |
0 |
0 |
T133 |
37363 |
229 |
0 |
0 |
T134 |
6466 |
30 |
0 |
0 |
T135 |
113555 |
844 |
0 |
0 |
T138 |
8345 |
49 |
0 |
0 |
T142 |
10163 |
3 |
0 |
0 |
T163 |
180450 |
425 |
0 |
0 |
T164 |
17802 |
84 |
0 |
0 |
T165 |
7251 |
34 |
0 |
0 |
T166 |
9876 |
8 |
0 |
0 |
T167 |
4605 |
43 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7738 |
0 |
0 |
T133 |
37363 |
241 |
0 |
0 |
T134 |
6466 |
17 |
0 |
0 |
T135 |
113555 |
815 |
0 |
0 |
T138 |
8345 |
38 |
0 |
0 |
T142 |
10163 |
118 |
0 |
0 |
T163 |
180450 |
443 |
0 |
0 |
T164 |
17802 |
55 |
0 |
0 |
T165 |
7251 |
26 |
0 |
0 |
T166 |
9876 |
27 |
0 |
0 |
T167 |
4605 |
7 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7281 |
0 |
0 |
T133 |
37363 |
227 |
0 |
0 |
T134 |
6466 |
35 |
0 |
0 |
T135 |
113555 |
834 |
0 |
0 |
T138 |
8345 |
116 |
0 |
0 |
T142 |
10163 |
180 |
0 |
0 |
T163 |
180450 |
450 |
0 |
0 |
T164 |
17802 |
40 |
0 |
0 |
T165 |
7251 |
3 |
0 |
0 |
T166 |
9876 |
26 |
0 |
0 |
T167 |
4605 |
3 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7515 |
0 |
0 |
T133 |
37363 |
267 |
0 |
0 |
T134 |
6466 |
52 |
0 |
0 |
T135 |
113555 |
811 |
0 |
0 |
T138 |
8345 |
75 |
0 |
0 |
T142 |
10163 |
67 |
0 |
0 |
T143 |
181709 |
411 |
0 |
0 |
T163 |
180450 |
499 |
0 |
0 |
T164 |
17802 |
86 |
0 |
0 |
T165 |
7251 |
17 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7734 |
0 |
0 |
T133 |
37363 |
239 |
0 |
0 |
T134 |
6466 |
23 |
0 |
0 |
T135 |
113555 |
744 |
0 |
0 |
T138 |
8345 |
41 |
0 |
0 |
T142 |
10163 |
121 |
0 |
0 |
T163 |
180450 |
463 |
0 |
0 |
T164 |
17802 |
72 |
0 |
0 |
T165 |
7251 |
23 |
0 |
0 |
T166 |
9876 |
71 |
0 |
0 |
T167 |
4605 |
33 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7551 |
0 |
0 |
T133 |
37363 |
258 |
0 |
0 |
T134 |
6466 |
44 |
0 |
0 |
T135 |
113555 |
855 |
0 |
0 |
T138 |
8345 |
4 |
0 |
0 |
T142 |
10163 |
68 |
0 |
0 |
T163 |
180450 |
448 |
0 |
0 |
T164 |
17802 |
36 |
0 |
0 |
T165 |
7251 |
13 |
0 |
0 |
T166 |
9876 |
10 |
0 |
0 |
T167 |
4605 |
4 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7514 |
0 |
0 |
T133 |
37363 |
223 |
0 |
0 |
T134 |
6466 |
59 |
0 |
0 |
T135 |
113555 |
813 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
169 |
0 |
0 |
T163 |
180450 |
533 |
0 |
0 |
T164 |
17802 |
43 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
38 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7702 |
0 |
0 |
T133 |
37363 |
289 |
0 |
0 |
T134 |
6466 |
7 |
0 |
0 |
T135 |
113555 |
780 |
0 |
0 |
T138 |
8345 |
68 |
0 |
0 |
T142 |
10163 |
135 |
0 |
0 |
T163 |
180450 |
497 |
0 |
0 |
T164 |
17802 |
39 |
0 |
0 |
T165 |
7251 |
18 |
0 |
0 |
T166 |
9876 |
9 |
0 |
0 |
T167 |
4605 |
53 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
6893 |
0 |
0 |
T133 |
37363 |
245 |
0 |
0 |
T134 |
6466 |
41 |
0 |
0 |
T135 |
113555 |
742 |
0 |
0 |
T138 |
8345 |
39 |
0 |
0 |
T142 |
10163 |
86 |
0 |
0 |
T163 |
180450 |
469 |
0 |
0 |
T164 |
17802 |
82 |
0 |
0 |
T165 |
7251 |
8 |
0 |
0 |
T166 |
9876 |
32 |
0 |
0 |
T167 |
4605 |
4 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
7400 |
0 |
0 |
T133 |
37363 |
219 |
0 |
0 |
T134 |
6466 |
32 |
0 |
0 |
T135 |
113555 |
790 |
0 |
0 |
T138 |
8345 |
17 |
0 |
0 |
T142 |
10163 |
50 |
0 |
0 |
T163 |
180450 |
475 |
0 |
0 |
T164 |
17802 |
77 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
64 |
0 |
0 |
T167 |
4605 |
4 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3752 |
0 |
0 |
T133 |
37363 |
226 |
0 |
0 |
T134 |
6466 |
4 |
0 |
0 |
T135 |
113555 |
796 |
0 |
0 |
T138 |
8345 |
10 |
0 |
0 |
T142 |
10163 |
19 |
0 |
0 |
T163 |
180450 |
449 |
0 |
0 |
T164 |
17802 |
78 |
0 |
0 |
T165 |
7251 |
23 |
0 |
0 |
T166 |
9876 |
3 |
0 |
0 |
T167 |
4605 |
6 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3836 |
0 |
0 |
T133 |
37363 |
258 |
0 |
0 |
T134 |
6466 |
4 |
0 |
0 |
T135 |
113555 |
825 |
0 |
0 |
T138 |
8345 |
14 |
0 |
0 |
T142 |
10163 |
25 |
0 |
0 |
T163 |
180450 |
440 |
0 |
0 |
T164 |
17802 |
101 |
0 |
0 |
T165 |
7251 |
7 |
0 |
0 |
T166 |
9876 |
10 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3854 |
0 |
0 |
T108 |
13852 |
1 |
0 |
0 |
T133 |
37363 |
227 |
0 |
0 |
T134 |
6466 |
9 |
0 |
0 |
T135 |
113555 |
820 |
0 |
0 |
T138 |
8345 |
12 |
0 |
0 |
T142 |
10163 |
5 |
0 |
0 |
T163 |
180450 |
460 |
0 |
0 |
T164 |
17802 |
29 |
0 |
0 |
T165 |
7251 |
32 |
0 |
0 |
T166 |
9876 |
10 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3884 |
0 |
0 |
T133 |
37363 |
236 |
0 |
0 |
T135 |
113555 |
712 |
0 |
0 |
T138 |
8345 |
21 |
0 |
0 |
T142 |
10163 |
30 |
0 |
0 |
T143 |
181709 |
505 |
0 |
0 |
T163 |
180450 |
471 |
0 |
0 |
T164 |
17802 |
56 |
0 |
0 |
T165 |
7251 |
27 |
0 |
0 |
T166 |
9876 |
11 |
0 |
0 |
T167 |
4605 |
6 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
4516 |
0 |
0 |
T133 |
37363 |
244 |
0 |
0 |
T134 |
6466 |
5 |
0 |
0 |
T135 |
113555 |
814 |
0 |
0 |
T138 |
8345 |
25 |
0 |
0 |
T142 |
10163 |
20 |
0 |
0 |
T163 |
180450 |
410 |
0 |
0 |
T164 |
17802 |
39 |
0 |
0 |
T165 |
7251 |
30 |
0 |
0 |
T166 |
9876 |
15 |
0 |
0 |
T167 |
4605 |
8 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
6605 |
0 |
0 |
T15 |
6514 |
61 |
0 |
0 |
T16 |
118935 |
0 |
0 |
0 |
T17 |
483762 |
0 |
0 |
0 |
T23 |
609 |
0 |
0 |
0 |
T24 |
7296 |
0 |
0 |
0 |
T25 |
663505 |
0 |
0 |
0 |
T26 |
209401 |
0 |
0 |
0 |
T27 |
2146 |
0 |
0 |
0 |
T28 |
499114 |
0 |
0 |
0 |
T33 |
805 |
0 |
0 |
0 |
T34 |
0 |
6 |
0 |
0 |
T60 |
0 |
23 |
0 |
0 |
T169 |
0 |
20 |
0 |
0 |
T170 |
0 |
33 |
0 |
0 |
T171 |
0 |
51 |
0 |
0 |
T172 |
0 |
22 |
0 |
0 |
T173 |
0 |
40 |
0 |
0 |
T174 |
0 |
18 |
0 |
0 |
T175 |
0 |
66 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3852 |
0 |
0 |
T133 |
37363 |
230 |
0 |
0 |
T135 |
113555 |
743 |
0 |
0 |
T138 |
8345 |
21 |
0 |
0 |
T142 |
10163 |
30 |
0 |
0 |
T143 |
181709 |
468 |
0 |
0 |
T163 |
180450 |
405 |
0 |
0 |
T164 |
17802 |
40 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
18 |
0 |
0 |
T167 |
4605 |
1 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3739 |
0 |
0 |
T104 |
8902 |
1 |
0 |
0 |
T133 |
37363 |
248 |
0 |
0 |
T134 |
6466 |
11 |
0 |
0 |
T135 |
113555 |
795 |
0 |
0 |
T138 |
8345 |
5 |
0 |
0 |
T142 |
10163 |
23 |
0 |
0 |
T163 |
180450 |
424 |
0 |
0 |
T164 |
17802 |
88 |
0 |
0 |
T165 |
7251 |
26 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3592 |
0 |
0 |
T133 |
37363 |
210 |
0 |
0 |
T135 |
113555 |
710 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
8 |
0 |
0 |
T143 |
181709 |
493 |
0 |
0 |
T163 |
180450 |
482 |
0 |
0 |
T164 |
17802 |
103 |
0 |
0 |
T165 |
7251 |
10 |
0 |
0 |
T166 |
9876 |
10 |
0 |
0 |
T167 |
4605 |
7 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3444 |
0 |
0 |
T133 |
37363 |
236 |
0 |
0 |
T134 |
6466 |
8 |
0 |
0 |
T135 |
113555 |
765 |
0 |
0 |
T138 |
8345 |
8 |
0 |
0 |
T142 |
10163 |
15 |
0 |
0 |
T163 |
180450 |
434 |
0 |
0 |
T164 |
17802 |
43 |
0 |
0 |
T165 |
7251 |
48 |
0 |
0 |
T166 |
9876 |
4 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3592 |
0 |
0 |
T133 |
37363 |
231 |
0 |
0 |
T134 |
6466 |
4 |
0 |
0 |
T135 |
113555 |
771 |
0 |
0 |
T138 |
8345 |
1 |
0 |
0 |
T142 |
10163 |
11 |
0 |
0 |
T143 |
181709 |
465 |
0 |
0 |
T163 |
180450 |
465 |
0 |
0 |
T164 |
17802 |
25 |
0 |
0 |
T165 |
7251 |
33 |
0 |
0 |
T166 |
9876 |
4 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3550 |
0 |
0 |
T133 |
37363 |
225 |
0 |
0 |
T134 |
6466 |
5 |
0 |
0 |
T135 |
113555 |
819 |
0 |
0 |
T138 |
8345 |
9 |
0 |
0 |
T142 |
10163 |
16 |
0 |
0 |
T163 |
180450 |
489 |
0 |
0 |
T164 |
17802 |
36 |
0 |
0 |
T165 |
7251 |
29 |
0 |
0 |
T166 |
9876 |
16 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
4649 |
0 |
0 |
T133 |
37363 |
248 |
0 |
0 |
T134 |
6466 |
17 |
0 |
0 |
T135 |
113555 |
801 |
0 |
0 |
T138 |
8345 |
32 |
0 |
0 |
T142 |
10163 |
36 |
0 |
0 |
T163 |
180450 |
481 |
0 |
0 |
T164 |
17802 |
44 |
0 |
0 |
T165 |
7251 |
22 |
0 |
0 |
T166 |
9876 |
8 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3583 |
0 |
0 |
T133 |
37363 |
238 |
0 |
0 |
T134 |
6466 |
5 |
0 |
0 |
T135 |
113555 |
764 |
0 |
0 |
T138 |
8345 |
12 |
0 |
0 |
T142 |
10163 |
8 |
0 |
0 |
T163 |
180450 |
424 |
0 |
0 |
T164 |
17802 |
78 |
0 |
0 |
T165 |
7251 |
15 |
0 |
0 |
T166 |
9876 |
19 |
0 |
0 |
T167 |
4605 |
10 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
4826 |
0 |
0 |
T133 |
37363 |
230 |
0 |
0 |
T134 |
6466 |
8 |
0 |
0 |
T135 |
113555 |
740 |
0 |
0 |
T138 |
8345 |
37 |
0 |
0 |
T142 |
10163 |
45 |
0 |
0 |
T163 |
180450 |
409 |
0 |
0 |
T164 |
17802 |
65 |
0 |
0 |
T165 |
7251 |
28 |
0 |
0 |
T166 |
9876 |
9 |
0 |
0 |
T167 |
4605 |
22 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3699 |
0 |
0 |
T133 |
37363 |
223 |
0 |
0 |
T134 |
6466 |
14 |
0 |
0 |
T135 |
113555 |
792 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
10 |
0 |
0 |
T163 |
180450 |
427 |
0 |
0 |
T164 |
17802 |
83 |
0 |
0 |
T165 |
7251 |
12 |
0 |
0 |
T166 |
9876 |
11 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3578 |
0 |
0 |
T133 |
37363 |
234 |
0 |
0 |
T134 |
6466 |
3 |
0 |
0 |
T135 |
113555 |
759 |
0 |
0 |
T138 |
8345 |
2 |
0 |
0 |
T142 |
10163 |
11 |
0 |
0 |
T143 |
181709 |
475 |
0 |
0 |
T163 |
180450 |
463 |
0 |
0 |
T164 |
17802 |
58 |
0 |
0 |
T166 |
9876 |
6 |
0 |
0 |
T167 |
4605 |
9 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3607 |
0 |
0 |
T133 |
37363 |
243 |
0 |
0 |
T134 |
6466 |
9 |
0 |
0 |
T135 |
113555 |
788 |
0 |
0 |
T138 |
8345 |
3 |
0 |
0 |
T142 |
10163 |
7 |
0 |
0 |
T143 |
181709 |
488 |
0 |
0 |
T163 |
180450 |
454 |
0 |
0 |
T164 |
17802 |
66 |
0 |
0 |
T165 |
7251 |
16 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3564 |
0 |
0 |
T133 |
37363 |
243 |
0 |
0 |
T134 |
6466 |
3 |
0 |
0 |
T135 |
113555 |
808 |
0 |
0 |
T138 |
8345 |
7 |
0 |
0 |
T142 |
10163 |
13 |
0 |
0 |
T163 |
180450 |
486 |
0 |
0 |
T164 |
17802 |
56 |
0 |
0 |
T165 |
7251 |
33 |
0 |
0 |
T166 |
9876 |
14 |
0 |
0 |
T167 |
4605 |
7 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3588 |
0 |
0 |
T133 |
37363 |
248 |
0 |
0 |
T134 |
6466 |
6 |
0 |
0 |
T135 |
113555 |
798 |
0 |
0 |
T138 |
8345 |
6 |
0 |
0 |
T142 |
10163 |
14 |
0 |
0 |
T163 |
180450 |
476 |
0 |
0 |
T164 |
17802 |
80 |
0 |
0 |
T165 |
7251 |
14 |
0 |
0 |
T166 |
9876 |
14 |
0 |
0 |
T167 |
4605 |
4 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3444 |
0 |
0 |
T133 |
37363 |
246 |
0 |
0 |
T134 |
6466 |
10 |
0 |
0 |
T135 |
113555 |
683 |
0 |
0 |
T138 |
8345 |
11 |
0 |
0 |
T142 |
10163 |
13 |
0 |
0 |
T163 |
180450 |
437 |
0 |
0 |
T164 |
17802 |
53 |
0 |
0 |
T165 |
7251 |
27 |
0 |
0 |
T166 |
9876 |
4 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
424186993 |
3779 |
0 |
0 |
T133 |
37363 |
238 |
0 |
0 |
T134 |
6466 |
4 |
0 |
0 |
T135 |
113555 |
815 |
0 |
0 |
T138 |
8345 |
5 |
0 |
0 |
T142 |
10163 |
18 |
0 |
0 |
T163 |
180450 |
445 |
0 |
0 |
T164 |
17802 |
88 |
0 |
0 |
T165 |
7251 |
33 |
0 |
0 |
T166 |
9876 |
10 |
0 |
0 |
T167 |
4605 |
2 |
0 |
0 |