Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
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Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

13 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tpm_access_0 100.00 1 100 1 64 64
tpm_access_1 100.00 1 100 1 64 64
tpm_access_2 100.00 1 100 1 64 64
tpm_access_3 100.00 1 100 1 64 64
tpm_access_4 100.00 1 100 1 64 64
tpm_did_vid 100.00 1 100 1 64 64
tpm_hash_start 100.00 1 100 1 64 64
tpm_int_enable 100.00 1 100 1 64 64
tpm_int_status 100.00 1 100 1 64 64
tpm_int_vector 100.00 1 100 1 64 64
tpm_intf_capability 100.00 1 100 1 64 64
tpm_rid 100.00 1 100 1 64 64
tpm_sts 100.00 1 100 1 64 64




Group Instance : tpm_access_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_access_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_access_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_access_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_access_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_access_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_access_2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_access_2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_access_2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_access_3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_access_3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_access_3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_access_4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_access_4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_access_4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_did_vid
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_did_vid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_did_vid
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_hash_start
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_hash_start

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_hash_start
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_int_enable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_int_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_int_enable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_int_status
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_int_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_int_status
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_int_vector
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_int_vector

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_int_vector
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_intf_capability
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_intf_capability

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_intf_capability
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_rid
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_rid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_rid
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0



Group Instance : tpm_sts
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tpm_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance tpm_sts
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_hit 1 0 1 100.00 100 1 1 0


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 592 1 T26 2 T18 2 T90 2


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 610 1 T5 6 T9 2 T26 4


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 552 1 T5 4 T26 4 T18 2


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 510 1 T5 4 T26 2 T18 2


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 524 1 T5 2 T26 6 T18 4


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2596 1 T5 14 T9 2 T26 18


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2614 1 T5 16 T9 6 T26 4


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2616 1 T5 16 T26 10 T18 14


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2640 1 T5 4 T26 20 T18 6


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2550 1 T5 16 T26 20 T18 12


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
done 4 1 T285 4


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2624 1 T5 8 T26 4 T18 12


Summary for Variable cp_hit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_hit

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
done 2291 1 T5 10 T10 10 T26 14

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