Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3414337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4152494

1

T1

917

T2

7

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4122786	1			T1	61		T2	1		T3	77
values[0x0]	1720677	1			T1	438		T2	4		T5	13863
values[0x1]	1723368	1			T1	463		T2	5		T5	13976

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2424573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5142258

1

T1

926

T2

8

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27232	1			T5	206		T6	22		T8	20
valid_sources[0x01]	26975	1			T5	178		T6	16		T8	20
valid_sources[0x02]	30640	1			T5	192		T6	20		T8	41
valid_sources[0x03]	27845	1			T5	179		T6	27		T7	2
valid_sources[0x04]	29671	1			T2	2		T5	198		T6	91
valid_sources[0x05]	27290	1			T5	188		T6	33		T7	1
valid_sources[0x06]	39959	1			T3	3		T5	228		T6	24
valid_sources[0x07]	27691	1			T5	174		T6	4		T8	15
valid_sources[0x08]	28614	1			T5	192		T6	16		T7	1
valid_sources[0x09]	29148	1			T5	179		T6	10		T8	19
valid_sources[0x0a]	29172	1			T5	202		T6	13		T8	19
valid_sources[0x0b]	25892	1			T5	203		T6	37		T8	36
valid_sources[0x0c]	32952	1			T5	251		T6	20		T8	11
valid_sources[0x0d]	29778	1			T5	244		T6	25		T7	1
valid_sources[0x0e]	30494	1			T5	203		T6	29		T7	2
valid_sources[0x0f]	30021	1			T5	214		T6	25		T8	40
valid_sources[0x10]	26840	1			T5	191		T6	25		T8	19
valid_sources[0x11]	32276	1			T5	201		T6	8		T7	1
valid_sources[0x12]	31047	1			T5	199		T6	18		T7	1
valid_sources[0x13]	29111	1			T5	152		T6	35		T8	17
valid_sources[0x14]	31226	1			T5	184		T6	25		T8	16
valid_sources[0x15]	28420	1			T5	226		T6	27		T8	25
valid_sources[0x16]	27867	1			T5	167		T6	20		T8	27
valid_sources[0x17]	27526	1			T5	204		T6	30		T8	30
valid_sources[0x18]	29661	1			T5	205		T6	31		T7	1
valid_sources[0x19]	26545	1			T5	248		T6	45		T8	36
valid_sources[0x1a]	31711	1			T5	211		T6	11		T8	21
valid_sources[0x1b]	30174	1			T5	207		T6	16		T8	53
valid_sources[0x1c]	35410	1			T5	209		T6	27		T8	20
valid_sources[0x1d]	29924	1			T5	187		T6	40		T8	28
valid_sources[0x1e]	27484	1			T5	193		T6	29		T8	22
valid_sources[0x1f]	27703	1			T5	182		T6	63		T7	1
valid_sources[0x20]	28481	1			T5	170		T6	6		T7	1
valid_sources[0x21]	28227	1			T3	5		T5	179		T6	12
valid_sources[0x22]	29232	1			T5	187		T6	7		T7	2
valid_sources[0x23]	26008	1			T5	213		T6	22		T8	11
valid_sources[0x24]	31615	1			T5	211		T6	38		T8	16
valid_sources[0x25]	27954	1			T5	186		T6	33		T8	26
valid_sources[0x26]	29413	1			T5	178		T6	13		T7	1
valid_sources[0x27]	29111	1			T5	227		T6	33		T8	25
valid_sources[0x28]	29621	1			T5	241		T6	38		T8	23
valid_sources[0x29]	37713	1			T5	195		T6	10		T8	15
valid_sources[0x2a]	28504	1			T5	205		T6	42		T8	31
valid_sources[0x2b]	28991	1			T5	258		T6	6		T8	30
valid_sources[0x2c]	30962	1			T5	227		T6	41		T8	18
valid_sources[0x2d]	26736	1			T5	206		T6	22		T8	28
valid_sources[0x2e]	27617	1			T5	222		T6	30		T8	10
valid_sources[0x2f]	29800	1			T3	2		T5	188		T6	37
valid_sources[0x30]	30639	1			T5	209		T6	51		T8	31
valid_sources[0x31]	29666	1			T5	201		T6	26		T8	18
valid_sources[0x32]	34838	1			T5	210		T6	32		T8	24
valid_sources[0x33]	27606	1			T5	269		T6	13		T8	27
valid_sources[0x34]	28680	1			T5	241		T6	28		T8	25
valid_sources[0x35]	27887	1			T5	208		T6	15		T8	10
valid_sources[0x36]	32252	1			T5	200		T6	18		T8	14
valid_sources[0x37]	29313	1			T3	5		T5	195		T6	18
valid_sources[0x38]	28032	1			T5	183		T6	37		T8	28
valid_sources[0x39]	26108	1			T5	182		T6	18		T8	14
valid_sources[0x3a]	26870	1			T5	229		T6	4		T8	16
valid_sources[0x3b]	26238	1			T5	174		T6	65		T8	32
valid_sources[0x3c]	42192	1			T5	218		T6	38		T8	32
valid_sources[0x3d]	27022	1			T5	194		T6	28		T8	32
valid_sources[0x3e]	26455	1			T5	258		T6	29		T8	24
valid_sources[0x3f]	31098	1			T5	190		T8	23		T9	126
valid_sources[0x40]	30458	1			T5	207		T6	18		T7	1
valid_sources[0x41]	31390	1			T5	182		T6	23		T7	1
valid_sources[0x42]	28125	1			T5	202		T6	19		T8	22
valid_sources[0x43]	27582	1			T5	203		T6	23		T8	29
valid_sources[0x44]	37828	1			T5	211		T6	34		T8	18
valid_sources[0x45]	31185	1			T5	237		T6	32		T7	1
valid_sources[0x46]	31525	1			T5	216		T6	6		T8	39
valid_sources[0x47]	28038	1			T5	216		T6	29		T8	17
valid_sources[0x48]	27638	1			T5	197		T6	21		T7	1
valid_sources[0x49]	26633	1			T5	207		T6	25		T8	26
valid_sources[0x4a]	27456	1			T5	201		T6	11		T8	29
valid_sources[0x4b]	29278	1			T2	1		T5	212		T6	30
valid_sources[0x4c]	32041	1			T5	189		T6	72		T8	17
valid_sources[0x4d]	31974	1			T5	252		T6	23		T8	26
valid_sources[0x4e]	28103	1			T5	173		T6	24		T8	34
valid_sources[0x4f]	30518	1			T5	167		T6	5		T8	18
valid_sources[0x50]	28303	1			T5	192		T6	19		T7	1
valid_sources[0x51]	29443	1			T3	3		T5	250		T6	33
valid_sources[0x52]	31067	1			T5	217		T6	28		T8	16
valid_sources[0x53]	28396	1			T5	204		T6	32		T8	12
valid_sources[0x54]	29021	1			T5	238		T8	26		T9	166
valid_sources[0x55]	28246	1			T3	2		T5	247		T6	11
valid_sources[0x56]	27928	1			T5	212		T6	15		T8	16
valid_sources[0x57]	28313	1			T5	227		T6	14		T7	1
valid_sources[0x58]	28828	1			T5	227		T6	22		T8	28
valid_sources[0x59]	28005	1			T5	225		T6	23		T8	41
valid_sources[0x5a]	28381	1			T5	197		T6	30		T7	1
valid_sources[0x5b]	29802	1			T5	222		T6	20		T8	32
valid_sources[0x5c]	28051	1			T5	224		T6	15		T8	16
valid_sources[0x5d]	26795	1			T5	205		T6	32		T8	14
valid_sources[0x5e]	29945	1			T5	229		T6	28		T8	15
valid_sources[0x5f]	33367	1			T5	168		T6	21		T8	30
valid_sources[0x60]	27954	1			T3	3		T5	193		T6	37
valid_sources[0x61]	25978	1			T3	3		T5	207		T6	32
valid_sources[0x62]	30558	1			T3	8		T4	41		T5	248
valid_sources[0x63]	28368	1			T5	200		T6	20		T7	1
valid_sources[0x64]	26671	1			T5	202		T6	28		T8	16
valid_sources[0x65]	27160	1			T3	1		T5	202		T6	29
valid_sources[0x66]	31005	1			T5	210		T6	25		T8	4
valid_sources[0x67]	27859	1			T5	183		T6	14		T8	20
valid_sources[0x68]	35837	1			T5	230		T6	10		T8	21
valid_sources[0x69]	27518	1			T5	234		T6	17		T7	1
valid_sources[0x6a]	26667	1			T1	23		T5	198		T6	38
valid_sources[0x6b]	27451	1			T5	203		T6	16		T8	37
valid_sources[0x6c]	30225	1			T5	186		T6	36		T8	14
valid_sources[0x6d]	28499	1			T5	178		T6	15		T8	36
valid_sources[0x6e]	25806	1			T5	250		T6	39		T8	37
valid_sources[0x6f]	28212	1			T5	215		T6	12		T8	19
valid_sources[0x70]	29813	1			T5	223		T6	22		T8	23
valid_sources[0x71]	29717	1			T5	192		T6	37		T8	25
valid_sources[0x72]	28251	1			T5	184		T6	21		T7	1
valid_sources[0x73]	31695	1			T5	225		T6	48		T8	10
valid_sources[0x74]	27186	1			T3	1		T5	203		T6	18
valid_sources[0x75]	27304	1			T5	190		T6	48		T8	22
valid_sources[0x76]	27905	1			T5	194		T6	18		T7	1
valid_sources[0x77]	27173	1			T5	187		T6	42		T8	33
valid_sources[0x78]	28711	1			T5	235		T6	17		T8	22
valid_sources[0x79]	26397	1			T5	194		T6	1		T8	32
valid_sources[0x7a]	32178	1			T3	3		T5	242		T6	20
valid_sources[0x7b]	26862	1			T5	207		T6	19		T8	16
valid_sources[0x7c]	28961	1			T5	226		T6	39		T7	1
valid_sources[0x7d]	31582	1			T5	193		T6	9		T7	1
valid_sources[0x7e]	28840	1			T5	212		T6	32		T8	32
valid_sources[0x7f]	35500	1			T5	206		T6	29		T8	21
valid_sources[0x80]	28446	1			T5	191		T6	8		T8	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1020566

1

T1

22

T3

1

T5

3635

values[0x0]

all_enables

biggest_size

1576603

1

T1

436

T2

4

T5

12298

values[0x1]

all_enables

biggest_size

1555325

1

T1

459

T2

3

T5

12018