Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3430015

1

T1

45

T2

3

T3

76

full_word

4151238

1

T1

917

T2

7

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7580843	1			T1	962		T2	10		T3	77
auto[TlIntgErrCmd]	141	1			T98	3		T99	10		T100	7
auto[TlIntgErrData]	137	1			T98	4		T99	11		T100	15
auto[TlIntgErrBoth]	132	1			T98	3		T99	9		T100	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4123763

1

T1

61

T2

1

T3

77

auto[1]

3457490

1

T1

901

T2

9

T5

27839

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3103005	1			T1	39		T2	1		T3	76
auto[TlIntgErrNone]	partial	auto[1]	326632	1			T1	6		T2	2		T5	3523
auto[TlIntgErrNone]	full_word	auto[0]	1020562	1			T1	22		T3	1		T5	3635
auto[TlIntgErrNone]	full_word	auto[1]	3130644	1			T1	895		T2	7		T5	24316
auto[TlIntgErrCmd]	partial	auto[0]	61	1			T99	7		T100	4		T118	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T98	3		T99	3		T100	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T118	2		T119	1		T174	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T175	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	59	1			T98	2		T99	7		T100	8
auto[TlIntgErrData]	partial	auto[1]	64	1			T98	2		T99	2		T100	6
auto[TlIntgErrData]	full_word	auto[0]	11	1			T99	1		T100	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T99	1		T174	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T98	2		T99	7		T100	1
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T98	1		T99	2		T100	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T118	1		T176	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T118	2		T119	2		T174	1