Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	2899497	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	2899497	0	0
T1	4025	1663	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	22472	0	0
T6	139317	1663	0	0
T7	1116	0	0	0
T8	94768	7485	0	0
T9	306225	26654	0	0
T10	5644	0	0	0
T12	0	15801	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	832	0	0
T23	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	3095732	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	3095732	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	28392	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	4992	0	0
T9	306225	35504	0	0
T10	5644	0	0	0
T12	0	9984	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T23	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	182439	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	182439	0	0
T5	198135	2207	0	0
T6	139317	0	0	0
T7	1116	0	0	0
T8	94768	129	0	0
T9	306225	1500	0	0
T10	5644	0	0	0
T11	2326	0	0	0
T12	390821	591	0	0
T13	199590	491	0	0
T23	1700	100	0	0
T24	0	1328	0	0
T25	0	68	0	0
T26	0	980	0	0
T36	0	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	433243	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	433243	0	0
T5	198135	9704	0	0
T6	139317	0	0	0
T7	1116	0	0	0
T8	94768	129	0	0
T9	306225	4609	0	0
T10	5644	0	0	0
T11	2326	0	0	0
T12	390821	591	0	0
T13	199590	2166	0	0
T23	1700	100	0	0
T24	0	1315	0	0
T25	0	68	0	0
T26	0	4375	0	0
T36	0	429	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	5909338	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	5909338	0	0
T1	4025	130	0	0
T2	1160	10	0	0
T3	1697	77	0	0
T4	1255	41	0	0
T5	198135	41700	0	0
T6	139317	5309	0	0
T7	1116	59	0	0
T8	94768	789	0	0
T9	306225	15671	0	0
T10	5644	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	484990045	12198475	0	0
DepthKnown_A	484990045	484858036	0	0
RvalidKnown_A	484990045	484858036	0	0
WreadyKnown_A	484990045	484858036	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	12198475	0	0
T1	4025	130	0	0
T2	1160	10	0	0
T3	1697	77	0	0
T4	1255	41	0	0
T5	198135	166760	0	0
T6	139317	5309	0	0
T7	1116	59	0	0
T8	94768	788	0	0
T9	306225	48234	0	0
T10	5644	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484990045	484858036	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0