Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T13
1	0	Covered	T5,T9,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T9,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	783207650	631446954	0	0
CheckNGreaterZero_A	2928	2928	0	0
GntImpliesReady_A	783207650	3687196	0	0
GntImpliesValid_A	783207650	3687196	0	0
GrantKnown_A	783207650	631446954	0	0
IdxKnown_A	783207650	631446954	0	0
IndexIsCorrect_A	783207650	3687196	0	0
LockArbDecision_A	783207650	0	0	0
NoReadyValidNoGrant_A	783207650	0	0	0
ReadyAndValidImplyGrant_A	783207650	3687196	0	0
ReqAndReadyImplyGrant_A	783207650	3687196	0	0
ReqImpliesValid_A	783207650	3687196	0	0
ReqStaysHighUntilGranted0_M	783207650	0	0	0
RoundRobin_A	783207650	4	0	976
ValidKnown_A	783207650	631446954	0	0
gen_data_port_assertion.DataFlow_A	783207650	3687196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	631446954	0	0
T1	4265	4068	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	1995361	1084273	0	0
T6	228619	183050	0	0
T7	1116	1042	0	0
T8	480708	287285	0	0
T9	587005	751836	0	0
T10	6652	6053	0	0
T11	288	144	0	0
T12	962396	478751	0	0
T13	332072	162724	0	0
T14	73144	36572	0	0
T15	2128	2128	0	0
T16	0	80	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2928	2928	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	631446954	0	0
T1	4265	4068	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	1995361	1084273	0	0
T6	228619	183050	0	0
T7	1116	1042	0	0
T8	480708	287285	0	0
T9	587005	751836	0	0
T10	6652	6053	0	0
T11	288	144	0	0
T12	962396	478751	0	0
T13	332072	162724	0	0
T14	73144	36572	0	0
T15	2128	2128	0	0
T16	0	80	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	631446954	0	0
T1	4265	4068	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	1995361	1084273	0	0
T6	228619	183050	0	0
T7	1116	1042	0	0
T8	480708	287285	0	0
T9	587005	751836	0	0
T10	6652	6053	0	0
T11	288	144	0	0
T12	962396	478751	0	0
T13	332072	162724	0	0
T14	73144	36572	0	0
T15	2128	2128	0	0
T16	0	80	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	4	0	976
T20	860705	1	0	1
T21	116387	0	0	1
T34	2228	0	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	18187	0	0	1
T58	363813	0	0	1
T59	2661	0	0	1
T60	2245	0	0	1
T61	821	0	0	1
T62	1255	0	0	1
T63	226602	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	631446954	0	0
T1	4265	4068	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	1995361	1084273	0	0
T6	228619	183050	0	0
T7	1116	1042	0	0
T8	480708	287285	0	0
T9	587005	751836	0	0
T10	6652	6053	0	0
T11	288	144	0	0
T12	962396	478751	0	0
T13	332072	162724	0	0
T14	73144	36572	0	0
T15	2128	2128	0	0
T16	0	80	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783207650	3687196	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	1995361	30729	0	0
T6	228619	832	0	0
T7	1116	0	0	0
T8	480708	5942	0	0
T9	587005	30998	0	0
T10	6652	0	0	0
T11	288	0	0	0
T12	962396	15360	0	0
T13	332072	5292	0	0
T14	73144	846	0	0
T15	4256	832	0	0
T23	0	200	0	0
T24	0	12016	0	0
T25	0	423	0	0
T26	0	7751	0	0
T27	0	6802	0	0
T28	0	95	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T51	0	2266	0	0
T52	0	5513	0	0
T53	0	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T13
1	0	Covered	T5,T9,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Unreachable
1	1	Covered	T5,T9,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T9,T13
0	0	1	Unreachable
0	0	0	Covered	T5,T9,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150363875	27070701	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150363875	611495	0	0
GntImpliesValid_A	150363875	611495	0	0
GrantKnown_A	150363875	27070701	0	0
IdxKnown_A	150363875	27070701	0	0
IndexIsCorrect_A	150363875	611495	0	0
LockArbDecision_A	150363875	0	0	0
NoReadyValidNoGrant_A	150363875	0	0	0
ReadyAndValidImplyGrant_A	150363875	611495	0	0
ReqAndReadyImplyGrant_A	150363875	611495	0	0
ReqImpliesValid_A	150363875	611495	0	0
ReqStaysHighUntilGranted0_M	150363875	0	0	0
RoundRobin_A	150363875	0	0	0
ValidKnown_A	150363875	27070701	0	0
gen_data_port_assertion.DataFlow_A	150363875	611495	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	27070701	0	0
T5	898613	321656	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	340488	0	0
T10	504	504	0	0
T11	144	144	0	0
T12	481198	0	0	0
T13	166036	117408	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	27070701	0	0
T5	898613	321656	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	340488	0	0
T10	504	504	0	0
T11	144	144	0	0
T12	481198	0	0	0
T13	166036	117408	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	27070701	0	0
T5	898613	321656	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	340488	0	0
T10	504	504	0	0
T11	144	144	0	0
T12	481198	0	0	0
T13	166036	117408	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	27070701	0	0
T5	898613	321656	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	340488	0	0
T10	504	504	0	0
T11	144	144	0	0
T12	481198	0	0	0
T13	166036	117408	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	373016	0	0
T25	0	9688	0	0
T26	0	186080	0	0
T27	0	261944	0	0
T28	0	1592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	611495	0	0
T5	898613	9516	0	0
T6	44651	0	0	0
T8	192970	0	0	0
T9	140390	6285	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	0	0	0
T13	166036	2972	0	0
T14	36572	0	0	0
T15	2128	0	0	0
T24	0	4747	0	0
T25	0	423	0	0
T26	0	3920	0	0
T27	0	6802	0	0
T28	0	95	0	0
T51	0	2266	0	0
T52	0	5513	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150363875	121983103	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	150363875	818373	0	0
GntImpliesValid_A	150363875	818373	0	0
GrantKnown_A	150363875	121983103	0	0
IdxKnown_A	150363875	121983103	0	0
IndexIsCorrect_A	150363875	818373	0	0
LockArbDecision_A	150363875	0	0	0
NoReadyValidNoGrant_A	150363875	0	0	0
ReadyAndValidImplyGrant_A	150363875	818373	0	0
ReqAndReadyImplyGrant_A	150363875	818373	0	0
ReqImpliesValid_A	150363875	818373	0	0
ReqStaysHighUntilGranted0_M	150363875	0	0	0
RoundRobin_A	150363875	0	0	0
ValidKnown_A	150363875	121983103	0	0
gen_data_port_assertion.DataFlow_A	150363875	818373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	121983103	0	0
T1	240	128	0	0
T5	898613	564513	0	0
T6	44651	43796	0	0
T8	192970	192596	0	0
T9	140390	105150	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	478751	0	0
T13	166036	45316	0	0
T14	36572	36572	0	0
T15	0	2128	0	0
T16	0	80	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	121983103	0	0
T1	240	128	0	0
T5	898613	564513	0	0
T6	44651	43796	0	0
T8	192970	192596	0	0
T9	140390	105150	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	478751	0	0
T13	166036	45316	0	0
T14	36572	36572	0	0
T15	0	2128	0	0
T16	0	80	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	121983103	0	0
T1	240	128	0	0
T5	898613	564513	0	0
T6	44651	43796	0	0
T8	192970	192596	0	0
T9	140390	105150	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	478751	0	0
T13	166036	45316	0	0
T14	36572	36572	0	0
T15	0	2128	0	0
T16	0	80	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	121983103	0	0
T1	240	128	0	0
T5	898613	564513	0	0
T6	44651	43796	0	0
T8	192970	192596	0	0
T9	140390	105150	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	478751	0	0
T13	166036	45316	0	0
T14	36572	36572	0	0
T15	0	2128	0	0
T16	0	80	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150363875	818373	0	0
T5	898613	2766	0	0
T6	44651	0	0	0
T8	192970	800	0	0
T9	140390	2952	0	0
T10	504	0	0	0
T11	144	0	0	0
T12	481198	4748	0	0
T13	166036	0	0	0
T14	36572	10	0	0
T15	2128	0	0	0
T24	0	7269	0	0
T26	0	3831	0	0
T36	0	4839	0	0
T48	0	11554	0	0
T53	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	482479900	482393150	0	0
CheckNGreaterZero_A	976	976	0	0
GntImpliesReady_A	482479900	2257328	0	0
GntImpliesValid_A	482479900	2257328	0	0
GrantKnown_A	482479900	482393150	0	0
IdxKnown_A	482479900	482393150	0	0
IndexIsCorrect_A	482479900	2257328	0	0
LockArbDecision_A	482479900	0	0	0
NoReadyValidNoGrant_A	482479900	0	0	0
ReadyAndValidImplyGrant_A	482479900	2257328	0	0
ReqAndReadyImplyGrant_A	482479900	2257328	0	0
ReqImpliesValid_A	482479900	2257328	0	0
ReqStaysHighUntilGranted0_M	482479900	0	0	0
RoundRobin_A	482479900	4	0	976
ValidKnown_A	482479900	482393150	0	0
gen_data_port_assertion.DataFlow_A	482479900	2257328	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	482393150	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976	976	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	482393150	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	482393150	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	4	0	976
T20	860705	1	0	1
T21	116387	0	0	1
T34	2228	0	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	18187	0	0	1
T58	363813	0	0	1
T59	2661	0	0	1
T60	2245	0	0	1
T61	821	0	0	1
T62	1255	0	0	1
T63	226602	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	482393150	0	0
T1	4025	3940	0	0
T2	1160	1079	0	0
T3	1697	1626	0	0
T4	1255	1162	0	0
T5	198135	198104	0	0
T6	139317	139254	0	0
T7	1116	1042	0	0
T8	94768	94689	0	0
T9	306225	306198	0	0
T10	5644	5549	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482479900	2257328	0	0
T1	4025	832	0	0
T2	1160	0	0	0
T3	1697	0	0	0
T4	1255	0	0	0
T5	198135	18447	0	0
T6	139317	832	0	0
T7	1116	0	0	0
T8	94768	5142	0	0
T9	306225	21761	0	0
T10	5644	0	0	0
T12	0	10612	0	0
T13	0	2320	0	0
T14	0	836	0	0
T15	0	832	0	0
T23	0	200	0	0