Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3743409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4254928

1

T1

1228

T2

20908

T3

3847

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4393977	1			T1	675		T2	21342		T3	5948
values[0x0]	1800855	1			T1	444		T2	10477		T3	468
values[0x1]	1803505	1			T1	444		T2	10521		T3	446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2643111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5355226

1

T1

1297

T2

27538

T3

4470

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	36772	1			T1	7		T2	135		T3	30
valid_sources[0x01]	31123	1			T1	4		T2	472		T3	20
valid_sources[0x02]	28724	1			T1	12		T2	50		T3	52
valid_sources[0x03]	33067	1			T1	11		T2	380		T3	21
valid_sources[0x04]	30784	1			T1	5		T2	230		T3	17
valid_sources[0x05]	31104	1			T1	6		T2	787		T3	18
valid_sources[0x06]	30892	1			T1	4		T2	50		T3	20
valid_sources[0x07]	29628	1			T1	2		T2	171		T3	30
valid_sources[0x08]	32950	1			T1	9		T2	23		T3	24
valid_sources[0x09]	28048	1			T1	11		T2	167		T3	16
valid_sources[0x0a]	33059	1			T2	43		T3	31		T5	2
valid_sources[0x0b]	29765	1			T1	3		T2	235		T3	29
valid_sources[0x0c]	28818	1			T1	7		T2	19		T3	26
valid_sources[0x0d]	30927	1			T1	7		T2	228		T3	36
valid_sources[0x0e]	29191	1			T1	9		T2	93		T3	33
valid_sources[0x0f]	28060	1			T1	5		T2	198		T3	30
valid_sources[0x10]	31793	1			T1	9		T2	91		T3	22
valid_sources[0x11]	29174	1			T1	4		T2	9		T3	21
valid_sources[0x12]	29251	1			T1	5		T2	45		T3	31
valid_sources[0x13]	28060	1			T1	5		T2	199		T3	16
valid_sources[0x14]	29347	1			T1	3		T2	723		T3	9
valid_sources[0x15]	30208	1			T1	6		T2	185		T3	21
valid_sources[0x16]	29499	1			T1	4		T2	874		T3	26
valid_sources[0x17]	29189	1			T1	14		T2	296		T3	24
valid_sources[0x18]	26614	1			T1	5		T2	205		T3	30
valid_sources[0x19]	31375	1			T1	2		T2	70		T3	25
valid_sources[0x1a]	29788	1			T1	5		T2	97		T3	52
valid_sources[0x1b]	34428	1			T1	10		T2	124		T3	12
valid_sources[0x1c]	30456	1			T1	8		T2	320		T3	38
valid_sources[0x1d]	38772	1			T1	9		T2	333		T3	26
valid_sources[0x1e]	30115	1			T1	8		T2	61		T3	34
valid_sources[0x1f]	30493	1			T1	1		T2	238		T3	34
valid_sources[0x20]	34781	1			T1	10		T2	209		T3	23
valid_sources[0x21]	36299	1			T1	6		T2	65		T3	34
valid_sources[0x22]	28978	1			T1	5		T2	139		T3	16
valid_sources[0x23]	27506	1			T1	2		T2	120		T3	23
valid_sources[0x24]	27162	1			T1	8		T2	138		T3	14
valid_sources[0x25]	32561	1			T1	3		T2	121		T3	11
valid_sources[0x26]	38009	1			T1	8		T2	167		T3	16
valid_sources[0x27]	28613	1			T1	6		T2	8		T3	29
valid_sources[0x28]	29118	1			T1	9		T2	213		T3	26
valid_sources[0x29]	29076	1			T1	6		T2	526		T3	20
valid_sources[0x2a]	31777	1			T1	1		T2	93		T3	30
valid_sources[0x2b]	29160	1			T1	6		T2	80		T3	26
valid_sources[0x2c]	32405	1			T1	7		T2	120		T3	52
valid_sources[0x2d]	30524	1			T1	6		T2	168		T3	44
valid_sources[0x2e]	29003	1			T1	6		T2	389		T3	35
valid_sources[0x2f]	31582	1			T1	8		T2	138		T3	27
valid_sources[0x30]	29156	1			T1	3		T2	182		T3	17
valid_sources[0x31]	29230	1			T1	6		T2	30		T3	23
valid_sources[0x32]	30416	1			T1	4		T2	20		T3	9
valid_sources[0x33]	31327	1			T1	4		T2	96		T3	23
valid_sources[0x34]	29536	1			T1	2		T2	490		T3	29
valid_sources[0x35]	30777	1			T1	9		T2	247		T3	17
valid_sources[0x36]	32647	1			T1	2		T2	207		T3	24
valid_sources[0x37]	30312	1			T1	3		T2	158		T3	36
valid_sources[0x38]	33356	1			T1	8		T2	10		T3	20
valid_sources[0x39]	31888	1			T1	3		T2	31		T3	23
valid_sources[0x3a]	31754	1			T1	10		T2	198		T3	25
valid_sources[0x3b]	29666	1			T1	9		T2	21		T3	16
valid_sources[0x3c]	35034	1			T1	5		T2	91		T3	17
valid_sources[0x3d]	30505	1			T1	11		T2	219		T3	17
valid_sources[0x3e]	59624	1			T1	9		T2	284		T3	16
valid_sources[0x3f]	28729	1			T1	9		T2	83		T3	24
valid_sources[0x40]	30374	1			T1	5		T2	25		T3	15
valid_sources[0x41]	30021	1			T1	8		T2	153		T3	16
valid_sources[0x42]	32477	1			T1	5		T2	29		T3	33
valid_sources[0x43]	29542	1			T1	6		T2	211		T3	44
valid_sources[0x44]	29888	1			T1	9		T2	129		T3	42
valid_sources[0x45]	27902	1			T1	7		T2	59		T3	47
valid_sources[0x46]	29833	1			T1	3		T2	161		T3	32
valid_sources[0x47]	34909	1			T1	7		T2	312		T3	31
valid_sources[0x48]	38267	1			T1	4		T2	32		T3	42
valid_sources[0x49]	32464	1			T1	4		T2	58		T3	25
valid_sources[0x4a]	29688	1			T1	2		T2	440		T3	22
valid_sources[0x4b]	30176	1			T1	6		T2	131		T3	19
valid_sources[0x4c]	32125	1			T1	4		T2	95		T3	32
valid_sources[0x4d]	35012	1			T1	2		T2	38		T3	34
valid_sources[0x4e]	34038	1			T1	3		T2	189		T3	20
valid_sources[0x4f]	35004	1			T1	5		T2	69		T3	16
valid_sources[0x50]	27693	1			T1	7		T2	339		T3	20
valid_sources[0x51]	28782	1			T1	6		T2	143		T3	22
valid_sources[0x52]	27765	1			T1	7		T2	5		T3	15
valid_sources[0x53]	33196	1			T1	4		T2	107		T3	16
valid_sources[0x54]	27815	1			T1	1		T2	33		T3	27
valid_sources[0x55]	29622	1			T1	4		T2	15		T3	7
valid_sources[0x56]	54853	1			T1	5		T2	10		T3	50
valid_sources[0x57]	30469	1			T1	6		T2	30		T3	24
valid_sources[0x58]	29030	1			T1	3		T2	5		T3	26
valid_sources[0x59]	29886	1			T1	6		T2	3		T3	49
valid_sources[0x5a]	33459	1			T1	7		T2	232		T3	29
valid_sources[0x5b]	30677	1			T1	7		T2	896		T3	15
valid_sources[0x5c]	29357	1			T1	4		T2	133		T3	21
valid_sources[0x5d]	29264	1			T1	7		T2	196		T3	25
valid_sources[0x5e]	28442	1			T1	8		T2	267		T3	20
valid_sources[0x5f]	33508	1			T1	6		T2	627		T3	18
valid_sources[0x60]	30255	1			T1	10		T2	35		T3	12
valid_sources[0x61]	30012	1			T1	3		T2	170		T3	41
valid_sources[0x62]	31348	1			T1	6		T2	144		T3	27
valid_sources[0x63]	28715	1			T1	9		T2	91		T3	31
valid_sources[0x64]	29256	1			T1	4		T2	127		T3	39
valid_sources[0x65]	27536	1			T1	10		T2	132		T3	41
valid_sources[0x66]	28148	1			T1	5		T2	292		T3	19
valid_sources[0x67]	29281	1			T1	9		T2	50		T3	25
valid_sources[0x68]	30628	1			T1	5		T2	295		T3	17
valid_sources[0x69]	31129	1			T1	11		T2	19		T3	29
valid_sources[0x6a]	30296	1			T1	7		T2	62		T3	28
valid_sources[0x6b]	29442	1			T1	5		T2	92		T3	45
valid_sources[0x6c]	28694	1			T1	3		T2	40		T3	37
valid_sources[0x6d]	32485	1			T1	2		T2	96		T3	22
valid_sources[0x6e]	28796	1			T1	2		T2	66		T3	42
valid_sources[0x6f]	30529	1			T1	11		T2	60		T3	31
valid_sources[0x70]	31190	1			T1	4		T2	22		T3	28
valid_sources[0x71]	28569	1			T1	9		T2	149		T3	37
valid_sources[0x72]	29717	1			T1	4		T2	107		T3	33
valid_sources[0x73]	28255	1			T1	5		T2	171		T3	33
valid_sources[0x74]	29555	1			T1	6		T2	157		T3	21
valid_sources[0x75]	29869	1			T1	9		T2	204		T3	39
valid_sources[0x76]	31924	1			T1	14		T2	46		T3	33
valid_sources[0x77]	28334	1			T1	2		T2	23		T3	22
valid_sources[0x78]	29562	1			T1	7		T2	91		T3	22
valid_sources[0x79]	29623	1			T1	6		T2	89		T3	27
valid_sources[0x7a]	38533	1			T1	8		T2	53		T3	21
valid_sources[0x7b]	30952	1			T1	4		T2	216		T3	13
valid_sources[0x7c]	54452	1			T1	3		T2	315		T3	25
valid_sources[0x7d]	28507	1			T1	2		T2	46		T3	43
valid_sources[0x7e]	26443	1			T1	3		T2	36		T3	21
valid_sources[0x7f]	29386	1			T1	5		T2	102		T3	27
valid_sources[0x80]	29605	1			T1	14		T2	161		T3	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

998477

1

T1

350

T2

2694

T3

2939

values[0x0]

all_enables

biggest_size

1639665

1

T1

436

T2

9190

T3

467

values[0x1]

all_enables

biggest_size

1616786

1

T1

442

T2

9024

T3

441