Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3763545

1

T1

335

T2

21432

T3

3015

full_word

4254086

1

T1

1228

T2

20908

T3

3847

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8017221	1			T1	1563		T2	42340		T3	6862
auto[TlIntgErrCmd]	136	1			T93	3		T96	5		T97	10
auto[TlIntgErrData]	159	1			T93	3		T96	9		T97	18
auto[TlIntgErrBoth]	115	1			T93	4		T96	6		T97	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4395817

1

T1

675

T2

21342

T3

5948

auto[1]

3621814

1

T1

888

T2

20998

T3

914

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3397042	1			T1	325		T2	18648		T3	3009
auto[TlIntgErrNone]	partial	auto[1]	366132	1			T1	10		T2	2784		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	998578	1			T1	350		T2	2694		T3	2939
auto[TlIntgErrNone]	full_word	auto[1]	3255469	1			T1	878		T2	18214		T3	908
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T93	1		T96	4		T97	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T93	2		T96	1		T97	6
auto[TlIntgErrCmd]	full_word	auto[0]	10	1			T97	1		T113	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T173	1		T175	3		T176	1
auto[TlIntgErrData]	partial	auto[0]	76	1			T93	2		T96	6		T97	8
auto[TlIntgErrData]	partial	auto[1]	68	1			T93	1		T96	3		T97	7
auto[TlIntgErrData]	full_word	auto[0]	9	1			T97	1		T113	1		T146	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T97	2		T114	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T93	2		T96	3		T97	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T93	2		T96	2		T113	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T114	1		T146	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T96	1		T173	1		T178	1