Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Unreachable
1	1	Covered	T2,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T12
1	0	Covered	T2,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	735139421	590637351	0	0
CheckNGreaterZero_A	2925	2925	0	0
GntImpliesReady_A	735139421	3733746	0	0
GntImpliesValid_A	735139421	3733746	0	0
GrantKnown_A	735139421	590637351	0	0
IdxKnown_A	735139421	590637351	0	0
IndexIsCorrect_A	735139421	3733746	0	0
LockArbDecision_A	735139421	0	0	0
NoReadyValidNoGrant_A	735139421	0	0	0
ReadyAndValidImplyGrant_A	735139421	3733746	0	0
ReqAndReadyImplyGrant_A	735139421	3733746	0	0
ReqImpliesValid_A	735139421	3733746	0	0
ReqStaysHighUntilGranted0_M	735139421	0	0	0
RoundRobin_A	735139421	4	0	975
ValidKnown_A	735139421	590637351	0	0
gen_data_port_assertion.DataFlow_A	735139421	3733746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	590637351	0	0
T1	40845	40363	0	0
T2	1233908	689113	0	0
T3	420465	281354	0	0
T4	2429	2339	0	0
T5	817583	717244	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	315399	274028	0	0
T9	4238	3360	0	0
T10	1847	1758	0	0
T11	8354	4177	0	0
T12	1643698	810216	0	0
T14	54542	25584	0	0
T15	77292	36232	0	0
T16	32935	32550	0	0
T17	0	108048	0	0
T18	0	81566	0	0
T19	0	97968	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	590637351	0	0
T1	40845	40363	0	0
T2	1233908	689113	0	0
T3	420465	281354	0	0
T4	2429	2339	0	0
T5	817583	717244	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	315399	274028	0	0
T9	4238	3360	0	0
T10	1847	1758	0	0
T11	8354	4177	0	0
T12	1643698	810216	0	0
T14	54542	25584	0	0
T15	77292	36232	0	0
T16	32935	32550	0	0
T17	0	108048	0	0
T18	0	81566	0	0
T19	0	97968	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	590637351	0	0
T1	40845	40363	0	0
T2	1233908	689113	0	0
T3	420465	281354	0	0
T4	2429	2339	0	0
T5	817583	717244	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	315399	274028	0	0
T9	4238	3360	0	0
T10	1847	1758	0	0
T11	8354	4177	0	0
T12	1643698	810216	0	0
T14	54542	25584	0	0
T15	77292	36232	0	0
T16	32935	32550	0	0
T17	0	108048	0	0
T18	0	81566	0	0
T19	0	97968	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	4	0	975
T49	683913	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	8780	0	0	1
T54	1184	0	0	1
T55	4699	0	0	1
T56	391486	0	0	1
T57	426231	0	0	1
T58	112382	0	0	1
T59	208993	0	0	1
T60	1712	0	0	1
T61	3085	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	590637351	0	0
T1	40845	40363	0	0
T2	1233908	689113	0	0
T3	420465	281354	0	0
T4	2429	2339	0	0
T5	817583	717244	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	315399	274028	0	0
T9	4238	3360	0	0
T10	1847	1758	0	0
T11	8354	4177	0	0
T12	1643698	810216	0	0
T14	54542	25584	0	0
T15	77292	36232	0	0
T16	32935	32550	0	0
T17	0	108048	0	0
T18	0	81566	0	0
T19	0	97968	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735139421	3733746	0	0
T1	28228	832	0	0
T2	1233908	21002	0	0
T3	420465	832	0	0
T4	2429	200	0	0
T5	817583	1672	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	315399	2359	0	0
T9	4238	0	0	0
T10	1847	0	0	0
T11	8354	832	0	0
T12	1643698	38036	0	0
T14	54542	0	0	0
T15	77292	1139	0	0
T16	65870	3182	0	0
T17	0	1043	0	0
T20	0	19853	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	6041	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	5796	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Unreachable
1	1	Covered	T2,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143090342	26591039	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	143090342	628736	0	0
GntImpliesValid_A	143090342	628736	0	0
GrantKnown_A	143090342	26591039	0	0
IdxKnown_A	143090342	26591039	0	0
IndexIsCorrect_A	143090342	628736	0	0
LockArbDecision_A	143090342	0	0	0
NoReadyValidNoGrant_A	143090342	0	0	0
ReadyAndValidImplyGrant_A	143090342	628736	0	0
ReqAndReadyImplyGrant_A	143090342	628736	0	0
ReqImpliesValid_A	143090342	628736	0	0
ReqStaysHighUntilGranted0_M	143090342	0	0	0
RoundRobin_A	143090342	0	0	0
ValidKnown_A	143090342	26591039	0	0
gen_data_port_assertion.DataFlow_A	143090342	628736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	26591039	0	0
T2	532646	132312	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	37776	0	0
T9	792	792	0	0
T11	4177	0	0	0
T12	821849	233000	0	0
T14	27271	25584	0	0
T15	38646	36232	0	0
T16	32935	0	0	0
T17	0	5728	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	26591039	0	0
T2	532646	132312	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	37776	0	0
T9	792	792	0	0
T11	4177	0	0	0
T12	821849	233000	0	0
T14	27271	25584	0	0
T15	38646	36232	0	0
T16	32935	0	0	0
T17	0	5728	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	26591039	0	0
T2	532646	132312	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	37776	0	0
T9	792	792	0	0
T11	4177	0	0	0
T12	821849	233000	0	0
T14	27271	25584	0	0
T15	38646	36232	0	0
T16	32935	0	0	0
T17	0	5728	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	26591039	0	0
T2	532646	132312	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	37776	0	0
T9	792	792	0	0
T11	4177	0	0	0
T12	821849	233000	0	0
T14	27271	25584	0	0
T15	38646	36232	0	0
T16	32935	0	0	0
T17	0	5728	0	0
T25	0	14896	0	0
T27	0	2792	0	0
T28	0	93664	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	628736	0	0
T2	532646	5177	0	0
T3	139028	0	0	0
T5	99390	0	0	0
T8	39526	1544	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	9168	0	0
T14	27271	0	0	0
T15	38646	1139	0	0
T16	32935	0	0	0
T17	0	229	0	0
T20	0	9130	0	0
T25	0	389	0	0
T27	0	189	0	0
T28	0	4351	0	0
T48	0	3472	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T12
1	0	Covered	T2,T5,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T5,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143090342	115176457	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	143090342	853093	0	0
GntImpliesValid_A	143090342	853093	0	0
GrantKnown_A	143090342	115176457	0	0
IdxKnown_A	143090342	115176457	0	0
IndexIsCorrect_A	143090342	853093	0	0
LockArbDecision_A	143090342	0	0	0
NoReadyValidNoGrant_A	143090342	0	0	0
ReadyAndValidImplyGrant_A	143090342	853093	0	0
ReqAndReadyImplyGrant_A	143090342	853093	0	0
ReqImpliesValid_A	143090342	853093	0	0
ReqStaysHighUntilGranted0_M	143090342	0	0	0
RoundRobin_A	143090342	0	0	0
ValidKnown_A	143090342	115176457	0	0
gen_data_port_assertion.DataFlow_A	143090342	853093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	115176457	0	0
T1	12617	12224	0	0
T2	532646	388192	0	0
T3	139028	139028	0	0
T5	99390	98504	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	4177	0	0
T12	821849	577216	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	0	32550	0	0
T17	0	102320	0	0
T18	0	81566	0	0
T19	0	97968	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	115176457	0	0
T1	12617	12224	0	0
T2	532646	388192	0	0
T3	139028	139028	0	0
T5	99390	98504	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	4177	0	0
T12	821849	577216	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	0	32550	0	0
T17	0	102320	0	0
T18	0	81566	0	0
T19	0	97968	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	115176457	0	0
T1	12617	12224	0	0
T2	532646	388192	0	0
T3	139028	139028	0	0
T5	99390	98504	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	4177	0	0
T12	821849	577216	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	0	32550	0	0
T17	0	102320	0	0
T18	0	81566	0	0
T19	0	97968	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	115176457	0	0
T1	12617	12224	0	0
T2	532646	388192	0	0
T3	139028	139028	0	0
T5	99390	98504	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	4177	0	0
T12	821849	577216	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	0	32550	0	0
T17	0	102320	0	0
T18	0	81566	0	0
T19	0	97968	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143090342	853093	0	0
T2	532646	3988	0	0
T3	139028	0	0	0
T5	99390	4	0	0
T8	39526	0	0	0
T9	792	0	0	0
T11	4177	0	0	0
T12	821849	10293	0	0
T14	27271	0	0	0
T15	38646	0	0	0
T16	32935	3182	0	0
T17	0	814	0	0
T20	0	10723	0	0
T28	0	1690	0	0
T41	0	4	0	0
T43	0	14	0	0
T48	0	2324	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	448958737	448869855	0	0
CheckNGreaterZero_A	975	975	0	0
GntImpliesReady_A	448958737	2251917	0	0
GntImpliesValid_A	448958737	2251917	0	0
GrantKnown_A	448958737	448869855	0	0
IdxKnown_A	448958737	448869855	0	0
IndexIsCorrect_A	448958737	2251917	0	0
LockArbDecision_A	448958737	0	0	0
NoReadyValidNoGrant_A	448958737	0	0	0
ReadyAndValidImplyGrant_A	448958737	2251917	0	0
ReqAndReadyImplyGrant_A	448958737	2251917	0	0
ReqImpliesValid_A	448958737	2251917	0	0
ReqStaysHighUntilGranted0_M	448958737	0	0	0
RoundRobin_A	448958737	4	0	975
ValidKnown_A	448958737	448869855	0	0
gen_data_port_assertion.DataFlow_A	448958737	2251917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	448869855	0	0
T1	28228	28139	0	0
T2	168616	168609	0	0
T3	142409	142326	0	0
T4	2429	2339	0	0
T5	618803	618740	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	236347	236252	0	0
T9	2654	2568	0	0
T10	1847	1758	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	975	975	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	448869855	0	0
T1	28228	28139	0	0
T2	168616	168609	0	0
T3	142409	142326	0	0
T4	2429	2339	0	0
T5	618803	618740	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	236347	236252	0	0
T9	2654	2568	0	0
T10	1847	1758	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	448869855	0	0
T1	28228	28139	0	0
T2	168616	168609	0	0
T3	142409	142326	0	0
T4	2429	2339	0	0
T5	618803	618740	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	236347	236252	0	0
T9	2654	2568	0	0
T10	1847	1758	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	4	0	975
T49	683913	1	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	8780	0	0	1
T54	1184	0	0	1
T55	4699	0	0	1
T56	391486	0	0	1
T57	426231	0	0	1
T58	112382	0	0	1
T59	208993	0	0	1
T60	1712	0	0	1
T61	3085	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	448869855	0	0
T1	28228	28139	0	0
T2	168616	168609	0	0
T3	142409	142326	0	0
T4	2429	2339	0	0
T5	618803	618740	0	0
T6	1509	1440	0	0
T7	2529	2474	0	0
T8	236347	236252	0	0
T9	2654	2568	0	0
T10	1847	1758	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448958737	2251917	0	0
T1	28228	832	0	0
T2	168616	11837	0	0
T3	142409	832	0	0
T4	2429	200	0	0
T5	618803	1668	0	0
T6	1509	200	0	0
T7	2529	832	0	0
T8	236347	815	0	0
T9	2654	0	0	0
T10	1847	0	0	0
T11	0	832	0	0
T12	0	18575	0	0