Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
3868 |
0 |
0 |
T92 |
3315 |
104 |
0 |
0 |
T94 |
5917 |
242 |
0 |
0 |
T95 |
7436 |
155 |
0 |
0 |
T96 |
52447 |
2 |
0 |
0 |
T97 |
105311 |
3 |
0 |
0 |
T105 |
13783 |
134 |
0 |
0 |
T111 |
7947 |
5 |
0 |
0 |
T112 |
5582 |
1 |
0 |
0 |
T113 |
28805 |
1 |
0 |
0 |
T114 |
26213 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1548 |
0 |
0 |
T97 |
105311 |
128 |
0 |
0 |
T110 |
14311 |
16 |
0 |
0 |
T118 |
9476 |
11 |
0 |
0 |
T120 |
11266 |
8 |
0 |
0 |
T121 |
3372 |
8 |
0 |
0 |
T139 |
11756 |
14 |
0 |
0 |
T145 |
13400 |
56 |
0 |
0 |
T146 |
102637 |
107 |
0 |
0 |
T147 |
78714 |
128 |
0 |
0 |
T148 |
101817 |
108 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1599 |
0 |
0 |
T97 |
105311 |
117 |
0 |
0 |
T110 |
14311 |
13 |
0 |
0 |
T118 |
9476 |
12 |
0 |
0 |
T120 |
11266 |
18 |
0 |
0 |
T121 |
3372 |
6 |
0 |
0 |
T139 |
11756 |
29 |
0 |
0 |
T145 |
13400 |
24 |
0 |
0 |
T146 |
102637 |
122 |
0 |
0 |
T147 |
78714 |
139 |
0 |
0 |
T148 |
101817 |
100 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2536 |
0 |
0 |
T97 |
105311 |
211 |
0 |
0 |
T110 |
14311 |
11 |
0 |
0 |
T118 |
9476 |
21 |
0 |
0 |
T120 |
11266 |
20 |
0 |
0 |
T139 |
11756 |
41 |
0 |
0 |
T145 |
13400 |
29 |
0 |
0 |
T146 |
102637 |
170 |
0 |
0 |
T147 |
78714 |
119 |
0 |
0 |
T148 |
101817 |
202 |
0 |
0 |
T149 |
11026 |
36 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
14673 |
0 |
0 |
T97 |
105311 |
1725 |
0 |
0 |
T110 |
14311 |
141 |
0 |
0 |
T118 |
9476 |
253 |
0 |
0 |
T120 |
11266 |
131 |
0 |
0 |
T121 |
3372 |
66 |
0 |
0 |
T139 |
11756 |
60 |
0 |
0 |
T145 |
13400 |
17 |
0 |
0 |
T146 |
102637 |
2125 |
0 |
0 |
T147 |
78714 |
125 |
0 |
0 |
T148 |
101817 |
1804 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
15045 |
0 |
0 |
T97 |
105311 |
1786 |
0 |
0 |
T110 |
14311 |
159 |
0 |
0 |
T118 |
9476 |
8 |
0 |
0 |
T120 |
11266 |
233 |
0 |
0 |
T121 |
3372 |
73 |
0 |
0 |
T139 |
11756 |
24 |
0 |
0 |
T145 |
13400 |
19 |
0 |
0 |
T146 |
102637 |
1590 |
0 |
0 |
T147 |
78714 |
128 |
0 |
0 |
T148 |
101817 |
1873 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
14247 |
0 |
0 |
T97 |
105311 |
1612 |
0 |
0 |
T110 |
14311 |
178 |
0 |
0 |
T118 |
9476 |
9 |
0 |
0 |
T120 |
11266 |
111 |
0 |
0 |
T121 |
3372 |
2 |
0 |
0 |
T139 |
11756 |
35 |
0 |
0 |
T145 |
13400 |
63 |
0 |
0 |
T146 |
102637 |
1952 |
0 |
0 |
T147 |
78714 |
93 |
0 |
0 |
T148 |
101817 |
2292 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
15238 |
0 |
0 |
T97 |
105311 |
2264 |
0 |
0 |
T110 |
14311 |
80 |
0 |
0 |
T118 |
9476 |
93 |
0 |
0 |
T120 |
11266 |
290 |
0 |
0 |
T121 |
3372 |
53 |
0 |
0 |
T139 |
11756 |
49 |
0 |
0 |
T145 |
13400 |
20 |
0 |
0 |
T146 |
102637 |
2105 |
0 |
0 |
T147 |
78714 |
86 |
0 |
0 |
T148 |
101817 |
1874 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
16657 |
0 |
0 |
T97 |
105311 |
2147 |
0 |
0 |
T110 |
14311 |
233 |
0 |
0 |
T118 |
9476 |
164 |
0 |
0 |
T120 |
11266 |
232 |
0 |
0 |
T139 |
11756 |
41 |
0 |
0 |
T145 |
13400 |
42 |
0 |
0 |
T146 |
102637 |
2586 |
0 |
0 |
T147 |
78714 |
149 |
0 |
0 |
T148 |
101817 |
2251 |
0 |
0 |
T149 |
11026 |
315 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
14916 |
0 |
0 |
T97 |
105311 |
1813 |
0 |
0 |
T110 |
14311 |
67 |
0 |
0 |
T118 |
9476 |
296 |
0 |
0 |
T120 |
11266 |
215 |
0 |
0 |
T139 |
11756 |
10 |
0 |
0 |
T145 |
13400 |
108 |
0 |
0 |
T146 |
102637 |
2081 |
0 |
0 |
T147 |
78714 |
117 |
0 |
0 |
T148 |
101817 |
1847 |
0 |
0 |
T149 |
11026 |
10 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
16454 |
0 |
0 |
T97 |
105311 |
1803 |
0 |
0 |
T110 |
14311 |
73 |
0 |
0 |
T118 |
9476 |
96 |
0 |
0 |
T120 |
11266 |
285 |
0 |
0 |
T121 |
3372 |
30 |
0 |
0 |
T139 |
11756 |
37 |
0 |
0 |
T145 |
13400 |
44 |
0 |
0 |
T146 |
102637 |
2141 |
0 |
0 |
T147 |
78714 |
134 |
0 |
0 |
T148 |
101817 |
1974 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
15450 |
0 |
0 |
T97 |
105311 |
1936 |
0 |
0 |
T110 |
14311 |
70 |
0 |
0 |
T118 |
9476 |
91 |
0 |
0 |
T120 |
11266 |
159 |
0 |
0 |
T121 |
3372 |
10 |
0 |
0 |
T139 |
11756 |
31 |
0 |
0 |
T145 |
13400 |
17 |
0 |
0 |
T146 |
102637 |
1794 |
0 |
0 |
T147 |
78714 |
144 |
0 |
0 |
T148 |
101817 |
1916 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7208 |
0 |
0 |
T97 |
105311 |
636 |
0 |
0 |
T110 |
14311 |
110 |
0 |
0 |
T118 |
9476 |
72 |
0 |
0 |
T120 |
11266 |
56 |
0 |
0 |
T121 |
3372 |
24 |
0 |
0 |
T139 |
11756 |
23 |
0 |
0 |
T145 |
13400 |
43 |
0 |
0 |
T146 |
102637 |
813 |
0 |
0 |
T147 |
78714 |
84 |
0 |
0 |
T148 |
101817 |
749 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7001 |
0 |
0 |
T97 |
105311 |
785 |
0 |
0 |
T110 |
14311 |
33 |
0 |
0 |
T118 |
9476 |
95 |
0 |
0 |
T120 |
11266 |
181 |
0 |
0 |
T121 |
3372 |
8 |
0 |
0 |
T139 |
11756 |
24 |
0 |
0 |
T145 |
13400 |
23 |
0 |
0 |
T146 |
102637 |
888 |
0 |
0 |
T147 |
78714 |
147 |
0 |
0 |
T148 |
101817 |
550 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6063 |
0 |
0 |
T97 |
105311 |
681 |
0 |
0 |
T110 |
14311 |
74 |
0 |
0 |
T118 |
9476 |
87 |
0 |
0 |
T120 |
11266 |
87 |
0 |
0 |
T121 |
3372 |
23 |
0 |
0 |
T139 |
11756 |
20 |
0 |
0 |
T145 |
13400 |
25 |
0 |
0 |
T146 |
102637 |
953 |
0 |
0 |
T147 |
78714 |
142 |
0 |
0 |
T148 |
101817 |
623 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6639 |
0 |
0 |
T97 |
105311 |
724 |
0 |
0 |
T110 |
14311 |
52 |
0 |
0 |
T118 |
9476 |
64 |
0 |
0 |
T120 |
11266 |
69 |
0 |
0 |
T139 |
11756 |
21 |
0 |
0 |
T145 |
13400 |
32 |
0 |
0 |
T146 |
102637 |
950 |
0 |
0 |
T147 |
78714 |
164 |
0 |
0 |
T148 |
101817 |
853 |
0 |
0 |
T149 |
11026 |
10 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7153 |
0 |
0 |
T97 |
105311 |
685 |
0 |
0 |
T110 |
14311 |
80 |
0 |
0 |
T118 |
9476 |
13 |
0 |
0 |
T120 |
11266 |
108 |
0 |
0 |
T139 |
11756 |
29 |
0 |
0 |
T145 |
13400 |
35 |
0 |
0 |
T146 |
102637 |
944 |
0 |
0 |
T147 |
78714 |
171 |
0 |
0 |
T148 |
101817 |
824 |
0 |
0 |
T149 |
11026 |
70 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7337 |
0 |
0 |
T97 |
105311 |
811 |
0 |
0 |
T110 |
14311 |
80 |
0 |
0 |
T118 |
9476 |
43 |
0 |
0 |
T120 |
11266 |
75 |
0 |
0 |
T121 |
3372 |
10 |
0 |
0 |
T139 |
11756 |
14 |
0 |
0 |
T145 |
13400 |
57 |
0 |
0 |
T146 |
102637 |
868 |
0 |
0 |
T147 |
78714 |
112 |
0 |
0 |
T148 |
101817 |
1025 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6773 |
0 |
0 |
T97 |
105311 |
709 |
0 |
0 |
T110 |
14311 |
12 |
0 |
0 |
T118 |
9476 |
42 |
0 |
0 |
T120 |
11266 |
162 |
0 |
0 |
T121 |
3372 |
23 |
0 |
0 |
T139 |
11756 |
42 |
0 |
0 |
T145 |
13400 |
21 |
0 |
0 |
T146 |
102637 |
941 |
0 |
0 |
T147 |
78714 |
149 |
0 |
0 |
T148 |
101817 |
754 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7380 |
0 |
0 |
T97 |
105311 |
669 |
0 |
0 |
T110 |
14311 |
48 |
0 |
0 |
T118 |
9476 |
83 |
0 |
0 |
T120 |
11266 |
113 |
0 |
0 |
T121 |
3372 |
4 |
0 |
0 |
T139 |
11756 |
24 |
0 |
0 |
T145 |
13400 |
31 |
0 |
0 |
T146 |
102637 |
942 |
0 |
0 |
T147 |
78714 |
116 |
0 |
0 |
T148 |
101817 |
769 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6873 |
0 |
0 |
T97 |
105311 |
697 |
0 |
0 |
T110 |
14311 |
51 |
0 |
0 |
T118 |
9476 |
115 |
0 |
0 |
T120 |
11266 |
51 |
0 |
0 |
T121 |
3372 |
8 |
0 |
0 |
T139 |
11756 |
27 |
0 |
0 |
T145 |
13400 |
43 |
0 |
0 |
T146 |
102637 |
655 |
0 |
0 |
T147 |
78714 |
117 |
0 |
0 |
T148 |
101817 |
911 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6439 |
0 |
0 |
T97 |
105311 |
493 |
0 |
0 |
T110 |
14311 |
71 |
0 |
0 |
T118 |
9476 |
136 |
0 |
0 |
T120 |
11266 |
105 |
0 |
0 |
T121 |
3372 |
25 |
0 |
0 |
T139 |
11756 |
23 |
0 |
0 |
T145 |
13400 |
57 |
0 |
0 |
T146 |
102637 |
876 |
0 |
0 |
T147 |
78714 |
163 |
0 |
0 |
T148 |
101817 |
719 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7146 |
0 |
0 |
T97 |
105311 |
911 |
0 |
0 |
T110 |
14311 |
62 |
0 |
0 |
T118 |
9476 |
58 |
0 |
0 |
T120 |
11266 |
4 |
0 |
0 |
T121 |
3372 |
2 |
0 |
0 |
T139 |
11756 |
37 |
0 |
0 |
T145 |
13400 |
4 |
0 |
0 |
T146 |
102637 |
991 |
0 |
0 |
T147 |
78714 |
134 |
0 |
0 |
T148 |
101817 |
905 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6898 |
0 |
0 |
T97 |
105311 |
707 |
0 |
0 |
T110 |
14311 |
96 |
0 |
0 |
T118 |
9476 |
72 |
0 |
0 |
T120 |
11266 |
45 |
0 |
0 |
T121 |
3372 |
19 |
0 |
0 |
T139 |
11756 |
18 |
0 |
0 |
T145 |
13400 |
25 |
0 |
0 |
T146 |
102637 |
751 |
0 |
0 |
T147 |
78714 |
123 |
0 |
0 |
T148 |
101817 |
985 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6583 |
0 |
0 |
T97 |
105311 |
792 |
0 |
0 |
T110 |
14311 |
66 |
0 |
0 |
T118 |
9476 |
13 |
0 |
0 |
T120 |
11266 |
4 |
0 |
0 |
T139 |
11756 |
32 |
0 |
0 |
T145 |
13400 |
42 |
0 |
0 |
T146 |
102637 |
784 |
0 |
0 |
T147 |
78714 |
115 |
0 |
0 |
T148 |
101817 |
852 |
0 |
0 |
T149 |
11026 |
56 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7134 |
0 |
0 |
T97 |
105311 |
850 |
0 |
0 |
T110 |
14311 |
49 |
0 |
0 |
T118 |
9476 |
52 |
0 |
0 |
T120 |
11266 |
70 |
0 |
0 |
T121 |
3372 |
28 |
0 |
0 |
T139 |
11756 |
4 |
0 |
0 |
T145 |
13400 |
5 |
0 |
0 |
T146 |
102637 |
653 |
0 |
0 |
T147 |
78714 |
111 |
0 |
0 |
T148 |
101817 |
1004 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7532 |
0 |
0 |
T97 |
105311 |
847 |
0 |
0 |
T110 |
14311 |
24 |
0 |
0 |
T118 |
9476 |
48 |
0 |
0 |
T120 |
11266 |
70 |
0 |
0 |
T121 |
3372 |
29 |
0 |
0 |
T139 |
11756 |
37 |
0 |
0 |
T145 |
13400 |
38 |
0 |
0 |
T146 |
102637 |
974 |
0 |
0 |
T147 |
78714 |
134 |
0 |
0 |
T148 |
101817 |
880 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6576 |
0 |
0 |
T97 |
105311 |
886 |
0 |
0 |
T110 |
14311 |
51 |
0 |
0 |
T118 |
9476 |
62 |
0 |
0 |
T120 |
11266 |
94 |
0 |
0 |
T121 |
3372 |
34 |
0 |
0 |
T139 |
11756 |
26 |
0 |
0 |
T145 |
13400 |
26 |
0 |
0 |
T146 |
102637 |
652 |
0 |
0 |
T147 |
78714 |
165 |
0 |
0 |
T148 |
101817 |
646 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
5965 |
0 |
0 |
T97 |
105311 |
723 |
0 |
0 |
T110 |
14311 |
35 |
0 |
0 |
T118 |
9476 |
54 |
0 |
0 |
T120 |
11266 |
43 |
0 |
0 |
T139 |
11756 |
18 |
0 |
0 |
T145 |
13400 |
11 |
0 |
0 |
T146 |
102637 |
594 |
0 |
0 |
T147 |
78714 |
117 |
0 |
0 |
T148 |
101817 |
723 |
0 |
0 |
T149 |
11026 |
58 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6410 |
0 |
0 |
T97 |
105311 |
709 |
0 |
0 |
T110 |
14311 |
55 |
0 |
0 |
T118 |
9476 |
114 |
0 |
0 |
T120 |
11266 |
54 |
0 |
0 |
T121 |
3372 |
59 |
0 |
0 |
T139 |
11756 |
46 |
0 |
0 |
T145 |
13400 |
61 |
0 |
0 |
T146 |
102637 |
701 |
0 |
0 |
T147 |
78714 |
139 |
0 |
0 |
T148 |
101817 |
776 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7020 |
0 |
0 |
T97 |
105311 |
788 |
0 |
0 |
T110 |
14311 |
30 |
0 |
0 |
T118 |
9476 |
68 |
0 |
0 |
T120 |
11266 |
63 |
0 |
0 |
T121 |
3372 |
1 |
0 |
0 |
T139 |
11756 |
23 |
0 |
0 |
T145 |
13400 |
64 |
0 |
0 |
T146 |
102637 |
927 |
0 |
0 |
T147 |
78714 |
148 |
0 |
0 |
T148 |
101817 |
1044 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7184 |
0 |
0 |
T97 |
105311 |
1001 |
0 |
0 |
T110 |
14311 |
76 |
0 |
0 |
T118 |
9476 |
41 |
0 |
0 |
T120 |
11266 |
108 |
0 |
0 |
T139 |
11756 |
21 |
0 |
0 |
T145 |
13400 |
49 |
0 |
0 |
T146 |
102637 |
756 |
0 |
0 |
T147 |
78714 |
198 |
0 |
0 |
T148 |
101817 |
829 |
0 |
0 |
T149 |
11026 |
16 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6884 |
0 |
0 |
T97 |
105311 |
902 |
0 |
0 |
T110 |
14311 |
59 |
0 |
0 |
T118 |
9476 |
79 |
0 |
0 |
T120 |
11266 |
184 |
0 |
0 |
T121 |
3372 |
5 |
0 |
0 |
T139 |
11756 |
24 |
0 |
0 |
T145 |
13400 |
38 |
0 |
0 |
T146 |
102637 |
561 |
0 |
0 |
T147 |
78714 |
139 |
0 |
0 |
T148 |
101817 |
821 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7137 |
0 |
0 |
T97 |
105311 |
835 |
0 |
0 |
T110 |
14311 |
48 |
0 |
0 |
T118 |
9476 |
114 |
0 |
0 |
T120 |
11266 |
98 |
0 |
0 |
T139 |
11756 |
7 |
0 |
0 |
T145 |
13400 |
55 |
0 |
0 |
T146 |
102637 |
738 |
0 |
0 |
T147 |
78714 |
136 |
0 |
0 |
T148 |
101817 |
905 |
0 |
0 |
T149 |
11026 |
113 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
6593 |
0 |
0 |
T97 |
105311 |
749 |
0 |
0 |
T110 |
14311 |
55 |
0 |
0 |
T118 |
9476 |
56 |
0 |
0 |
T120 |
11266 |
95 |
0 |
0 |
T121 |
3372 |
10 |
0 |
0 |
T139 |
11756 |
24 |
0 |
0 |
T145 |
13400 |
34 |
0 |
0 |
T146 |
102637 |
832 |
0 |
0 |
T147 |
78714 |
99 |
0 |
0 |
T148 |
101817 |
751 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
7283 |
0 |
0 |
T97 |
105311 |
588 |
0 |
0 |
T110 |
14311 |
47 |
0 |
0 |
T118 |
9476 |
63 |
0 |
0 |
T120 |
11266 |
110 |
0 |
0 |
T121 |
3372 |
21 |
0 |
0 |
T139 |
11756 |
19 |
0 |
0 |
T145 |
13400 |
31 |
0 |
0 |
T146 |
102637 |
1076 |
0 |
0 |
T147 |
78714 |
161 |
0 |
0 |
T148 |
101817 |
808 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2237 |
0 |
0 |
T97 |
105311 |
203 |
0 |
0 |
T110 |
14311 |
22 |
0 |
0 |
T118 |
9476 |
12 |
0 |
0 |
T120 |
11266 |
13 |
0 |
0 |
T139 |
11756 |
35 |
0 |
0 |
T145 |
13400 |
20 |
0 |
0 |
T146 |
102637 |
180 |
0 |
0 |
T147 |
78714 |
118 |
0 |
0 |
T148 |
101817 |
202 |
0 |
0 |
T149 |
11026 |
19 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1970 |
0 |
0 |
T97 |
105311 |
158 |
0 |
0 |
T110 |
14311 |
27 |
0 |
0 |
T118 |
9476 |
13 |
0 |
0 |
T120 |
11266 |
19 |
0 |
0 |
T139 |
11756 |
36 |
0 |
0 |
T145 |
13400 |
14 |
0 |
0 |
T146 |
102637 |
146 |
0 |
0 |
T147 |
78714 |
133 |
0 |
0 |
T148 |
101817 |
169 |
0 |
0 |
T149 |
11026 |
8 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2077 |
0 |
0 |
T97 |
105311 |
190 |
0 |
0 |
T110 |
14311 |
19 |
0 |
0 |
T118 |
9476 |
6 |
0 |
0 |
T120 |
11266 |
11 |
0 |
0 |
T121 |
3372 |
3 |
0 |
0 |
T139 |
11756 |
22 |
0 |
0 |
T145 |
13400 |
22 |
0 |
0 |
T146 |
102637 |
182 |
0 |
0 |
T147 |
78714 |
141 |
0 |
0 |
T148 |
101817 |
164 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2104 |
0 |
0 |
T97 |
105311 |
178 |
0 |
0 |
T110 |
14311 |
20 |
0 |
0 |
T118 |
9476 |
18 |
0 |
0 |
T120 |
11266 |
21 |
0 |
0 |
T139 |
11756 |
42 |
0 |
0 |
T145 |
13400 |
28 |
0 |
0 |
T146 |
102637 |
175 |
0 |
0 |
T147 |
78714 |
163 |
0 |
0 |
T148 |
101817 |
168 |
0 |
0 |
T149 |
11026 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2794 |
0 |
0 |
T97 |
105311 |
269 |
0 |
0 |
T110 |
14311 |
17 |
0 |
0 |
T118 |
9476 |
26 |
0 |
0 |
T120 |
11266 |
42 |
0 |
0 |
T121 |
3372 |
4 |
0 |
0 |
T139 |
11756 |
33 |
0 |
0 |
T145 |
13400 |
57 |
0 |
0 |
T146 |
102637 |
238 |
0 |
0 |
T147 |
78714 |
121 |
0 |
0 |
T148 |
101817 |
282 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
5494 |
0 |
0 |
T22 |
195880 |
42 |
0 |
0 |
T30 |
0 |
24 |
0 |
0 |
T46 |
330268 |
0 |
0 |
0 |
T150 |
0 |
22 |
0 |
0 |
T151 |
0 |
33 |
0 |
0 |
T152 |
0 |
12 |
0 |
0 |
T153 |
0 |
59 |
0 |
0 |
T154 |
0 |
69 |
0 |
0 |
T155 |
0 |
9 |
0 |
0 |
T156 |
0 |
38 |
0 |
0 |
T157 |
0 |
48 |
0 |
0 |
T158 |
7918 |
0 |
0 |
0 |
T159 |
18528 |
0 |
0 |
0 |
T160 |
10219 |
0 |
0 |
0 |
T161 |
227543 |
0 |
0 |
0 |
T162 |
185593 |
0 |
0 |
0 |
T163 |
1489 |
0 |
0 |
0 |
T164 |
687637 |
0 |
0 |
0 |
T165 |
836 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2191 |
0 |
0 |
T97 |
105311 |
169 |
0 |
0 |
T110 |
14311 |
19 |
0 |
0 |
T118 |
9476 |
33 |
0 |
0 |
T120 |
11266 |
28 |
0 |
0 |
T139 |
11756 |
34 |
0 |
0 |
T145 |
13400 |
60 |
0 |
0 |
T146 |
102637 |
164 |
0 |
0 |
T147 |
78714 |
142 |
0 |
0 |
T148 |
101817 |
194 |
0 |
0 |
T149 |
11026 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2123 |
0 |
0 |
T95 |
7436 |
8 |
0 |
0 |
T97 |
105311 |
150 |
0 |
0 |
T110 |
14311 |
12 |
0 |
0 |
T118 |
9476 |
32 |
0 |
0 |
T120 |
11266 |
15 |
0 |
0 |
T139 |
11756 |
11 |
0 |
0 |
T145 |
13400 |
96 |
0 |
0 |
T146 |
102637 |
151 |
0 |
0 |
T147 |
78714 |
134 |
0 |
0 |
T148 |
101817 |
157 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1540 |
0 |
0 |
T97 |
105311 |
104 |
0 |
0 |
T110 |
14311 |
6 |
0 |
0 |
T118 |
9476 |
16 |
0 |
0 |
T120 |
11266 |
10 |
0 |
0 |
T139 |
11756 |
34 |
0 |
0 |
T145 |
13400 |
28 |
0 |
0 |
T146 |
102637 |
97 |
0 |
0 |
T147 |
78714 |
139 |
0 |
0 |
T148 |
101817 |
85 |
0 |
0 |
T149 |
11026 |
13 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1830 |
0 |
0 |
T97 |
105311 |
130 |
0 |
0 |
T110 |
14311 |
10 |
0 |
0 |
T118 |
9476 |
9 |
0 |
0 |
T120 |
11266 |
5 |
0 |
0 |
T139 |
11756 |
13 |
0 |
0 |
T145 |
13400 |
57 |
0 |
0 |
T146 |
102637 |
111 |
0 |
0 |
T147 |
78714 |
137 |
0 |
0 |
T148 |
101817 |
115 |
0 |
0 |
T149 |
11026 |
24 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1630 |
0 |
0 |
T97 |
105311 |
112 |
0 |
0 |
T110 |
14311 |
13 |
0 |
0 |
T118 |
9476 |
6 |
0 |
0 |
T120 |
11266 |
11 |
0 |
0 |
T139 |
11756 |
44 |
0 |
0 |
T145 |
13400 |
39 |
0 |
0 |
T146 |
102637 |
119 |
0 |
0 |
T147 |
78714 |
128 |
0 |
0 |
T148 |
101817 |
84 |
0 |
0 |
T149 |
11026 |
20 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1710 |
0 |
0 |
T97 |
105311 |
110 |
0 |
0 |
T110 |
14311 |
11 |
0 |
0 |
T118 |
9476 |
9 |
0 |
0 |
T120 |
11266 |
14 |
0 |
0 |
T121 |
3372 |
6 |
0 |
0 |
T139 |
11756 |
29 |
0 |
0 |
T145 |
13400 |
33 |
0 |
0 |
T146 |
102637 |
112 |
0 |
0 |
T147 |
78714 |
137 |
0 |
0 |
T148 |
101817 |
131 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2916 |
0 |
0 |
T97 |
105311 |
250 |
0 |
0 |
T110 |
14311 |
18 |
0 |
0 |
T118 |
9476 |
21 |
0 |
0 |
T120 |
11266 |
38 |
0 |
0 |
T121 |
3372 |
3 |
0 |
0 |
T139 |
11756 |
19 |
0 |
0 |
T145 |
13400 |
62 |
0 |
0 |
T146 |
102637 |
295 |
0 |
0 |
T147 |
78714 |
148 |
0 |
0 |
T148 |
101817 |
302 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1601 |
0 |
0 |
T97 |
105311 |
119 |
0 |
0 |
T110 |
14311 |
14 |
0 |
0 |
T118 |
9476 |
19 |
0 |
0 |
T120 |
11266 |
8 |
0 |
0 |
T121 |
3372 |
6 |
0 |
0 |
T139 |
11756 |
12 |
0 |
0 |
T145 |
13400 |
26 |
0 |
0 |
T146 |
102637 |
82 |
0 |
0 |
T147 |
78714 |
145 |
0 |
0 |
T148 |
101817 |
109 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
3495 |
0 |
0 |
T97 |
105311 |
316 |
0 |
0 |
T110 |
14311 |
37 |
0 |
0 |
T118 |
9476 |
32 |
0 |
0 |
T120 |
11266 |
76 |
0 |
0 |
T121 |
3372 |
6 |
0 |
0 |
T145 |
13400 |
128 |
0 |
0 |
T146 |
102637 |
338 |
0 |
0 |
T147 |
78714 |
140 |
0 |
0 |
T148 |
101817 |
382 |
0 |
0 |
T149 |
11026 |
31 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
2166 |
0 |
0 |
T97 |
105311 |
171 |
0 |
0 |
T110 |
14311 |
6 |
0 |
0 |
T118 |
9476 |
21 |
0 |
0 |
T120 |
11266 |
15 |
0 |
0 |
T121 |
3372 |
1 |
0 |
0 |
T139 |
11756 |
10 |
0 |
0 |
T145 |
13400 |
63 |
0 |
0 |
T146 |
102637 |
198 |
0 |
0 |
T147 |
78714 |
171 |
0 |
0 |
T148 |
101817 |
168 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1781 |
0 |
0 |
T97 |
105311 |
112 |
0 |
0 |
T110 |
14311 |
23 |
0 |
0 |
T118 |
9476 |
13 |
0 |
0 |
T120 |
11266 |
16 |
0 |
0 |
T121 |
3372 |
2 |
0 |
0 |
T139 |
11756 |
9 |
0 |
0 |
T145 |
13400 |
32 |
0 |
0 |
T146 |
102637 |
128 |
0 |
0 |
T147 |
78714 |
116 |
0 |
0 |
T148 |
101817 |
120 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1571 |
0 |
0 |
T97 |
105311 |
107 |
0 |
0 |
T110 |
14311 |
9 |
0 |
0 |
T118 |
9476 |
10 |
0 |
0 |
T120 |
11266 |
14 |
0 |
0 |
T139 |
11756 |
9 |
0 |
0 |
T145 |
13400 |
41 |
0 |
0 |
T146 |
102637 |
92 |
0 |
0 |
T147 |
78714 |
165 |
0 |
0 |
T148 |
101817 |
124 |
0 |
0 |
T149 |
11026 |
12 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1605 |
0 |
0 |
T97 |
105311 |
98 |
0 |
0 |
T118 |
9476 |
7 |
0 |
0 |
T120 |
11266 |
12 |
0 |
0 |
T125 |
7318 |
11 |
0 |
0 |
T139 |
11756 |
19 |
0 |
0 |
T145 |
13400 |
46 |
0 |
0 |
T146 |
102637 |
125 |
0 |
0 |
T147 |
78714 |
145 |
0 |
0 |
T148 |
101817 |
116 |
0 |
0 |
T149 |
11026 |
16 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1540 |
0 |
0 |
T97 |
105311 |
105 |
0 |
0 |
T110 |
14311 |
17 |
0 |
0 |
T118 |
9476 |
9 |
0 |
0 |
T120 |
11266 |
11 |
0 |
0 |
T139 |
11756 |
6 |
0 |
0 |
T145 |
13400 |
38 |
0 |
0 |
T146 |
102637 |
111 |
0 |
0 |
T147 |
78714 |
114 |
0 |
0 |
T148 |
101817 |
116 |
0 |
0 |
T149 |
11026 |
20 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1671 |
0 |
0 |
T97 |
105311 |
111 |
0 |
0 |
T110 |
14311 |
24 |
0 |
0 |
T118 |
9476 |
15 |
0 |
0 |
T120 |
11266 |
10 |
0 |
0 |
T139 |
11756 |
1 |
0 |
0 |
T145 |
13400 |
53 |
0 |
0 |
T146 |
102637 |
107 |
0 |
0 |
T147 |
78714 |
104 |
0 |
0 |
T148 |
101817 |
154 |
0 |
0 |
T149 |
11026 |
8 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
451291024 |
1542 |
0 |
0 |
T97 |
105311 |
114 |
0 |
0 |
T110 |
14311 |
15 |
0 |
0 |
T118 |
9476 |
6 |
0 |
0 |
T120 |
11266 |
10 |
0 |
0 |
T139 |
11756 |
15 |
0 |
0 |
T145 |
13400 |
54 |
0 |
0 |
T146 |
102637 |
123 |
0 |
0 |
T147 |
78714 |
106 |
0 |
0 |
T148 |
101817 |
115 |
0 |
0 |
T149 |
11026 |
21 |
0 |
0 |