Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3176886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4212699

1

T1

103

T2

13

T3

20632

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4042752	1			T1	101		T2	1		T3	18765
values[0x0]	1674316	1			T1	47		T2	8		T3	10083
values[0x1]	1672517	1			T1	53		T2	8		T3	9901

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2279883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5109702

1

T1

157

T2

13

T3

26418

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26598	1			T3	151		T4	9		T5	424
valid_sources[0x01]	26812	1			T1	3		T3	159		T4	1
valid_sources[0x02]	30907	1			T3	157		T6	44		T8	1
valid_sources[0x03]	24892	1			T3	159		T4	1		T5	2
valid_sources[0x04]	27170	1			T1	1		T3	147		T4	4
valid_sources[0x05]	25432	1			T1	1		T3	150		T4	4
valid_sources[0x06]	29403	1			T3	151		T4	4		T5	1520
valid_sources[0x07]	26786	1			T1	1		T3	157		T4	2
valid_sources[0x08]	26836	1			T1	1		T3	142		T4	2
valid_sources[0x09]	28277	1			T3	143		T4	12		T5	1
valid_sources[0x0a]	28848	1			T1	3		T3	157		T4	8
valid_sources[0x0b]	27664	1			T1	1		T3	170		T4	6
valid_sources[0x0c]	26121	1			T3	138		T4	2		T5	2
valid_sources[0x0d]	28030	1			T3	135		T4	3		T6	98
valid_sources[0x0e]	27451	1			T3	160		T4	9		T5	47
valid_sources[0x0f]	25993	1			T3	149		T4	3		T6	15
valid_sources[0x10]	30093	1			T1	3		T3	159		T4	2
valid_sources[0x11]	26416	1			T1	2		T3	146		T4	5
valid_sources[0x12]	27218	1			T3	139		T4	14		T5	1
valid_sources[0x13]	25039	1			T3	171		T6	79		T8	10
valid_sources[0x14]	25164	1			T2	1		T3	167		T6	96
valid_sources[0x15]	28073	1			T3	155		T4	1		T5	44
valid_sources[0x16]	28373	1			T3	160		T4	8		T5	418
valid_sources[0x17]	26098	1			T3	136		T4	2		T5	1
valid_sources[0x18]	25507	1			T3	161		T4	4		T5	36
valid_sources[0x19]	26771	1			T3	145		T4	7		T5	32
valid_sources[0x1a]	30300	1			T3	165		T4	3		T6	6
valid_sources[0x1b]	57505	1			T3	148		T4	11		T6	12
valid_sources[0x1c]	30337	1			T3	150		T4	3		T5	136
valid_sources[0x1d]	25850	1			T3	165		T4	4		T5	1
valid_sources[0x1e]	28568	1			T1	5		T3	158		T4	2
valid_sources[0x1f]	32961	1			T3	145		T4	1		T5	1
valid_sources[0x20]	26475	1			T3	163		T4	6		T5	1
valid_sources[0x21]	26669	1			T3	145		T4	13		T5	281
valid_sources[0x22]	26981	1			T3	152		T4	4		T6	27
valid_sources[0x23]	32343	1			T3	143		T5	652		T6	71
valid_sources[0x24]	24013	1			T2	2		T3	160		T4	3
valid_sources[0x25]	26068	1			T3	144		T4	2		T5	83
valid_sources[0x26]	27784	1			T3	156		T4	4		T6	192
valid_sources[0x27]	27141	1			T3	155		T4	6		T5	352
valid_sources[0x28]	27178	1			T3	138		T4	9		T6	16
valid_sources[0x29]	26999	1			T3	153		T4	7		T5	7
valid_sources[0x2a]	25693	1			T1	1		T3	145		T4	7
valid_sources[0x2b]	26802	1			T3	159		T4	2		T5	4
valid_sources[0x2c]	28342	1			T3	131		T4	1		T5	1
valid_sources[0x2d]	30241	1			T1	1		T3	139		T4	3
valid_sources[0x2e]	35284	1			T3	160		T4	5		T8	2
valid_sources[0x2f]	34348	1			T1	1		T3	147		T4	4
valid_sources[0x30]	27021	1			T3	174		T4	1		T5	128
valid_sources[0x31]	27721	1			T1	1		T2	1		T3	132
valid_sources[0x32]	29081	1			T3	140		T4	5		T5	2
valid_sources[0x33]	27625	1			T3	144		T6	417		T8	2
valid_sources[0x34]	25381	1			T1	3		T3	136		T5	11
valid_sources[0x35]	26094	1			T3	165		T6	49		T8	4
valid_sources[0x36]	28297	1			T3	133		T4	4		T6	10
valid_sources[0x37]	30181	1			T2	1		T3	138		T4	9
valid_sources[0x38]	28110	1			T3	155		T4	3		T5	74
valid_sources[0x39]	26886	1			T1	1		T3	158		T4	3
valid_sources[0x3a]	29057	1			T1	1		T3	158		T4	4
valid_sources[0x3b]	28195	1			T3	169		T4	8		T6	68
valid_sources[0x3c]	26894	1			T3	132		T6	5		T8	4
valid_sources[0x3d]	29469	1			T1	1		T3	149		T5	121
valid_sources[0x3e]	26831	1			T3	156		T4	2		T5	147
valid_sources[0x3f]	28019	1			T3	145		T4	2		T6	11
valid_sources[0x40]	27366	1			T3	147		T4	2		T5	10
valid_sources[0x41]	25634	1			T2	4		T3	134		T4	2
valid_sources[0x42]	27737	1			T3	151		T5	21		T6	44
valid_sources[0x43]	27578	1			T1	2		T3	158		T5	4
valid_sources[0x44]	46001	1			T3	162		T4	4		T5	76
valid_sources[0x45]	28140	1			T3	135		T4	1		T5	3
valid_sources[0x46]	27591	1			T3	155		T4	11		T5	5
valid_sources[0x47]	26766	1			T3	159		T4	6		T5	89
valid_sources[0x48]	31999	1			T3	144		T5	37		T6	1
valid_sources[0x49]	27032	1			T1	3		T3	167		T4	18
valid_sources[0x4a]	24816	1			T3	163		T4	4		T5	12
valid_sources[0x4b]	41099	1			T3	150		T4	9		T5	10
valid_sources[0x4c]	26247	1			T3	153		T5	32		T6	2
valid_sources[0x4d]	30503	1			T3	132		T4	8		T5	1
valid_sources[0x4e]	25463	1			T3	143		T4	2		T5	8
valid_sources[0x4f]	27033	1			T3	179		T4	1		T8	6
valid_sources[0x50]	27368	1			T1	2		T3	174		T4	3
valid_sources[0x51]	27517	1			T2	1		T3	154		T4	1
valid_sources[0x52]	27034	1			T3	158		T4	1		T5	1
valid_sources[0x53]	29861	1			T3	146		T4	4		T6	48
valid_sources[0x54]	30808	1			T1	1		T3	123		T4	2
valid_sources[0x55]	29636	1			T3	121		T4	11		T6	2
valid_sources[0x56]	28448	1			T3	154		T4	4		T5	1
valid_sources[0x57]	28430	1			T3	145		T5	18		T6	35
valid_sources[0x58]	26631	1			T1	1		T3	151		T6	2
valid_sources[0x59]	27004	1			T3	143		T4	2		T5	1
valid_sources[0x5a]	30434	1			T3	168		T4	3		T5	3
valid_sources[0x5b]	24090	1			T3	169		T5	158		T6	1
valid_sources[0x5c]	25786	1			T3	152		T4	3		T6	69
valid_sources[0x5d]	28522	1			T3	124		T4	1		T5	220
valid_sources[0x5e]	25898	1			T3	151		T6	127		T8	6
valid_sources[0x5f]	24969	1			T1	3		T3	140		T5	2
valid_sources[0x60]	25660	1			T3	132		T4	4		T5	54
valid_sources[0x61]	27980	1			T3	139		T4	1		T5	1476
valid_sources[0x62]	25069	1			T3	151		T5	1		T6	6
valid_sources[0x63]	31473	1			T1	1		T3	140		T8	1
valid_sources[0x64]	27197	1			T3	135		T4	7		T6	11
valid_sources[0x65]	26191	1			T3	147		T4	3		T5	101
valid_sources[0x66]	27634	1			T3	146		T4	7		T5	2
valid_sources[0x67]	30407	1			T3	166		T4	1		T5	69
valid_sources[0x68]	27096	1			T2	1		T3	168		T4	2
valid_sources[0x69]	26402	1			T3	175		T4	2		T6	18
valid_sources[0x6a]	26030	1			T1	3		T3	162		T4	3
valid_sources[0x6b]	31945	1			T3	154		T5	47		T8	3
valid_sources[0x6c]	48020	1			T3	154		T4	11		T5	1
valid_sources[0x6d]	28976	1			T3	149		T4	3		T5	1
valid_sources[0x6e]	32574	1			T3	177		T4	1		T5	1
valid_sources[0x6f]	28740	1			T1	14		T3	176		T5	4
valid_sources[0x70]	28412	1			T3	158		T6	1		T8	6
valid_sources[0x71]	25928	1			T3	167		T4	1		T6	20
valid_sources[0x72]	28326	1			T1	1		T3	159		T5	1
valid_sources[0x73]	30570	1			T1	11		T3	147		T5	5
valid_sources[0x74]	25793	1			T3	131		T4	4		T6	1
valid_sources[0x75]	29743	1			T3	152		T4	1		T5	1
valid_sources[0x76]	31852	1			T1	2		T3	142		T4	1
valid_sources[0x77]	58529	1			T2	2		T3	136		T4	4
valid_sources[0x78]	28585	1			T1	14		T3	130		T4	1
valid_sources[0x79]	27823	1			T3	138		T4	2		T6	71
valid_sources[0x7a]	25182	1			T3	171		T4	5		T5	1
valid_sources[0x7b]	34284	1			T3	147		T4	6		T5	7
valid_sources[0x7c]	28442	1			T3	158		T4	1		T5	28
valid_sources[0x7d]	27112	1			T3	136		T4	1		T5	305
valid_sources[0x7e]	29299	1			T1	2		T3	138		T4	6
valid_sources[0x7f]	35736	1			T3	152		T4	3		T5	12
valid_sources[0x80]	27559	1			T3	141		T4	7		T5	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1145575

1

T1

3

T2

1

T3

2376

values[0x0]

all_enables

biggest_size

1545670

1

T1

47

T2

5

T3

9235

values[0x1]

all_enables

biggest_size

1521454

1

T1

53

T2

7

T3

9021