Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3191927

1

T2

4

T3

18117

T4

3

full_word

4211434

1

T2

13

T3

20632

T4

880

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7402981	1			T2	17		T3	38749		T4	883
auto[TlIntgErrCmd]	122	1			T93	3		T96	10		T97	6
auto[TlIntgErrData]	144	1			T93	2		T96	14		T97	13
auto[TlIntgErrBoth]	114	1			T93	5		T96	6		T97	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4043275

1

T2

1

T3

18765

T4

4

auto[1]

3360086

1

T2

16

T3

19984

T4

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2897521	1			T3	16389		T4	1		T5	2725
auto[TlIntgErrNone]	partial	auto[1]	294060	1			T2	4		T3	1728		T4	2
auto[TlIntgErrNone]	full_word	auto[0]	1145577	1			T2	1		T3	2376		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	3065823	1			T2	12		T3	18256		T4	877
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T93	3		T96	3		T97	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T96	5		T97	3		T110	5
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T96	2		T170	1		T171	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T110	1		T167	1		-	-
auto[TlIntgErrData]	partial	auto[0]	66	1			T93	1		T96	6		T97	6
auto[TlIntgErrData]	partial	auto[1]	62	1			T93	1		T96	6		T97	6
auto[TlIntgErrData]	full_word	auto[0]	8	1			T96	1		T97	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T96	1		T110	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T93	3		T96	1		T97	6
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T93	2		T96	3		T97	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T96	1		T112	1		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T96	1		T110	1		T172	1