Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	3010603	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3010603	0	0
T1	3453	100	0	0
T2	2700	0	0	0
T3	272516	18325	0	0
T4	81008	1663	0	0
T5	563553	16634	0	0
T6	423824	15816	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	6663	0	0
T11	0	4409	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	3478193	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	3478193	0	0
T1	3453	468	0	0
T2	2700	0	0	0
T3	272516	22595	0	0
T4	81008	832	0	0
T5	563553	11648	0	0
T6	423824	11408	0	0
T7	100242	832	0	0
T8	496587	832	0	0
T9	183932	832	0	0
T10	290564	7612	0	0
T11	0	2624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	183772	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	183772	0	0
T1	3453	100	0	0
T2	2700	0	0	0
T3	272516	298	0	0
T4	81008	0	0	0
T5	563553	296	0	0
T6	423824	1067	0	0
T7	100242	0	0	0
T8	496587	0	0	0
T9	183932	0	0	0
T10	290564	195	0	0
T13	0	195	0	0
T15	0	1863	0	0
T23	0	87	0	0
T25	0	900	0	0
T32	0	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	431752	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	431752	0	0
T1	3453	481	0	0
T2	2700	0	0	0
T3	272516	1250	0	0
T4	81008	0	0	0
T5	563553	296	0	0
T6	423824	4617	0	0
T7	100242	0	0	0
T8	496587	0	0	0
T9	183932	0	0	0
T10	290564	597	0	0
T13	0	195	0	0
T15	0	1863	0	0
T23	0	87	0	0
T25	0	900	0	0
T32	0	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	5581334	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	5581334	0	0
T1	3453	1	0	0
T2	2700	17	0	0
T3	272516	30392	0	0
T4	81008	51	0	0
T5	563553	5711	0	0
T6	423824	11654	0	0
T7	100242	2976	0	0
T8	496587	60	0	0
T9	183932	2578	0	0
T10	290564	4507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	428630466	11260831	0	0
DepthKnown_A	428630466	428500890	0	0
RvalidKnown_A	428630466	428500890	0	0
WreadyKnown_A	428630466	428500890	0	0
gen_passthru_fifo.paramCheckPass	1149	1149	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	11260831	0	0
T1	3453	2	0	0
T2	2700	17	0	0
T3	272516	122060	0	0
T4	81008	51	0	0
T5	563553	5649	0	0
T6	423824	44721	0	0
T7	100242	2976	0	0
T8	496587	60	0	0
T9	183932	2578	0	0
T10	290564	13697	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	428630466	428500890	0	0
T1	3453	3396	0	0
T2	2700	2645	0	0
T3	272516	272507	0	0
T4	81008	80913	0	0
T5	563553	563316	0	0
T6	423824	423734	0	0
T7	100242	100189	0	0
T8	496587	496496	0	0
T9	183932	183923	0	0
T10	290564	290555	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149	1149	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0